ADM1033 D

ADM1033
Thermal Monitor and Fan
Speed (RPM) Controller
The ADM1033 is a one channel remote- and local-temperature
sensor and fan controller. The remote channel monitors the
temperature of the remote thermal diode, which may be discrete
2N3904/6s or may be located on a microprocessor die. The device also
monitors its own ambient temperature.
The ADM1033 can monitor and control the speed of cooling fan.
The user can program a target fan speed, or else use the look-up table
to input a temperature-to-fan speed profile. The look-up table can be
configured to run the fans at discrete speeds (discrete mode) or to ramp
the fan speed with temperature (linear mode).
The ADM1033 communicates over a 2-wire SMBus 2.0 interface.
An 8-level LOCATION input allows the user to choose between
SMBus 1.1 and SMBus 2.0. An ALERT output indicates error
conditions. The THERM I/O signals overtemperature as an output and
times THERM assertions as an input. Pin 8 can be configured as a
reference for the THERM (PROCHOT) input.
QSOP−16
CASE 492
PIN ASSIGNMENT
DRIVE1 1
16 SCL
TACH1 2
15 SDA
ALERT Comp 3
NC 4
Features
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GND 5
1 Local and Remote Temperature Channels
1C Accuracy on Local and Remote Channels
Automatic Remote Temperature Channel, Up to 1 kW
Fast (Up to 64 Measurements per Second)
SMBus 2.0, 1.1, and 1.0 Compliant
SMBus Address Input/LOCATION Input to UDID
Programmable Over/Undertemperature Limits
Programmable Fault Queue
SMBusALERT Output
Fail-Safe Overtemperature Comparator Output
Fan Speed (RPM) Controller
Look-up Table for Temperature-to-Fan Speed Control
Linear and Discrete Options for Look-up Table
FAN_FAULT Output
THERM Input, Used to Time PROCHOT Assertions
REF Input, Used as Reference for THERM (PROCHOT)
3.0 V to 5.5 V Supply
Small 16-lead QSOP Package
This is a Pb-Free Device*
14 ALERT
ADM1033
VCC 6
13 LOCATION
12 NC
11 NC
THERM 7
10 D1+
FAN_FAULT/REF 8
9 D1−
(Top View)
MARKING DIAGRAM
1033A
RQZ
#YYWW
1033ARQZ
#
YY
WW
= Specific Device Code
= Pb-Free Package
= Date Code
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 34 of this data sheet.
Applications




Desktop and Notebook PCs
Embedded Systems
Telecommunications Equipment
LCD Projectors
* For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 3
1
Publication Order Number:
ADM1033/D
ADM1033
VCC
6
ADM1033
SMBUS
ADDRESS
DRIVE
1
TACH
2
STATUS
REGISTER
ENHANCE
ACOUSTICS
SRC
BLOCK
ALERT Comp
14 SMBusALERT
7
THERM
THERM PERCENT
TIMER
OFFSET
REGISTERS
ANALOG
MULTIPLEXER
CONVERSION
RATE
REGISTER
BAND GAP
REFERENCE
NC 11
NC 12
FAN_FAULT
3
HYSTERESIS
REGISTERS
ADC
D+ 10
FAULT
QUEUE
8
FAULT
QUEUE
8
D− 9
MASK
REGISTERS
THERM
VALUE AND
LIMIT
REGISTERS
LOCATION 13
REF
ALERT
LIMIT
COMPARATOR
FAN
SPEED
COUNTER
SIGNAL
CONDITIONING
15 SDA
ADDRESS
POINTER
REGISTER
TEMPERATURE
TO FAN SPEED
LOOK-UP TABLE
RPM FAN
SPEED
CONTROLLER
16 SCL
SERIAL BUS
INTERFACE
MANUAL FAN
SPEED CONTROL
REGISTERS
BAND GAP
TEMPERATURE
SENSOR
CONFIGURATION
REGISTERS
5
NC = NO CONNECT
GND
Figure 1. Functional Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Positive Supply Voltage (VCC)
Voltage on Any Input or Output Pin except FAN_FAULT and LOCATION
Voltage on FAN_FAULT (Note 1)
Rating
Unit
−0.3, +6.5
V
−0.3 to VDD + 6.5
V
VCC
Voltage on LOCATION
VCC + 0.3
V
Input Current at Any Pin
20
mA
Maximum Junction Temperature (TJ MAX)
150
C
Storage Temperature Range
−65 to +150
C
Lead Temperature, Soldering (10 s)
300
C
IR Reflow Peak Temperature
220
C
ESD Rating − All Pins
1500
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. During powerup the voltage on FAN_FAULT should not be higher than VCC.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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ADM1033
Table 2. THERMAL CHARACTERISTICS
Package Type
16-lead QSOP Package
qJA
qJC
Unit
150
39
C/W
Table 3. PIN ASSIGNMENT
Pin No.
Mnemonic
1
DRIVE1
DRIVE1 Pin Drives Fan 1. Open-drain output. Requires a pullup resistor.
Description
2
TACH1
Fan 1 Fan Speed Measurement Input. Connects to the fan’s TACH output to measure the fan speed.
3
ALERT Comp
Open-Drain Active Low Output. Assets low whenever a measurement goes outside its programmed
limits if not masked. Automatically goes high again when the measured parameter falls back within its
limits.
4
NC
5
GND
No Connect.
Ground for Analog and Digital Circuitry.
6
VCC
Power. Can be powered by 3.3 V standby power if monitoring in low power states is required.
7
THERM
8
FAN_FAULT/R
EF
9
D1−
Cathode Connection for the First Thermal Diode or Diode-Connected Transistor.
10
D1+
Anode Connection for the First Thermal Diode or Diode-Connected Transistor.
11
NC
No Connect.
12
NC
No Connect.
13
LOCATION
14
ALERT
Open-Drain Output. SMBusALERT pin. Alerts the system in the case of out-of-limit events, such as
over temperature. Can be configured as sticky SMBus mode or comparator mode.
15
SDA
Serial Bus Bidirectional Data. Connects to the SMBus master’s data line. Requires pullup resistor if
not provided elsewhere in the system.
16
SCL
Serial SMBus Clock Input. Connects to the SMBus master’s clock line. Requires pullup resistor if not
already provided in the system.
Can be configured as an overtemperature interrupt output, or as an input (to monitor PROCHOT output
of an INTEL CPU). A timer measures assertion times on the THERM pin (either input or output).
FAN_FAULT: Open-Drain Output. Asserted low when one or both fans stall. Requires a pullup
resistor to VCC. REF: Analog Input Reference for the THERM Input.
8-level Analog Input. Used to determine the correct SMBus version and the SMBus address (in fixed
and discoverable mode) and to set the LLL bits in the UDID (in ARP-capable mode).
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ADM1033
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
3.0
3.30
3.6
V
Interface inactive, ADC Active
−
−
3.0
mA
Standby Mode
−
−
900
mA
−
2.5
−
V
1.0
−
2.4
V
−
−4.0
1.0
−
2.0
+2.0
C
−
0.03125
−
C
−
−
−3.0
0.5
1.0
−
1.0
1.25
+2.0
C
−
0.03125
−
C
−
−
−
85
34
5.0
−
−
−
mA
−
−
1000
W
Power Supply
Supply Voltage, VCC (Note 2)
Supply Current, ICC
Undervoltage Lockout Threshold
Power-On Reset Threshold
Temperature-to-Digital Converter
Internal Sensor Accuracy
20C  TA  60C
−40C  TA  +100C
Resolution
External Diode Sensor Accuracy
−40C  TD  +100C; TA = +40C
−40C  TD  +100C; +20C  TA  +60C
−40C  TD  +100C; −40C  TA  +100C
Resolution
Remote Sensor Source Current
High Level
Mid Level
Low Level
Series Resistance Cancellation
Power Supply Sensitivity
−
1.0
−
%/V
Conversion Time (Local Temperature)
Averaging Enabled
−
11
−
ms
Conversion Time (Remote Temperature)
Averaging Enabled
−
32
−
ms
Total Conversion Time
Averaging Enabled
−
43
−
ms
Open-Drain Digital Outputs (ALERT, THERM, FAN_FAULT, DRIVE1, DRIVE2) (Note 3)
Output Low Voltage, VOL
IOUT = −6.0 mA; VCC = +3.0 V
−
−
0.4
V
High Level Output Leakage Current, IOH
VOUT = VCC; VCC = 3.0 V
−
0.1
1.0
mA
−1.0
−
−
mA
−
−
1.0
mA
−
7.0
−
pF
Input High Voltage, VIH
2.0
−
5.5
V
Input Low Voltage, VIL
−0.3
−
+0.8
V
−
500
−
mV p−p
Digital Input Leakage Current (TACH1, TACH2)
Input High Current, IIH
−VIN = VCC
Input Low Current, IIL
VIN = 0
Input Capacitance, CIN
Digital Input Logic Levels (TACH1, TACH2)
Hysteresis
Open-Drain Serial Data Bus Output (SDA)
Output Low Voltage, VOL
IOUT = −6.0 mA; VCC
−
−
0.4
V
High Level Output Leakage Current, IOH
VOUT = VCC
−
0.1
1.0
mA
Input High Voltage, VIH
2.1
−
−
V
Input Low Voltage, VIL
−
−
0.8
V
Hysteresis
−
500
−
mV
80
125
160
kW
−
−
4.0
%
Serial Bus Digital Inputs (SCL, SDA)
Analog Inputs (Location, REF)
Input Resistance
Tachometer Accuracy
Fan Speed Measurement Accuracy
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ADM1033
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Input High Level
−
0.75 x
REF
−
V
Input Low Level
−
−
0.4
V
AGTL + INPUT (THERM)
SERIAL BUS TIMING (Note 4)
−
−
400
kHz
Glitch Immunity, tSW
See Figure 2 for All Parameters
−
50
−
ns
Bus Free Time, tBUF
1.3
−
−
ms
Start Setup Time, tSU:STA
0.6
−
−
ms
Start Hold Time, tHD:STA
0.6
−
−
ms
Stop Condition Setup Time tSU:STO
0.6
−
−
ms
SCL Low Time, tLOW
1.3
−
−
ms
SCL High Time, tHIGH
0.6
−
−
ms
−
−
1000
ns
Clock Frequency, fSCLK
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU:DAT
Detect Clock Low Timeout, tTIMEOUT
(Note 5)
−
−
300
ns
100
−
−
ns
25
−
35
ms
1. Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
2. Operation at 5.5 V is guaranteed by design, not production tested.
3. Recommend use of 100 kW pullup resistors for all open-drain outputs from the ADM1033.
4. Guaranteed by design, not production tested.
5. SMBus timeout disabled by default. See the SMBus section for more information.
t LOW
tF
t HD; STA
tR
SCL
t HD; STA
t HD; DAT
t HIGH
t SU; STA
t SU; DAT
t SU; STO
SDA
P
t BUF
S
S
Figure 2. Serial Bus Timing Diagram
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P
ADM1033
40
0
20
−10
TEMPERATURE ERROR (C)
TEMPERATURE ERROR (C)
TYPICAL PERFORMANCE CHARACTERISTICS
D+ TO GND
0
D+ TO VCC
−20
−40
−60
−80
−100
0
10
20
30
40
50
60
70
80
−30
−40
DEV 31 (C)
−50
DEV 32 (C)
−60
−70
−80
90 100
DEV 33 (C)
−20
0
2
LEAKAGE RESISTANCE (MW)
Figure 3. Temperature Error vs. PCB Track
Resistance DXP to GND and VCC
20
DEV 33
80
TEMPERATURE ERROR (C)
TEMPERATURE ERROR (C)
90
70
60
50
DEV 31
40
30
20
10
DEV 32
0
−10
1
2
3
4
5
0
−5
−10
6
0
1M
TEMPERATURE ERROR (C)
3.5
40
35
30
100 mV
20
20 mV
50 mV
0
1M
2M
3M
4M
3M
4M
5M
6M
FREQUENCY (Hz)
4.0
5
2M
Figure 6. Remote Temperature Error vs.
Power Supply Noise Frequency
45
10
12
5
50
15
10
10
SERIES RESISTANCE IN D+/D− (kW)
25
8
EXT 100 mVpp
EXT 250 mVpp
15
Figure 5. Remote Temperature Error vs.
Series Resistance on D+ and D−
TEMPERATURE ERROR (C)
6
Figure 4. Remote Temperature Error vs.
D+, D− Capacitance
100
0
4
CAPACITANCE (nF)
5M
10 mV
20 mV
3.0
2.5
2.0
1.5
1.0
0.5
0
6M
NOISE FREQUENCY (Hz)
0
1M
2M
3M
4M
5M
NOISE FREQUENCY (Hz)
Figure 8. Remote Temperature Error vs.
Differential Mode Noise Frequency Coupled
on D+ and D−
Figure 7. Remote Temperature Error vs.
Common-Mode Noise Frequency Coupled
on D+ and D−
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6M
ADM1033
TYPICAL PERFORMANCE CHARACTERISTICS (Cont’d)
2
2
1
HIGH 4 SIGMA
0
0
−1
−1
ERROR (C)
TEMPERATURE ERROR (C)
1
−2
−3
MEAN
−4
S1
S2
S3
S4
S5
−5
−6
V1
V2
V3
V4
V5
−7
−60 −40 −20
0
20
HIGH 4 SIGMA
−2
−3
MEAN
−4
S1
S2
S3
S4
S5
−5
−6
LOW 4 SIGMA
40
60
−7
−50
80 100 120 140
0
TEMPERATURE (C)
420
0.6
ICC (mA)
410
STANDBY SUPPLY CURRENT
0.7
DEV 31
400
DEV 33
390
380
DEV 32
370
10
100
0.3
0.2
0.1
0
1000
0
1
1.50
SUPPLY CURRENT
1000
ICC (mA)
800
DEV 31
400
DEV 32
0.1
1
3
4
5
6
SUPPLY VOLTAGE (V)
1.55
0
0.01
2
Figure 12. Standby Supply Current vs.
Supply Voltage
1200
DEV 33
150
0.4
Figure 11. Standby Supply Current vs.
SCLK Frequency
200
100
0.5
FSCL (kHz)
600
50
Figure 10. Local Temperature Error vs.
Actual Temperature
430
1
LOW 4 SIGMA
TEMPERATURE (C)
Figure 9. Remote 1 Temperature Error vs.
Actual Temperature
360
V1
V2
V3
V4
V5
1.45
1.40
1.35
1.30
10
1.25
−60
100
CONVERSION RATE (Hz)
−40
−20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 13. Supply Current vs. Conversion Rate
Figure 14. Supply Current vs. ADM1033 Temperature
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ADM1033
Functional Description
and digitized by the on-chip ADC to determine the
LOCATION input value. Because the LOCATION input is
sampled only at powerup, changes made while power is
applied have no effect.
The ADM1033 is a local- and remote-temperature
monitor and fan controller for use in a variety of
applications, including microprocessor-based systems. The
device accurately monitors remote and ambient temperature
and uses that information to quietly control the speed of a
cooling fan. Whenever a fan stalls, the device asserts a
FAN_FAULT output.
The ADM1033 features a THERM I/O. As an input, this
measures assertions on the THERM pin. As an output, it
asserts a low signal to indicate when the measured
temperature exceeds the programmed THERM temperature.
The ADM1033 communicates over an SMBus 2.0 interface.
Its LOCATION input determines which version of SMBus to
use, as well as the SMBus address (in fixed and discoverable
mode) and the LOCATION bits in the UDID (in ARP-capable
mode).
SMBus 2.0 ARP-Capable Mode
In ARP-capable mode, the ADM1033 supports features
such as address resolution protocol (ARP) and unique device
identifier (UDID). The UDID is a 128-bit message that
describes the ADM1033’s capabilities to the master. The
UDID also includes a vendor specific ID for functionally
equivalent devices.
VCC
ARP
LOCATION = 111
1.5 kW
ARP
LOCATION = 110
Internal Registers
ARP
LOCATION = 101
ADM1033 3
1 kW
ARP
LOCATION = 100
Serial Bus Interface
The ADM1033 communicates with the master via the
2-wire SMBus 2.0 interface. It supports two versions of
SMBus 2.0, determined by the value of the LOCATION
input’s resistors.
The first version is fully ARP-capable. This means that it
supports address resolution protocol (ARP), allowing the
master to dynamically address the device on powerup. It
responds to ARP commands such as “Prepare to ARP.”
The second SMBus version, fixed and discoverable, is
backwards compatible with SMBus 1.0 and 1.1. In this mode,
the ADM1033 powers up with a fixed address, which is
determined by the state of the LOCATION pin on powerup.
FD
ADDRESS = 53h
ADM1033 4
1 kW
ADM1033 5
1 kW
FD
ADDRESS = 52h
ADM1033 6
1 kW
FD
ADDRESS = 51h
FD
ADDRESS = 50h
ADM1033 7
1.5 kW
ADM1033 8
GND
NOTE: When using the ADM1033, Addresses 0xC2 and 0xCA should
not be used by any other device on the bus.
Figure 16. Setting Up Multiple ADM1033 Addresses
in SMBus 2.0 ARP-capable Mode
Location Input
The LOCATION input is a resistor divider input. It has
multiple functions and can specify the SMBus version (in
fixed and discoverable or ARP-capable modes); the SMBus
address (in fixed and discoverable mode); and the LLL bits
(in UDID in ARP-capable mode).
In SMBus 2.0 mode, this vendor specific ID is generated
by an on-chip random number generator. This should enable
two adjacent ADM1033s in the same system to powerup
with a different vendor specific ID, allowing the master to
identify the two separate ADM1033’s and assign a different
address to each.
The state of the LOCATION input on powerup is also
reflected in the UDID. This is useful when there is more than
one ADM1033 in the system, so the master knows which one
it is communicating with. The complete UDID is listed in
Table 7.
The SMBus 2.0 master issues both general and directed
ARP commands. A general command is directed at all ARP
devices. A directed command is targeted at a single device
once an address has been established. The PEC byte must be
used for ARP commands. (Refer to the Packet Error
Checking (PEC) section.)
VCC
ADM1033
PIN 13
ADM1033 2
1 kW
Table 5 gives a brief description of the ADM1033’s
principal internal registers. For more detailed information
on the function of each register, refer to Table 35.
R1
ADM1033 1
LOCATION
R2
GND
Figure 15. Bootstrapping the LOCATION Input
The voltage of this 8-level input is set by a potential
divider. The voltage on LOCATION is sampled on powerup
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ADM1033
The ADM1033 responds to the following commands:
 Prepare to ARP (General)
 Reset Device (General and Directed)
 Get UDID (General and Directed)
 Assign Address (General)
Table 5. INTERNAL REGISTER DESCRIPTIONS
Register
Description
Configuration
Provides control and configuration of various functions on the device.
Conversion Rate
Determines the number of measurements per second completed by the ADM1033.
Address Pointer
Contains the address that selects one of the other internal registers. When writing to the ADM1033,
the first byte of data is always a register address, written to the address pointer register.
Status
Provides the status of each limit comparison.
Interrupt Mask
Allows the option to mask ALERTs due to particular out-of-limit conditions.
Value and Limit
Stores the results of temperature and fan speed measurements, along with their limit values.
Offset
Allows the local and remote temperature channel readings to be offset by a twos complement value
written to them. These values are automatically added to the temperature values (or subtracted from
them if negative). This allows the systems designer to optimize the system if required, by adding or
subtracting up to 15.875C from a temperature reading.
THERM Limit and Hysteresis
Contains the temperature value at which THERM is asserted and indicates the level of hysteresis.
Look-up Table
Used to program the look-up table for the fan speed-to-temperature profile.
THERM % On-time and
THERM % Limit
Reflects the state of the THERM input and monitors the duration of the assertion time of the signal as
a percentage of a time window. The user can program the length of the time window.
Table 6. RESISTOR RATIOS FOR SETTING LOCATION BITS
Ideal Ratio R2/(R1 + R2)
R1 kW
R2 W
Actual R2/(R1 + R2)
Error %
SMBus Ver
(Note 1)
SMBus Address
UDID LLL
N/A
0
O/C
1
0
ARP
N/A
111
0.8125
18
82
0.82
+0.75
ARP
N/A
110
0.6875
22
47
0.6812
−0.63
ARP
N/A
101
0.5625
12
15
0.5556
−0.69
ARP
N/A
100
0.4375
15
12
0.4444
+0.69
FD
0x53
N/A
0.3125
47
22
0.3188
+0.63
FD
0x52
N/A
0.1875
82
18
0.18
−0.75
FD
0x51
N/A
N/A
O/C
0
0
0
FD
0x50
N/A
1. ARP denotes ARP-capable mode, FD denotes fixed and discoverable mode.
Table 7. UDID VALUES
Bit No.
Name
Function
Value
<127:120>
Device Capabilities
Describes the ADM1033’s capabilities (for instance, that it supports
PEC and uses a random number address device).
11000001
<119:112>
Version/Revision
UDID version number (Version 1) and silicon revision identification
00001010
<111:96>
Vendor ID
Analog Devices vendor ID number, as assigned by the SBS
Implementer’s Forum or the PCI SIG.
00010001
11010100
<95:80>
Device ID
Device ID.
00010000
00110100
<79:64>
Interface
Identifies the protocol layer interfaces supported by the ADM1033.
This represents SMBus 2.0 as the Interface version..
00000000
00000100
<63:48>
Subsystem Vendor ID
Subsystem Vendor ID = 0 (subsystem fields are unsupported).
00000000
00000000
<47:32>
Subsystem Device ID
Subsystem Device ID = 0 (subsystem fields are unsupported).
00000000
00000000
<31:0>
Vendor Specific ID
A unique number per device. Contains LOCATION information (LL)
and a 16-bit random number (x). See Table 9 for information on
setting the LLL bits.
00000000
00000LLL
xxxxxxxx
xxxxxxxx
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ADM1033
SMBus 2.0 Fixed and Discoverable Mode
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the 9th clock pulse.
This is known as no acknowledge. The master
takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
The ADM1033 also supports fixed and discoverable mode,
which is backwards compatible with SMBus 1.0 and 1.1.
Fixed and discoverable mode supports all the same
functionality as ARP-capable mode, except for assign
address in which case it powers up with a fixed address and
is not changed by the assign address call. The fixed address
is determined by the state of the LOCATION pin on powerup.
SMBus 2.0 Read and Write Operations
It is not possible to mix read and write in one operation,
because the type of operation is determined at the beginning
and cannot be changed without starting a new operation.
To write data to one of the device data registers or to read
data from it, the address pointer register (APR) must be set
so that the correct data register is addressed; then data can be
written into that register or read from it. The first byte of a
write operation always contains an address that is stored in
the APR. If data is to be written to the device, then the write
operation contains a second data byte, which is written to the
register selected by the APR.
As illustrated in Figure 17, the device address is sent over
the bus, followed by R/W set to 0. This is followed by two
data bytes. The first data byte is the address of the internal
data register to be written to, which is stored in the APR. The
second data byte is the data to be written to the internal data
register.
When reading data from a register there are two
possibilities.
If the ADM1033’s APR value is unknown or incorrect, it
must be set to the correct value before data can be read from
the desired data register. To do this, perform a write to the
ADM1033 as before, but send only the data byte containing
the register (See Figure 18.) A read operation is then
performed, using the serial bus address and the R/W bit set
to 1, followed by the data byte read from the data register.
(See Figure 19.)
However, if the APR is already at the desired address, data
can be read from the corresponding data register without first
writing to the APR. In this case, see Figure 18 can be omitted.
In Figure 17 to Figure 19, the serial bus address is
determined by the state of the LOCATION pin on powerup.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDA) while the serial clock line (SCL) remains
high. This indicates that an address/data stream is to follow.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next 8 bits, which consist
of a 7-bit address (MSB first) plus an R/W bit. This last bit
determines the direction of the data transfer (whether data is
written to or read from the slave device).
1. The peripheral that corresponds to the transmitted
address responds by pulling the data line low
during the low period before the 9th clock pulse,
which is known as the acknowledge bit. All other
devices on the bus remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads
from it.
2. Data is sent over the serial bus in sequences of 9
clock pulses − 8 bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
high period, because a low-to-high transition when
the clock is high may be interpreted as a stop
signal. The number of data bytes that can be
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
1
9
1
9
SCL
SDA
START BY
MASTER
A6
A5
A4
A3
A2
A1
A0
D7
R/W
D6
ACK. BY
ADM1033
FRAME 1
SERIAL BUS ADDRESS BYTE
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1033
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
ADM1033
STOP BY
MASTER
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
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ADM1033
1
9
9
1
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
D7
R/W
START BY
MASTER
D6
D4
D5
D3
D2
D1
D0
STOP BY
MASTER
ACK. BY
ADM1033
ACK. BY
ADM1033
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
Figure 18. Writing to the Address Pointer Register Only (Send Byte)
9
1
9
1
SCL
SDA
START BY
MASTER
A6
A5
A4
A3
A2
A1
R/W
A0
D7
D6
D5
ACK. BY
ADM1033
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D3
D2
D1
FRAME 2
DATA BYTE FROM ADM1033
D0
NO ACK. BY STOP BY
ADM1033
MASTER
Figure 19. Reading Data from a Previously Selected Register
Register Addresses for Single/Block Byte Modes
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
The ADM1033 supports single byte as well as block read
and write operations. The register address determines
whether a single byte or multiple byte (block) operation is
run. For a single byte operation, the MSB of the register
address is set to 0; for a multiple byte operation, it is set to 1.
The number of bytes read in a multiple byte operation is set
in the #Bytes/Block Read Register at Address 0x00. The
number of bytes written to the ADM1033 is specified during
the block write operation. The addresses quoted in the
register map and throughout this data sheet assume single
byte operation. For multiple byte operations, set the MSB of
each register address to 1.
S
SLAVE
REG
W A
A P
ADDRESS
ADDRESS
Figure 20. Send Byte
The ADM1033 uses the send byte operation to write a
register address to the APR for a subsequent read from the
same address. (See Figure 24). The user may be required to
read data from the register immediately after setting up the
address. If so, the master can assert a repeat start condition
immediately after the final ACK and carry out a single byte
read without asserting an intermediate stop condition.
Write Operations
The SMBus specifications define protocols for read and
write operations. The ADM1033 supports send byte, write
byte, and block byte SMBus write protocols. The following
abbreviations are used in the diagrams:
S − START
P − STOP
R − READ
W − WRITE
A − ACKNOWLEDGE
A − NO ACKNOWLEDGE
Write Byte
In this operation, the master device sends a register
address and one data byte to the slave device as follows:
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by a write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The MSB of
the register address should equal 0 for a write byte
operation. If the MSB equals 1, a block write
operation takes place.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end
the transaction.
Send Byte
In this operation, the master device sends a
single-command byte to a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends a 7-bit address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
S
SLAVE
REG
W A
A
ADDRESS
ADDRESS
DATA
A P
Figure 21. Write Byte Operation
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ADM1033
Block Write
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address (MSB = 1).
5. The slave asserts ACK on SDA.
6. The master asserts a repeated start on SDA.
7. The master sends the 7-bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the byte count.
10. The master asserts ACK on SDA.
11. The slave sends N data bytes.
12. The master asserts ACK on SDA after each data
byte.
13. The master does not acknowledge after the Nth
data byte.
14. The master asserts a stop condition on SDA to end
the transaction.
In this operation, the master device writes a block of data
to a slave address as follows. A maximum of 32 bytes can be
written.
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by a write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The register
address sets up the address pointer register and
determines whether a block write (MSB = 1) or a
byte write (MSB = 0) takes place.
5. The slave asserts ACK on SDA.
6. The master sends the byte count.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each byte.
10. The master asserts a stop condition on SDA to end
the transaction.
S
SLAVE
W A
ADDRESS
REGISTER
ADDRESS
A
BYTE
A DATA 1 A DATA 2 A DATA N A P
COUNT
S
SLAVE
W A
ADDRESS
Figure 22. Block Write to RAM
BYTE
SLAVE
R A
A DATA 1 A DATA N A P
COUNT
ADDRESS
SMBus Timeout
The ADM1033 has a programmable SMBus timeout
feature. When this is enabled, the SMBus typically times out
after 25 ms of no activity. The timeout is disabled by default.
It prevents hangups by releasing the bus after a period of
inactivity.
To enable the SDA timeout, set the SDA timeout bit
(Bit 5) of Configuration Register 1 (Address 0x01) to 1.
To enable the SCL timeout, set the SCL timeout bit (Bit 4)
of Configuration Register 1 (Address 0x01) to 1.
Receive Byte
This is useful when repeatedly reading a single register.
The register address must be set up prior to this, with the
MSB at 0 to read a single byte. In this operation, the master
device receives a single byte from a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master sends NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
Packet Error Checking (PEC)
The ADM1033 also supports packet error checking
(PEC). This optional feature is triggered by the extra clock
for the PEC byte. The PEC byte is calculated using CRC-8.
The frame check sequence (FCS) conforms to CRC-8 by the
following:
In the ADM1033, the receive byte protocol is used to read
a single byte from a register whose address has previously
been set by a send byte or write byte operation.
SLAVE
R A
ADDRESS
A S
Figure 24. Block Read from RAM
Read Operations
S
REGISTER
ADDRESS
C(x) + x 8 ) x 2 ) x ) 1
(eq. 1)
For more information, consult www.SMBus.org.
Alert Response Address (ARA)
DATA
A P
S
Figure 23. Receive Byte
ALERT RESPONSE
DEVICE
R A
A P
ADDRESS
ADDRESS
Figure 25. ALERT Response Address
Block Read
In this operation, the master reads a block of data from a
slave device. The number of bytes to be read must be set in
advance. To do this, use a write byte operation to the
#Bytes/Block Read Register at Address 0x00. The register
address determines whether a block-read or a read-byte
operation is to be completed (set MSB to 1 to specify a
block-read operation). A maximum of 32 bytes can be read.
When multiple devices exist on the same bus, the ARA
feature allows an interrupting device to identify itself to the
host.
The ALERT output can be used as an interrupt output or
as an SMBusALERT. One or more ALERT outputs can be
connected to a common SMBusALERT line, connected to
the master.
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ADM1033
If a device’s ALERT line goes low, the following occurs:
1. SMBusALERT is pulled low.
2. The master initiates a receive byte operation and
sends the alert response address (ARA 0001 100).
This is a general call address that must not be used
as a specific address.
3. The device with the low ALERT output responds
to the ARA, and the master reads its device
address. Once the address is known, it can be
interrogated in the usual way.
4. If low ALERT output is detected in more than one
device, the one with the lowest device address has
priority, in accordance with normal SMBus
arbitration.
5. Once the ADM1033 has responded to the ARA, it
resets its ALERT output. However, if the error
persists, the ALERT is re-asserted on the next
monitoring cycle.
Table 9. LOCAL AND REMOTE SENSOR EXTENDED
RESOLUTION
Extended Resolution (5C)
Temperature Low Bits
0.0000
00000
0.03125
00001
0.0625
00010
0.125
00100
0.250
01000
0.375
01100
0.500
10000
0.625
10100
0.750
11000
0.875
11100
Temperature Measurement System
Temperature (C) = (MSB − 64C) + (LSB x 0.03125)
Example: MSB = 0101 0100 = 84d
LSB = 11100 = 28
Temperature C = (84 – 64) + (28 x 0.03125) = 20.875
Internal Temperature Measurement
Remote Temperature Measurement
The ADM1033 contains an on-chip band gap temperature
sensor. The on-chip ADC performs conversions on the
sensor’s output, outputting the data in 13-bit format. The
resolution of the local temperature sensor is 0.03125C.
Table 8 shows the format of the temperature data MSBs.
Table 9 shows the same for the LSBs. To ensure accurate
readings, read the LSBs first. This locks the current LSBs
and MSBs until the MSBs are read. They then start to update
again. (Reading only the MSBs does not lock the registers.)
Temperature updates to the look-up table take place in
parallel; so fan speeds may be updated even if the MSBs are
locked.
The ADM1033 can measure the temperature of external
diode sensor or diode-connected transistor, which are
connected to Pins 9 and 10. These pins are dedicated
temperature input channels. The series resistance cancellation
(SRC) feature can automatically cancel out the effect of up to
1 kW of resistance in series with the remote thermal diode.
The forward voltage of a diode or diode-connected
transistor, operated at a constant current, exhibits a negative
temperature coefficient of about −2 mV/C. Unfortunately,
the absolute value of VBE varies from device to device, and
individual calibration is required to null this out. Therefore,
the technique is unsuitable for mass production.
Table 8. TEMPERATURE DATA FORMAT
(LOCAL TEMPERATURE AND REMOTE
TEMPERATURE HIGH BYTES)
Temperature (5C)
Digital Output
−64C
0000 0000
−40C
0001 1000
−32C
0010 0000
−2C
0011 1110
−1C
0011 1111
0C
0100 0000
1C
0100 0001
2C
0100 0010
10C
0100 1010
20C
0101 0100
50C
0111 0010
75C
1000 1011
100C
1010 0100
125C
1011 1101
150C
1101 0110
191C
1111 1111
ADM1033
D+
2N3906
D−
2N3904
ADM1033
D+
D−
Figure 26. Measuring Temperature by Using Discreet
Transistors
The ADM1033 operates at three different currents to
measure the change in VBE. Figure 27 shows the input signal
conditioning used to measure the output of an external
temperature sensor. It also shows the external sensor as a
substrate transistor, provided for temperature monitoring on
some microprocessors. The external sensor could work
equally well as a discrete transistor.
If a discrete transistor is used, the collector is not grounded,
and should be linked to the base. If a PNP transistor is used,
the base is connected to the D− input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D− input and the base to the D+ input.
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ADM1033
If the sensor is used in a very noisy environment, a
capacitor value up to 1000 pF may be placed between the D+
and D− inputs to filter the noise. However, additional
parasitic capacitance on the lines between D+, D−, and the
thermal diode should also be considered. The total
capacitance should never be greater than 1000 pF.
To measure each DVBE, the sensor is switched between
operating currents of I, (N1  I), and (N2  I). The resulting
waveform is passed through a 65 kHz low-pass filter to
remove noise, then to a chopper-stabilized amplifier that
amplifies and rectifies the waveform. This produces a dc
voltage proportional to DVBE. These voltage measurements
determine the temperature of the thermal diode, while
automatically compensating for any series resistance on the
D+ and/or D− lines. The temperature is stored in two
registers as a 13-bit word.
To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles
at conversion rates of less than or equal to 8 Hz. An external
temperature measurement takes nominally 32 ms when
averaging is enabled and 6 ms when averaging is disabled.
One LSB of the ADC corresponds to 0.03125C. The
ADM1033 can theoretically measure temperatures from
−64C to +191.96875C, although these are outside its
operating range. The extended temperature resolution data
format is shown in Table 9. The data for the local and remote
channels is stored in the extended temperature resolution
registers (Reg. 0x40 = Local, Reg. 0x42 = Remote 1).
I
N2  I
N1  I
Table 10. TEMPERATURE MEASUREMENT
REGISTERS
Register
Description
0x40
Local Temperature, LSBs
0x00
0x41
Local Temperature, MSBs
0x00
0x42
Remote 1 Temperature, LSBs
0x00
0x43
Remote 1 Temperature, MSBs
0x00
High and low temperature limit registers are associated
with each temperature measurement channel. Exceeding the
programmed high and low limits sets the appropriate status
bit. Exceeding either limit can cause an SMBusALERT
interrupt.
Table 11. TEMPERATURE MEASUREMENT LIMIT
REGISTERS
Register
Description
Default
0x0B
Local High Limit
0x8B (75C)
0x0C
Local Low Limit
0x54 (20C)
0x0D
Local THERM Limit
0x95 (85C)
0x0E
Remote 1 High Limit
0x8B (75C)
0x0F
Remote 1 Low Limit
0x54 (20C)
0x10
Remote 1 THERM Limit
0x95 (85C)
VDD
IBIAS
D+
REMOTE
SENSING
TRANSISTOR
Default
VOUT+
To ADC
D−
VOUT−
LOW-PASS FILTER
fC = 65 kHz
Figure 27. ADM1033 Signal Conditioning
Additional Functions
Single-channel ADC Conversions
Several other temperature measurement functions
available on the ADM1033 offer the systems designer added
flexibility.
In normal operating mode, the ADM1033 converts on two
temperature channels: the local temperature channel, and
the remote channel. However, the user has the option to set
up the ADM1033 to convert on one channel only. To enable
single-channel mode, the user sets the round-robin bit
(Bit 7) in Configuration Register 2 (Address 0x02) to 0.
When the round-robin bit equals 1, the ADM1033 converts
on all temperature channels. In single-channel mode, it
converts on one channel only, to be determined by the state
of the channel selector bits (Bits 5 and 4) of the
Configuration Register 2 (Address 0x02).
Turn-off Averaging
The ADM1033 performs averaging at conversion rates of
less than or equal to 8 conversions per second. This means
that the value in the measurement register is the average of
16 measurements. For faster measurements, set the
conversion rate to 16 conversions per second or greater.
(Averaging is not carried out at these conversion rates.)
Alternatively, switch off averaging at the slower conversion
rates by setting Bit 1 (AVG) of Configuration 1 Register
(Address 0x01).
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ADM1033
 Use wide tracks to minimize inductance and reduce
Table 12. CHANNEL SELECTOR
Bits 5:4
noise pickup. At least 5 mil track width and spacing are
recommended.
Channel Selector (Configuration 2)
00
Local Channel = Default
01
Remote 1 Channel
10
Reserved
11
Reserved
GND
5 MIL
D+
5 MIL
5 MIL
Removing Temperature Errors
D−
As CPUs run faster and faster, it gets more difficult to
avoid high frequency clocks when routing the D+ and D−
traces around a system board. Even when the recommended
layout guidelines are followed, temperature errors attributed
to noise coupled onto the D+ and D− lines remain. High
frequency noise generally gives temperature measurements
that are consistently too high. The ADM1033 has Local and
Remote temperature offset registers at 0x16 and 0x17; one
for each channel. By completing a one-time calibration, the
user can determine the offset caused by the system board
noise and remove it using the offset registers. The registers
automatically add a twos compliment word to the remote
temperature measurements, ensuring correct readings in the
value registers.
Description
Local Offset
0x00
0x17
Remote 1 Offset
0x00
 Try to minimize the number of copper/solder joints,



Table 14. OFFSET REGISTER VALUES
Code
Offset Value
0 0000 000
0C (Default Value)
0 0000 001
0.125C
0 0000 111
0.875C
0 0001 111
1.875C
0 0111 111
7.875C
0 1111 111
15.875C
1 0000 000
−16C
1 1111 000
−0.875C
5 MIL
Figure 28. Arrangement of Signal Tracks
Default
0x16
5 MIL
5 MIL
GND
Table 13. OFFSET REGISTERS
Registration
5 MIL
because they can cause thermocouple effects. Where
copper/solder joints are used, make sure that they are in
both the D+ and D− paths and at the same temperature.
Thermocouple effects are not a major problem because
1C corresponds to approximately 200 mV, and
thermocouple voltages are approximately 3 mV/C of
temperature difference. Unless there are two
thermocouples with a big temperature differential between
them, the voltages should be much less than 200 mV.
Place a 0.1 mF bypass capacitor close to the ADM1033.
If the distance to the remote sensor is more than 8 inches,
twisted pair cable is recommended. This works up to
about 6 feet to 12 feet.
For very long distances (up to 100 feet), use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D− and the shield to
GND, close to the ADM1033. Leave the remote end of
the shield unconnected to avoid ground loops.
Because the measurement technique uses switched
current sources, excessive cable and/or filter capacitance
can affect the measurement. When using long cables, the
filter capacitor C1 may be reduced or removed. In any case,
the total shunt capacitance should never exceed 1000 pF.
Noise Filtering
For temperature sensors operating in noisy environments,
common practice is to place a capacitor across the D+ and
D− pins to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature
measurement, leading to a recommended maximum
capacitor value of 1000 pF. While this capacitor reduces the
noise, it does not eliminate it, making it difficult to use the
sensor in a very noisy environment.
The ADM1033 has a major advantage over other devices
when it comes to eliminating the effects of noise on the
external sensor. The series resistance cancellation feature
allows a filter to be constructed between the external
temperature sensor and the part. The effect of any filter
resistance seen in series with the remote sensor is
automatically cancelled from the temperature.
Layout Considerations
Digital boards can be electrically noisy environments. Try
to protect the analog inputs from noise, particularly when
measuring the very small voltages from a remote diode
sensor. Take the following precautions:
 Place the ADM1033 as close as possible to the remote
sensing diode. A distance of 4 inches to 8 inches is
adequate, provided that the worst noise sources such as
clock generators, data/address buses, and CRTs are
avoided.
 Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.
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ADM1033
Analog Monitoring Cycle Time
The construction of a filter allows the ADM1033 and the
remote temperature sensor to operate in noisy environments.
Figure 29 shows a low-pass R-C-R filter with the following
values: R = 100 W and C = 1 nF. This filtering reduces both
common-mode noise and differential noise.
100 W
REMOTE
TEMPERATURE
SENSOR
The analog monitoring cycle time begins on powerup, or,
if monitoring has been disabled, by writing a 1 to the monitor/
STBY bit of Configuration Register 1, (Address 0x01). The
ADC measures each one of the analog inputs in turn; as each
measurement is completed, the result is automatically stored
in the appropriate value register. The round-robin monitoring
cycle continues unless it is disabled by writing a 0 to the
monitor/STBY bit (Bit 0) of Configuration Register 1
(Address 0x01).
The ADC performs round-robin conversions and takes
11 ms for the local temperature measurement and 32 ms for
each remote temperature measurement with averaging
enabled.
The total monitoring cycle time for the average
temperatures is therefore nominally.
D+
1 nF
100 W
D−
Figure 29. Filter between Remote Sensor
and ADM1033
Limits, Status Registers, and Interrupts
High and low limits are associated with each measurement
channel on the ADM1033. These can form the basis of system
status monitoring. A status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBusALERTs can be generated to flag a processor or
microcontroller of an out-of-limit condition.
32 ) 11 + 43 ms
Once the conversion time elapses, the round robin starts
again. For more information, refer to the Conversion Rate
Register section.
Fan TACH measurements take place in parallel and are not
synchronized with the temperature measurements in any way.
8-bit Limits
The following is a list of all the 8-bit limits on the
ADM1033:
Status Registers
The results of limit comparisons are stored in the status
registers. A 1 represents an out-of-limit measurement; a 0
represents an in-limit measurement. The status registers are
located at Addresses 0x4F to 0x51.
If the measurement is outside its limits, the corresponding
status register bit is set to 1. It remains set at 1 until the
measurement falls back within its limits and it is read or until
an ARA is completed.
Poll the state of the various measurements by reading the
status registers over the serial bus. If Bit 0 (ALERT low) of
Status Register 3 (Address 0x51) is set, this means that the
ALERT output has been pulled low by the ADM1033.
Pin 14 can be configured as a SMBusALERT output. This
automatically notifies the system supervisor of an
out-of-limit condition. Reading the status register clears the
status bit as long as the error condition is gone.
Status register bits are sticky. Whenever a status bit is set
due to an out-of-limit condition, it remains set even after the
triggering event has gone. The only way to clear the status
bit is to read the status register (after the event has gone).
Interrupt mask registers (Reg. 0x08, Reg. 0x09, Reg. 0x0A)
allow individual interrupt sources to be masked from
causing an ALERT. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is
set in the status register.
Table 15. TEMPERATURE LIMIT REGISTERS
Register
Description
Default
0x0B
Local High Limit
0x8B (75C)
0x0C
Local Low Limit
0x54 (20C)
0x0D
Local THERM Limit
0x95 (85C)
0x0E
Remote 1 High Limit
0x8B (75C)
0x0F
Remote 1 Low Limit
0x54 (20C)
0x10
Remote 1 THERM Limit
0x95 (85C)
Table 16. THERM LIMIT REGISTERS
Register
Description
Default
0x19
THERM % Limit
0xFF default
(eq. 2)
Out-of-Limit Comparisons
The ADM1033 measures all parameters in a round-robin
format and sets the appropriate status bit for out-of-limit
conditions. Comparisons are made differently, depending
on whether the measured value is compared to a high or low
limit.
High Limit:  Comparison Performed
Low Limit: < Comparison Performed
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ADM1033
the SMBus ALERT output behaves when writing interrupt
handler software.
The ALERT output on the ADM1033 can be programmed
to operate in either SMBusALERT mode or in comp mode.
In SMBusALERT mode, the ALERT output remains low
until the measurement falls back within its programmed
limits and either the status register is read or an ARA is
completed. In comp mode, the ALERT output automatically
resets once the temperature measurement falls back within
the programmed limits.
Table 17. INTERRUPT STATUS REGISTER 1
(REG. 0X4F)
Bit #
Name
Description
7
LH
1 = Local high temperature limit has
been exceeded.
6
LL
1 = Local low temperature limit has
been exceeded.
5
R1H
1 = Remote 1 high temperature limit has
been exceeded
4
R1L
1 = Remote 1 low temperature limit has
been exceeded.
3
R1D
1 = Remote 1 diode error; indicates an
open or short on the D1+/D1− pins.
2
Unused
Reserved
1
Unused
Reserved
0
Unused
Reserved
Configuring the ALERT Output
For SMBusALERT mode, set the ALERT configuration bit
(Bit 3) of the Configuration Register 1 (Address 0x01) to 0.
In SMBusALERT mode, a status bit is set when a
measurement goes outside of its programmed limit. If the
corresponding mask bit is not set, the ALERT output is
pulled low. If the measured value falls back within the limits,
the ALERT output remains low until the corresponding
status register is read or until an ARA is completed (as long
as no other measurement is outside its limits).
For comp mode, set the ALERT configuration bit (Bit 3)
of Configuration Register 1 (Address 0x01) to1.
In comp mode, the ALERT output is automatically pulled
low when a measurement goes outside its programmed limits.
Once the measurement falls back within its limits (and
assuming no other measurement channel is outside its limits),
the ALERT output is automatically pulled high again.
The main difference between the two modes is that the
SMBusALERT does not reset without software intervention,
whereas the comp mode ALERT output automatically resets.
Table 18. STATUS REGISTER 2 (REG. 0X50)
Bit #
Name
Description
7
LT
1 = Local THERM temperature limit has
been exceeded.
6
R1T
1 = Remote 1 THERM temperature limit
has been exceeded.
5
Unused
4
T%
1 = THERM % on-time limit has been
exceeded.
3
TA
1 = One of the THERM limits has been
exceeded; and the THERM output
signal has been asserted.
2
TS
1 = THERM state. Indicates the THERM
pin is active; clears on a read if THERM
is not active. Does not generate an
ALERT in ALERT comp mode.
Reserved
1
Res
Reserved
0
Res
Reserved
TEMPERATURE
LIMITS
ALERT, 705C
Table 19. STATUS REGISTER 3 (REG. 0X51)
Bit #
Name
7
F1S
6
FA
Description
1 = Fan 1 has stalled.
1 = Fan alarm speed. Fan 1 and Fan 2
are running at alarm speed.
5
Res
Reserved
4
Res
Reserved
3
Res
Reserved
2
Res
Reserved
1
Res
Reserved
0
ALERT
TIME
SMBusALERT
ALERT COMP
CLEARED
ON READ
Figure 30. ALERT Comparator and SMBusALERT
Outputs
1 = ALERT low; indicates the ALERT
line has been pulled low.
Handling SMBusALERT Interrupts
To prevent tie-ups due to service interrupts, follow these
steps:
1. Detect an SMBus assertion.
2. Enter the interrupt handler.
3. Read the status register to identify the interrupt
source.
ALERT Interrupt Behavior
The ADM1033 generates an ALERT whenever an
out-of-limit measurement is made (if it is not masked out).
The user can also detect out-of-limit conditions by polling
the ADM1033 status registers. It is important to note how
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ADM1033
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(from Reg. 0x08 to Reg. 0x0A).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status register. If the interrupt
status bit clears, reset the corresponding interrupt
mask bit to 0. The SMBusALERT output and
status bits then behave as shown in Figure 31.
Table 21. MASK REGISTER 2 (REG. 0X09)
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
”STICKY”
STATUS BIT
Name
7
Res
Reserved
Description
6
Res
Reserved
5
Res
Reserved
4
T%
1 masks the ALERT for the THERM %
on-time limit.
3
TA
1 masks the ALERT for the THERM limit
being exceeded and the THERM output
signal being asserted.
2
TS
1 masks the ALERT for the THERM state;
has no effect on ALERT in ALERT comp
mode.
1
Res
Reserved
0
Res
Reserved
Table 22. MASK REGISTER 3 (REG. 0X0A)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBusALERT
Bit #
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBusALERT REARMED)
Figure 31. Handling SMBusALERT
Bit #
Name
7
F1S
Description
1 mask the ALERT for Fan 1 stalling
6
FA
1 mask the ALERT for fans at ALARM speed
5
Res
Reserved
4
Res
Reserved
3
Res
Reserved
Interrupt Masking Register
2
Res
Reserved
Mask Registers 1, 2, and 3 are located at Addresses 0x08,
0x09, and 0x0A. These allow individual interrupt sources to
be masked out to prevent the SMBusALERT interrupts.
Masking the interrupt source prevents only the
SMBusALERT from being asserted; the appropriate status bit
is still set as normal.
1
Res
Reserved
0
Res
Reserved
FAN_FAULT Output
The FAN_FAULT output signals when one or both of the
fans stall. Pin 8, the FAN_FAULT output, is a dual-function
pin. It defaults to being a FAN_FAULT output but can be
reconfigured as an analog input reference for the THERM
input. To do this, set the FAN_FAULT/REF (Bit 7) in
Configuration Register 4 (Address 0x04) to 1.
Table 20. MASK REGISTER 1 (REG. 0X08)
Bit #
Name
7
LH
1 masks the ALERT for the local high
temperature.
Description
6
LL
1 masks the ALERT for the local low
temperature.
5
R1H
1 masks the ALERT for the Remote 1
high temperature.
4
R1L
1 masks the ALERT for the Remote 1
low temperature.
3
R1D
1 masks the ALERT for the Remote 1
diode errors.
2
Res
Reserved
1
Res
Reserved
0
Res
Reserved
Fault Queue
The ADM1033 has a programmable fault queue option
that lets the user program the number of out-of-limit
measurements allowable before generating an ALERT. The
fault queue affects only temperature measurement channels
and is only operational in SMBusALERT mode. It performs
some simple filtering, which is particularly useful at the
higher conversion rates (16, 32, and 64 conversions per
second), where averaging is not carried out.
There is a queue for each of the temperature channels. If
L (the number programmed to the fault queue) or more
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ADM1033
THERM I/O Timer and Limits
consecutive out-of-limit readings are made on the same
temperature channel, the fault queue fills, and the
SMBusALERT output triggers. To fill the fault queue, one
needs L or more consecutive out of limits on the internal
temperature channel; L or more consecutive out-of-limits on
the external 1 temperature channel; or L or more consecutive
out-of-limits on the external 2 temperature channel. The
fault queue is independent of the state of the bits in the
ALERT status registers.
Pin 7 can be configured as either an input or output. As an
output it is asserted low to signal that the measured
temperature has exceeded preprogrammed temperature
limits. The output is automatically pulled high again when
the temperature falls below the THERM − Hys limit. The
value of hysteresis is programmable in Register 0x1A.
THERM is enabled as an output by default on powerup.
TEMPERATURE
LIMITS
Table 23. FAULT QUEUE ADDRESS 0X06
Bits <3:0>
Fault Queue
000X
1
001X
2
01XX
3
1XXX
4
THERM, 85C
THERM−HYST,
80C
To reset the fault queue, do one of the following:
 SMBus ARA Command
 Read Status Register 1
 Power-On Reset
TIME
THERM
Figure 32. THERM Behavior
The SMBusALERT clears, even if the condition that
caused the SMBusALERT remains. The SMBusALERT is
reasserted if the fault queue fills up.
Once the THERM limits are exceeded, the fans are
boosted to full speed, that is, as long as the Boost Disable Bit
(Bit 1) is not set in Configuration Register 2 (Address 0x02).
To configure THERM as an input, the user must set the
THERM timer bit (Bit 2) of Configuration Register 1
(Address 0x01) to 1. (It no longer operates as an output.) The
ADM1033 can then detect when the THERM input is
asserted low. This may be connected to a trip point
temperature sensor or to the FAN_FAULT PROCHOT
output of a CPU. With processor core voltages reducing all
the time, the threshold for the AGTL + PROCHOT output
also reduces down as new processors become available. The
default threshold on the input is the normal CMOS
threshold. However, Pin 8 (FAN_FAULT/REF) can also be
reconfigured as a REF input. This is done by setting Bit 7
(FAN_FAULT/REF) in Configuration Register 4 (Address
0x04). Connect the processor VCCP to this input to provide
a reference for the THERM input. The resulting THERM
threshold is 0.75  VCCP, which is the correct threshold for
an AGTL + signal.
The ADM1033 also measures assertion times on the
THERM input as a percentage of a time window. This time
window is programmable in Configuration Register 4
(Address 0x04) by using Bits <6:4> (THERM % Time
Window). Values between 0.25 seconds and 8 seconds are
programmable. The assertion time as a percentage of the
time window is stored in the THERM % On-Time Register
(Address 0x4E).
A THERM % limit is also associated with this register. Once
the measured percentage exceeds the percentage limit, the
Conversion Rate Register
The ADM1033 makes up to 64 measurements per second.
However, for the sake of reduced power consumption and
better noise immunity, users may run the ADM1033 at a
slower conversion rate. Better noise immunity results from
the averaging that occurs at the slower conversion rates.
Averaging does not occur at rates of 16, 32, or 64
conversions per second. Table 24 lists the available
conversion rates. Note that the current round-robin loop
must be finished for conversion rates changes to take effect.
Table 24. CONVERSION RATES
Code
Conversion Rate
0x00
0.0625
0x01
0.125
0x02
0.25
0x03
0.5
0x04
1
0x05
2
0x06
4
0x07
8
0x08
16
0x09
32
0x0A
64
0x0B to 0xFF
Reserved
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ADM1033
THERM % Exceeded Bit (Bit 4) in Status Register 2 (Address
0x50) is asserted and an ALERT is generated, that is, if the
mask bit is not set. If the limit is set to 0x00, an ALERT is
generated on the first assertion. If the limit is set to 0xFF, an
ALERT is never generated. This is because 0xFF corresponds
to the THERM input, which is asserted continuously.
applied to the fan varies the speed of the fan. The ADM1033
uses a control method called synchronous speed control, in
which the PWM drive signal applied to the fan is
synchronized with the fan’s TACH signal. See the
Synchronous Speed Control section for more information.
The external circuitry required to drive the fan is very
simple. A single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend
on the maximum current required by the fan and the gate
voltage drive (VGS < 3.0 V for direct interfacing to the drive
pin). VGS can be greater than 3.0 V, as long as the pullup on
the gate is tied to 5.0 V. The MOSFET should also have a low
on-resistance to ensure that there is no significant voltage
drop across the FET. A high on-resistance reduces the
voltage applied across the fan and therefore the maximum
operating speed of the fan. Figure 33 shows a scheme for
driving a 3-wire fan.
Code
THERM %
On-Time Window
000
0.25 s
001
0.5 s
010
1s
011
2s
100
4s
101
8s
110
8s
111
8s
12 V
10 kW
10 kW
When THERM is configured as an input only, setting the
Enable THERM Events bits in Configuration Register 4
allows Pin 7 to operate as an I/O.
The user can configure the THERM pin to be pulled low
as an output whenever the local temperature exceeds the
local THERM limit. To do this, set the Enable Local
THERM events bit (Bit 0) of Configuration Register 4
(Address 0x04).
The user can also configure the THERM pin to be pulled
low as an output whenever the Remote 1 temperature
exceeds the Remote 1 THERM limit. Set the Enable
Remote 1 THERM events bit (Bit 1) of Configuration
Register 4 (Address 0x04).
TACH
4.7 kW
ADM1033
TACH
12 V
12 V
FAN
1N4148
Table 25. CONVERSION RATES
3.3 V
100 kW
DRIVE
Q1
NDT3055L
Figure 33. Interfacing a 3-wire Fan to the ADM1033
by Using an N-channel MOSFET
Figure 33 uses a 10 kW pullup resistor for the TACH
signal. This assumes that the TACH signal is an open
collector from the fan. In all cases, the fan’s TACH signal
must be kept below 5.0 V maximum to prevent damaging
the ADM1033.
If in doubt as to whether a fan has an open-collector or
totem pole TACH output, use one of the input signal
conditioning circuits shown in the Fan Inputs section.
When designing drive circuits with transistors and FETs,
make sure that the drive pins are not required to source
current and that they sink less than the maximum current
specified here.
THERM % Limit Register
The THERM % limit is programmed to Register 0x19. An
ALERT is generated, if THERM is asserted for longer than
the programmed percentage limit. The limit is programmed
as a percentage of the chosen time window.
THERM % limit register is an 8-bit register.
0x00 = 0%
0xFF = 100%
Therefore, 1 LSB = 0.39%.
Example:
If a time window of 8 seconds is chosen, and an ALERT
is to be generated if THERM is asserted for more than
1 second, program the following value to the limit register:
% Limit = 1/8  100 = 12.5%
12.5%/0.39% = 32d = 0x20 = 0010 0000
Synchronous Speed Control
The ADM1033 drives the fan by using a control scheme
called synchronous speed control. In this scheme, the PWM
drive signal applied to the fan is synchronized with the
TACH signal. Accurate and repeatable fan speed
measurements are the main benefits. The fan is allowed to
run reliably at speeds as low as 30 percent of the full
capability.
The drive signal applied to the fan is synchronized with
the TACH signal. The ADM1033 switches on the drive
An ALERT is generated if the THERM limit is exceeded
after the time window has elapsed, assuming it is not
masked.
Fan Drive Signal
The ADM1033 contols the speed of up to one cooling fan.
Varying the duty cycle (on/off time) of a square wave
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ADM1033
Figure 34 shows how the synchronous speed drive signal
works. The ideal TACH signal is the TACH signal that
would be output from the fan if power were applied
100 percent of the time. It is representative of the actual
speed of the fan. The actual TACH signal is the signal the
user would see on the TACH output from the fan if the user
were to put a scope on it. In effect, the actual TACH signal
is the ideal TACH signal chopped with the drive signal.
signal and waits for a transition on the TACH signal. When
a transition takes place on the TACH signal, the PWM drive
is switched off for a period of time called toff . The drive
signal is then switched on again. The toff time is varied in
order to vary the fan speed. If the fan is running too fast, the
toff time is increased. If the fan is running too slow, the toff
time is decreased.
Since the drive signal is synchronized with the TACH
signal, the frequency with which the fan is driven depends
on the current speed of the fan and the number of poles in it.
POLE TRANSITION POINTS
IDEAL TACH
tPOLE
DRIVE
tOFF
ACTUAL TACH
DASH = TACH FLOATS HIGH BY PULL-UP RESISTOR
SOLID = TRUE TACH WHEN FAN IS POWERED
Figure 34. Drive Signal by Using Synchronous Control
Fan Inputs
If the fan output has a resistive pullup to 12 V (or another
voltage greater than 5.0 V), the fan output can be clamped
with a Zener diode, as shown in Figure 36. The Zener
voltage should be chosen so that it is greater than VIH but less
than 5.0 V. Allowing for the voltage tolerance of the Zener,
a value of between 3.0 V and 5.0 V is suitable.
Pin 2 is a TACH input intended for fan speed measurement.
This input is open-drain.
Signal conditioning on the ADM1033 accommodates the
slow rise and fall time of typical tachometer outputs. The
maximum input signal range is from 0 V to 5.0 V, even when
VCC is less than 5.0 V. In the event that these inputs are
supplied from fan outputs exceeding 0 V to 5.0 V, either
resistive attenuation of the fan signal or diode clamping
must be used to keep the fan inputs within an acceptable
range.
Figure 35 to Figure 38 show examples of possible fan
input circuits. If the fan TACH has a resistive pullup to VCC,
it can be connected directly to the fan output.
5 V or 12 V
FAN
PULL-UP
4.7 kW
TYP
5 V or 12 V
FAN
PULL−UP
4.7 kW
TYP
VCC
100 kW
TYP
100 kW
TYP
ADM1033
TACH X
ZD1*
FAN SPEED
COUNTER
DRIVE X
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8  VCC
ADM1033
TACH X
TACH
OUTPUT
VCC
VCC
TACH
OUTPUT
VCC
FAN SPEED
COUNTER
Figure 36. Fan with TACH Pullup to Voltage > 5.0 V,
Clamped with Zener Diode
DRIVE X
If the fan has a strong pullup (less than 1 kW to +12 V) or
a totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 37. Alternatively, a
resistive attenuator may be used, as shown in Figure 38.
Figure 35. Fan with TACH Pullup to +VCC
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ADM1033
Figure 39 shows the fan speed measurement period,
assuming that the fan outputs an ideal TACH signal. In
reality, the TACH signal output by the fan is chopped by the
drive signal. However, since the drive and the TACH signal
are synchronized, there is enough information available for
the ADM1033 to measure the fan speed accurately.
R1 and R2 should be chosen such that
2 V t V PULLUP
R2ń(R PULLUP ) R1 ) R2) t 5 V
(eq. 3)
The fan inputs have an input resistance of nominally
160 kW to ground. This should be taken into account when
calculating resistor values.
With a pullup voltage of 12 V and pullup resistor less than
1 kW, suitable values for R1 and R2 would be 100 kW and
47 kW. This gives a high input voltage of 3.83 V.
12 V
CLOCK
VCC
IDEAL
TACH
FAN
MEASUREMENT
PERIOD
ADM1033
FAN (0−7)
PULL-UP
ZD1*
TYP < 1 kW
Figure 39. Fan Speed Measurement for a 4-pole Fan
FAN SPEED
COUNTER
Fan Speed Measurement Registers
These 16-bit measurements are stored in the TACH value
registers.
OR TOTEM-POLE
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8  VCC
Table 26. TACH VALUE REGISTERS
Figure 37. Fan with Strong TACH. Pullup to >VCC or
Totem-Pole Output, Clamped with Zener and Resistor
12 V
VCC
< 1 kW
TACH
OUTPUT
R1*
ADM1033
FAN (0−7)
Register
Description
Default
0x4A
TACH1 Period, LSB
0xFF
0x4B
TACH1 Period, MSB
0xFF
0x4C
TACH2 Period, LSB
0xFF
0x4D
TACH2 Period, MSB
0xFF
Reading Fan Speed
Reading back fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
freezes the high byte until both high and low byte registers
have been read, preventing erroneous fan speed
measurement readings.
The fan tachometer reading registers report back the
number of 12.2 ms period clocks (81.92 kHz oscillator)
gated to the fan speed counter, for one full rotation of the fan,
assuming the correct number of poles is programmed. Since
the ADM1033 essentially measures the fan TACH period,
the higher the count value, the slower the actual fan speed.
A 16-bit fan TACH reading of 0xFFFF indicates that the fan
has stalled or is running very slowly (< 75 rpm).
FAN SPEED
COUNTER
R2
*SEE TEXT
Figure 38. Fan with Strong TACH. Pullup to >VCC or
Totem-Pole Output, Attenuated with R1/R2
Fan Speed Measurement
The fan counter does not count the fan TACH output
pulses directly. This is because the fan may be spinning at
less than 1000 rpm and it would take several seconds to
accumulate a reasonably large and accurate count. Instead,
the period of the fan revolution is measured by gating an
on-chip 81.92 kHz oscillator into the input of a 16-bit
counter for one complete revolution of the fan. Therefore,
the accumulated count is actually proportional to the fan
tachometer period and inversely proportional to the fan
speed.
The number of poles in the fan must be programmed in
Configuration Register 3 (Address 0x03). Bits <3:0> set the
number of poles for Fan 1, and Bits <7:4> set the number of
poles for Fan 2. This number must be an even number only,
because there cannot be an uneven number of poles in a fan.
A TACH period is output for every two poles. Therefore, the
number of poles must be known so that the ADM1033 can
measure for a full revolution.
Calculating Fan Speed
Fan speed in rpm is calculated as follows. This assumes
that the number of poles programmed in the Configuration
Register 3 (Address 0x03) is correct for both fans.
Fan Speed (RPM) = (81920  60)/Fan TACH Reading
where:
Fan TACH Reading = 16-bit Fan TACHometer Reading
Example:
TACH1 High Byte (Reg. 0x4A) = 0x17
TACH1 Low Byte (Reg. 0x4B) = 0xFF
What is Fan 1 speed in rpm?
Fan 1 TACH Reading = 0x17FF = 6143d
RPM = (f  60) / Fan 1 TACH reading
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ADM1033
Manual Mode
RPM = (81920  60) / 6143
Fan Speed = 800 RPM
In manual mode, the ADM1033 is under software control.
The software can program the required fan speed value or
the target fan speed to the ADM1033, which then outputs
that fan speed.
Alarm Speed
The fan ALARM speed (Bit 6) in Status Register 3
(Address 0x51) is set whenever the fan runs at alarm speed.
This occurs if the device is programmed to run the fan at full
speed whenever the THERM temperature limits are
exceeded. The device runs at alarm speed, for example, if the
Boost Disable bit (Bit 1) of the Configuration 2 Register
(Address 0x02) is not set to 1.
Programming Target Fan Speed
In this mode, the user programs the target fan speed as a
TACH count for N poles or a TACH count for one full
rotation of the fan, assuming the number of poles is
programmed correctly in the Configuration 3 Register
(Address 0x03).
Use the following steps to program the target fan speed:
1. Place the ADM1033 into manual mode. Set Bit 7
(Table/SW) of Configuration Register 1
(Address 0x01) = 0.
2. Program the target TACH count (fan speed) using
the following equation:
Fan Response Register
The ADM1033 fan speed controller operates by reading
the current fan speed, comparing it with the programmed fan
speed, and then updating the drive signal applied to the fan.
The rate at which the ADM1033 looks at and updates the
drive signal is determined by the fan response register.
Different fans have different inertias and respond to a
changing drive signal more or less quickly than others. The
fan response register allows the user to tailor the ADM1033
to a particular fan to prevent situations like overshoot.
The user programs the number of updates the ADM1033
can make to the drive signal per second. Table 27 lists the
available options.
TACH Count + (f
Update Rate
000
1.25 Updates/Second
001
2.5 Updates/Second = Default
010
5 Updates/Second
011
10 Updates/Second
100
20 Updates/Second
101
40 Updates/Second
110
80 Updates/Second
Fan
111
160 Updates/Second
Table 29. REGISTERS TO BE PROGRAMMED
Table 28. CONVERSION RATES
Bit #
Function
7
Reserved
<6:4>
Reserved
3
Reserved
<2:0>
Fan 1 Response
(eq. 4)
where:
f = clock frequency = 81.92 kHz
R = required RPM value
Example 1: If the desired speed for Fan 1 is 5000 rpm,
program the following value to the TACH count registers:
TACH Count = (f  60)/5000
TACH Count = 983d = 0x03D7
Example 2: If the desired speed for Fan 2 is 3500 rpm,
program the following value to the TACH pulse period
registers:
TACH Count = (f  60)/3500
TACH Count = 1404d = 0x057C
Table 27. FAN RESPONSE CODES
Code
60)ńR
Description
Address
Value
Fan 1
Look-up Table FS1, LSB
0x2A
0xD7
Fan 1
Look-up Table FS1, MSB
0x2B
0x03
Look-up Table
The ADM1033 allows the user to program a
temperature-to-fan speed profile. There are 24 registers in
the look-up table; 8 for temperature and 16 for target fan
speed (each target fan speed is two registers). In total, there
are eight available points.
There are two options when programming the look-up
table. The ADM1033 can be programmed to make the fan
speed run at discrete speeds and jump to the new fan speed
once the temperature threshold is crossed. Or, it can linearly
ramp the TACH count between the two temperature
thresholds.
Look-up Table: Modes of Operation
The ADM1033 look-up table has two different modes of
operation used to determine the behavior of the system:
 Manual Mode
 Look-up Table
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ADM1033
Figure 40 and Figure 41 show what the look-up table
looks like if all eight points are used on the one curve.
Figure 40 shows the transfer curve when the fan is
programmed to run at discrete speeds. The ADM1033 spins
the fan at its new speed once a threshold is crossed.
Once the temperature exceeds the highest temperature
point in the look-up table, the fan speed remains at the
highest speed until the temperature drops below the T7
temperature value. When the look-up table is split in two, the
same applies.
If the temperatures in T1 to T8 are not programmed in
succession, the fan speed moves to the next highest
programmed temperature as the temperature increases.
Similarly, when the temperature decreases, it ignores
programmed higher temperatures and jumps to the next lower
temperature. Therefore, the temperature-to-fan speed profile
for increasing and decreasing temperature can be different.
When programming the look-up table, the user has the
option to use between two and eight points for the fan. If the
user just wants to program a transfer curve (and knows the
starting temperature, minimum speed, maximum
temperature, and maximum speed), then all the user needs
to program are four parameters: T1, T2, FS1, and FS2. The
remainder of the look-up temperature thresholds should
remain at their default values of +191C. If required, the FS3
should be programmed with the same value as FS2 to give
the flat curve, if required. Or, the fan speeds can be left at the
default value of 0. However, it is normal to program a
THERM limit as well. Once this temperature is exceeded
and the boost bit is set, the fan run to full speed. This
overrides the look-up table.
FAN SPEED
TACH COUNT 8
TACH COUNT 7
TACH COUNT 6
TACH COUNT 5
TACH COUNT 4
TACH COUNT 3
TACH COUNT 2
TACH COUNT 1
T1
T2
T3
T4
T5
T6
T7
T8
TEMPERATURE
Figure 40. Programming the Look-up Table in
Discreet Fan Speeds Mode
Figure 41 shows the transfer curve if the Linear Fan
Speeds option is chosen. At temperature T1, the fan runs at
Fan Speed 1. As the temperature increases, the fan speed
increases until it reaches Fan Speed 2 at T2.
FAN SPEED
TACH COUNT 8
Table 30. LOOK-UP TABLE REGISTER ADDRESS
TACH COUNT 7
TACH COUNT 6
TACH COUNT 5
TACH COUNT 4
x
Temperature, x
1
0x22
0x2A
0x2B
TACH COUNT 3
2
0x23
0x2C
0x2D
TACH COUNT 2
3
0x24
0x2E
0x2F
TACH COUNT 1
4
0x25
0x30
0x31
5
0x26
0x32
0x33
6
0x27
0x34
0x35
7
0x28
0x36
0x37
8
0x29
0x38
0x39
T1
T2
T3
T4
T5
T6
T7
T8
TEMPERATURE
Figure 41. Programming the Look-up Table in Linear
Fan Speeds Mode
FSx, LSB
FSx, MSB
Setting Up the Look-up Table in Linear Mode
FAN SPEED
When Discrete/Linear Speed (Bit 2) is set to 1 (default),
the TACH count decreases linearly (and therefore the fan
speed increases) with temperature.
Example: At temperature TX, the fans run at FSX and fan
speed increases with temperature to FSX+1 at temperature
TX+1.
Alternatively, the fan can be run at discrete fan speeds.
When Discrete/Linear Speed (Bit 2) is set to 0, the fan runs
at a new speed once the temperature threshold is exceeded.
TACH COUNT 2 TO 8
TACH COUNT 1
T1
T2
T (3 TO 8) = C
Setting Which Temperature Channel Controls a Fan
TEMPERATURE
Fan Behavior Register (Address 0x07)
Bits <1:0> = DRIVE1 Behavior (D1B)
Figure 42. Programming Two Points on the
Look-up Table
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ADM1033
The ADM1033 can be configured so that Fan 1 can be
controlled by either the local temperature, or by the Remote 1
temperatures.
Table 33. THERM HYSTERESIS REGISTERS
Address
Table 31. DRIVE BHVR BITS
Bits
DRIVE x BHVR
00
Local Temperature Controls Fan
01
Remote 1 Temperature Controls Fan
10
Reserved
11
Fan Runs at Full Speed
Description
Default
0x0D
Local THERM Limit
0x95 (85C)
0x10
Remote 1 THERM Limit
0x95 (85C)
The THERM hysteresis register is at Address 0x1A. A
hysteresis value is programmed and applied to all two
temperature channels; Local and Remote 1. A THERM
hysteresis value of between 0C and 15C can be programmed
with a resolution of 1C. Table 33 gives some examples.
Table 34. PROGRAMMING THERM HYSTERESIS
Look-up Table Hysteresis
The user can program a hysteresis to be applied to the
look-up table. The advantage of this is apparent if the
temperature is cycling around one of the threshold
temperatures and causing the fan speed to switch between
the two speeds, particularly when the look-up table is
configured in discrete mode. It would not be as important in
the linear mode.
Table 32. PROGRAMMING THE HYSTERESIS
Code
Hysteresis Value
0000 0000
0C
0000 0001
1C
0000 0010
2C
0000 0101
5C
0000 1000
8C
0000 1111
15C
Code
Hysteresis Value
0000 0000
0C
0000 0001
1C
0000 0010
2C
0000 0101
5C = Default
0000 1000
8C
0000 1111
15C
XOR Tree Test Mode
The ADM1033 includes an XOR tree test mode. This is
useful for in circuit test equipment at board level testing. By
applying stimulus to the pins included in the XOR test, it is
possible to detect opens or shorts on the system board.
Figure 43 shows the signals that are exercised in the XOR
tree test mode. The XOR tree test is enabled by setting the
XOR bit (Bit 3) in Configuration 4 Register (0x04).
TACH1
DRIVE2
The look-up table’s hysteresis register is at Address 0x3A.
A hysteresis value of between 0C and 15C can be
programmed with a resolution of 1C and applied to all the
temperature thresholds. Table 32 gives examples of values
for programming.
THERM
Programming the THERM Limit for Temperature
Channels
FAN_FAULT/REF
THERM is the absolute maximum temperature allowed
on a temperature channel. Above this temperature, a
component such as the CPU or VRM may be operating
beyond its safe operating limit. When the temperature
measured exceeds THERM, all fans are driven at full speed
to provide critical system cooling. The fans remain running
at full speed until the temperature drops below THERM –
Hysteresis. The hysteresis value is programmable; its
default is 5C. If the Boost Disable bit (Bit 1) is set in
Configuration Register 2, the fan do not run to full speed.
The THERM limit is considered the maximum worst-case
operating temperature of the system. Exceeding any
THERM limit runs the fan at full speed, a condition with
very negative acoustic effects. This limit should be set up as
a fail-safe and not exceeded under normal system operating
conditions. The THERM temperature limit registers are
listed in Table 33.
LOCATION
ALERT
DRIVE1
Figure 43. XOR Tree Test
Lock Bit
Setting the Lock bit (Bit 6) of Configuration Register 1
(Address 0x01) makes all the lockable registers read-only.
These registers remain read-only until the ADM1033 is
powered down and back up again. For more information on
which registers are lockable, see Table 35.
SW Reset
Setting the Software Reset bit (Bit 0) of Configuration
Register 2 (Address 0x02) resets all software resettable bits
to their default value. For more information on resetting
registers and their default values, see Table 35 to Table 69.
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ADM1033
Table 35. ADM1033 REGISTERS
Address
R/W
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lock−
able?
0x00/80
R/W
#Bytes/Block Read
7
6
5
4
3
2
1
0
0x20
Y
0x01/81
R/W
Configuration 1
Table/SW
Lock
SDA
SCL
ALERT
TIMER
Avg
Mon
0x01
Y
0x02/82
R/W
Configuration 2
RR
RES
CS
CS
RES
D/L
BD
Reset
0x84
Y
0x03/83
R/W
Configuration 3
#FP2
#FP2
#FP2
#FP2
#FP1
#FP1
#FP1
#FP1
0x04
Y
0x04/84
R/W
Configuration 4
FF/REF
%T
%T
%T
XOR
RES
R1TM
LTM
0x00
Y
0x05/85
R/W
Conversion Rate
RES
RES
RES
RES
Conv
Conv
Conv
Conv
0x07
Y
0x06/86
R/W
Fault Queue
RES
RES
RES
RES
FQ
FQ
FQ
FQ
0x01
Y
0x07/87
R/W
Fan Behavior
RES
F1 Off
RES
RES
RES
RES
D1B
D1B
0x01
Y
0x08/88
R/W
Mask 1
LH
LL
R1H
R1L
R1D
R2H
R2L
R2D
0x50
N
0x09/89
R/W
Mask 2
RES
RES
RES
%T
TA
TS
RES
RES
0x18
N
0x0A/8A
R/W
Mask 3
F1S
FA
F2S
RES
RES
RES
RES
RES
0x00
N
0x0B/8B
R/W
Local High Limit
7
6
5
4
3
2
1
0
0x8B
N
0x0C/8C
R/W
Local Low Limit
7
6
5
4
3
2
1
0
0x54
N
0x0D/8D
R/W
Local THERM Limit
7
6
5
4
3
2
1
0
0x95
Y
0x0E/8E
R/W
Remote 1 High
Limit
7
6
5
4
3
2
1
0
0x8B
N
0x0F/8F
R/W
Remote 1 Low
Limit
7
6
5
4
3
2
1
0
0x54
N
0x10/90
R/W
Remote 1 THERM
Limit
7
6
5
4
3
2
1
0
0x95
Y
0x16/96
R/W
Local Offset
7
6
5
4
3
2
1
0
0x00
Y
0x17/97
R/W
Remote 1 Offset
7
6
5
4
3
2
1
0
0x00
Y
0x19/99
R/W
THERM % Limit
0x1A/9A
R/W
THERM Hysteresis
7
6
5
4
3
2
1
0
0xFF
Y
RES
RES
RES
RES
Hys
Hys
Hys
Hys
0x05
0x22/A2
R/W
Y
Look-up table T1
7
6
5
4
3
2
1
0
0xFF
Y
0x23/A3
0x24/A4
R/W
Look-up table T2
7
6
5
4
3
2
1
0
0xFF
Y
R/W
Look-up table T3
7
6
5
4
3
2
1
0
0xFF
Y
0x25/A5
R/W
Look-up table T4
7
6
5
4
3
2
1
0
0xFF
Y
0x26/A6
R/W
Look-up table T5
7
6
5
4
3
2
1
0
0xFF
Y
0x27/A7
R/W
Look-up table T6
7
6
5
4
3
2
1
0
0xFF
Y
0x28/A8
R/W
Look-up table T7
7
6
5
4
3
2
1
0
0xFF
Y
0x29/A9
R/W
Look-up table T8
7
6
5
4
3
2
1
0
0xFF
Y
0x2A/AA
R/W
Look-up table, FS1
7
6
5
4
3
2
1
0
0xFF
Y
0x2B/AB
R/W
Look-up table, FS1
15
14
13
12
11
10
9
8
0xFF
Y
0x2C/AC
R/W
Look-up table, FS2
7
6
5
4
3
2
1
0
0xFF
Y
0x2D/AD
R/W
Look-up table, FS2
15
14
13
12
11
10
9
8
0xFF
Y
0x2E/AE
R/W
Look-up table, FS3
7
6
5
4
3
2
1
0
0xFF
Y
0x2F/AF
R/W
Look-up table, FS3
15
14
13
12
11
10
9
8
0xFF
Y
0x30/B0
R/W
Look-up table, FS4
7
6
5
4
3
2
1
0
0xFF
Y
0x31/B1
R/W
Look-up table, FS4
15
14
13
12
11
10
9
8
0xFF
Y
0x32/B2
R/W
Look-up table, FS5
7
6
5
4
3
2
1
0
0xFF
Y
0x33/B3
R/W
Look-up table, FS5
15
14
13
12
11
10
9
8
0xFF
Y
0x34/B4
R/W
Look-up table, FS6
7
6
5
4
3
2
1
0
0xFF
Y
0x35/B5
R/W
Look-up table, FS6
15
14
13
12
11
10
9
8
0xFF
Y
0x36/B6
R/W
Look-up table, FS7
7
6
5
4
3
2
1
0
0xFF
Y
0x37/B7
R/W
Look-up table, FS7
15
14
13
12
11
10
9
8
0xFF
Y
0x38/B8
R/W
Look-up table, FS8
7
6
5
4
3
2
1
0
0xFF
Y
0x39/B9
R/W
Look-up table, FS8
15
14
13
12
11
10
9
8
0xFF
Y
0x3A/BA
R/W
Look-up table Hysteresis
RES
RES
RES
RES
Hys
Hys
Hys
Hys
0x05
Y
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ADM1033
Table 35. ADM1033 REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lock−
able?
RES
RES
RES
RES
RES
F1
F1
F1
0x01
Y
Device ID
7
6
5
4
3
2
1
0
0x34
N
Company ID
7
6
5
4
3
2
1
0
0x41
N
R
Revision Register
7
6
5
4
3
2
1
0
0x02
N
0x40/C0
R
Local Temperature
4
3
2
1
0
RES
RES
RES
0x00
N
0x41/C1
R
Local Temperature
12
11
10
9
8
7
6
5
0x00
N
0x42/C2
R
Remote 1 Temp
4
3
2
1
0
RES
RES
RES
0x00
N
0x43/C3
R
Remote 1 Temp
12
11
10
9
8
7
6
5
0x00
N
0x4A/CA
R
TACH1 Period
7
6
5
4
3
2
1
0
0xFF
N
0x4B/CB
R
TACH1 Period
15
14
13
12
11
10
9
8
0xFF
N
0x4E/CE
R
THERM % Ontime
7
6
5
4
3
2
1
0
0x00
N
0x4F/CF
R
Status 1
LH
LL
R1H
R1L
R1D
RES
RES
RES
0x00
N
0x50/D0
R
Status 2
LT
R1T
RES
%T
TA
TS
RES
RES
0x00
N
0x51/D1
R
Status 3
F1S
FA
RES
RES
RES
RES
RES
ALERT
0x00
N
Address
R/W
0x3C/BC
R/W
0x3D/BD
R
0x3E/BE
R
0x3F/BF
Description
Fan Response
Table 36. REGISTER 0X00, # BYTES/BLOCK READ, POR = 0X20, LOCK = Y, S/W RESET = Y
Bit
<7:0>
Name
# Bytes Block Read
R/W
Description
R/W
Block reads are # bytes/block read long. The maximum is 32 bytes, the SMBus transaction
limit.
Table 37. REGISTER 0X01, CONFIGURATION REGISTER 1, POWER-ON DEFAULT 0X01, LOCK = Y, S/W RESET = Y
Bit
Name
R/W
Description
7
Table/SW Con
R/W
Set this bit to 1 to place the fan speed under the control of the Look-up table. When this
bit is 0, the ADM1033 is in software/manual control mode. Default = 0.
6
Lock Bit
R/W
Set this bit to 1 to prevent the user from writing to the ADM1033 registers. 1 = ADM1033
registers locked. 0 = ADM1033 registers unlocked. Default = 0.
5
SDA Timeout
R/W
1 = SDA timeout enabled. 0 = SDA timeout disabled. Default = 0.
4
SCL Timeout
R/W
1 = SCL timeout enabled. 0 = SDL timeout disabled. Default = 0.
3
ALERT Configuration
R/W
0 = SMBusALERT. Default = 0. 1 = ALERT_COMP mode.
2
Enable THERM Timer
R/W
1 = timer enabled, 0 = timer disabled. This bit enables THERM as an input. Default = 0.
1
Averaging Off
R/W
This bit is used to disable averaging at the slower conversion rates (8 Hz and slower).
Averaging is automatically disabled at the higher (16, 32, and 64 Hz ) conversion rates.
Default = averaging on = 0.
0
Monitor/STBY
R/W
Set bit to 1 to enable temperature monitoring. Set bit to 0 to disable it. Power-On Default = 1.
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ADM1033
Table 38. REGISTER 0X02, CONFIGURATION REGISTER 2, POWER-ON DEFAULT 0X84, LOCK = Y, S/W RESET = Y
Bit
Name
R/W
Description
7
Round Robin
R/W
This bit enables the round-robin mode. Set this bit to 0 to put the ADM1033 in
single-channel mode. The ADC converts on one channel only, which is determined
by the channel selector bits. Default = Round Robin = 1.
6
Reserved
R/W
Reserved
Channel Selector
R/W
This bit determines the channel on which the ADC converts.
00 = Local Channel Only
01 = Remote 1 Channel Only
10 = Reserved
11 = Reserved
3
Reserved
R/W
Reserved
2
Discrete/Linear Speed
R/W
This bit determines whether the fans run at discrete speeds or at speeds that
increase with temperature between the two thresholds. Default = 1 = Linear.
1
Boost Disable
R/W
Set bit to 1 to prevent the fans from being boosted if either THERM temperature or
THERM timer limits are exceeded. Under these conditions, the fan runs at the
previously calculated speed. Default = 0.
0
SW Reset
R/W
Set this bit to 1 to reset the ADM1033 registers to their default values, excluding the
limit registers, offset registers, and Look-up table registers. This bit self-clears.
Default = 0.
<5:4>
Table 39. REGISTER 0X03, CONFIGURATION REGISTER 3, POWER-ON DEFAULT 0X04, LOCK = Y, S/W RESET = Y
Bit
Name
R/W
Description
<7:4>
Reserved
R/W
Reserved
<3:0>
#Poles Fan
R/W
Write the number of poles in Fan to this register. power-on default = 4 poles = 100.
This should always be an even number, because there cannot be an odd number of
poles in a fan.
Table 40. REGISTER 0X04, CONFIGURATION REGISTER 4, POWER-ON DEFAULT 0X00, LOCK = Y, S/W RESET = Y
Bit
7
Name
R/W
Description
FAN_FAULT/REF
R/W
This bit sets the function for Pin 8. 0 = Default = FAN_FAULT output (THERM input
is CMOS). 1 = Reference input for THERM.
THERM % Time Window
R/W
These bits set the time window over which THERM % is calculated.
000 = 0.25 second
001 = 0.5 second
010 = 1 second
011 = 2 seconds
100 = 4 seconds
101 = 8 seconds
110 = 8 seconds
111 = 8 seconds
3
XOR Test
R/W
Set this bit to 1 to enable the XOR connectivity test.
2
Reserved
R/W
Reserved
1
Enable Remote 1 THERM
Events
R/W
This bit enables THERM assertions as an output. Functions when the THERM timer
is enabled and the Remote 1 temperature exceeeds its THERM limit.
0
Enable Local THERM
Events
R/W
This bit enables THERM assertions as an output. Functions when the THERM timer
is enabled and the local temperature exceeeds its THERM limit.
<6:4>
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ADM1033
Table 41. REGISTER 0X05, CONFIGURATION RATE REGISTER, POWER-ON DEFAULT 0X07, LOCK = Y, S/W
RESET = Y
Bit
Name
7
Reserved
<6:4>
Reserved
<3:0>
Conversion Rate
R/W
Description
R
This bit is reserved for future use. Do not write to this bit.
R
Reserved.
R/W
These four bits set the conversion rate of the ADM1033. Changing these bits does not
update the conversion rate until the start of the next round robin.
0000 = 0.0625 conversions/second
0001 = 0.125 conversions/second
0010 = 0.25 conversions/second
0011 = 0.5 conversions/second
0100 = 1 conversion/second
0110 = 4 conversions/second
0111 = 8 conversions/second = Default
1000 = 16 conversions/second
1001 = 32 conversions/second
1010 = 64 conversions/second
Table 42. REGISTER 0X06, FAULT QUEUE, POWER-ON DEFAULT 0X01, LOCK = Y, S/W RESET = Y
Bit
Name
<7:4>
Unused
<3:0>
Fault Queue Length
R/W
R
R/W
Description
Reserved.
These four bits set the fault queue (the number of out-of-limit measurements made
before an ALERT is generated).
000x = 1
001x = 2
01xx = 3
1xxx = 4
Table 43. REGISTER 0X07, FAN BEHAVIOR REGISTER, POWER-ON DEFAULT 0X01, LOCK = Y, S/W RESET = Y
Bit
Name
6
Fan 1 Off
5
Res
4
Res
<1:0>
DRIVE1 BHVR
R/W
R/W
Description
Set this bit to 1 to switch off Fan 1.
R
Reserved
R
Reserved
R/W
These bits determine which temperature source controls the DRIVE1 output.
00 = Local temperature controls DRIVE1
01 = Remote 1 temperature controls DRIVE1
10 = Remote 2 temperature controls DRIVE1
11 = DRIVE1 full speed
Table 44. REGISTER 0X08, MASK REGISTER 1, POWER-ON DEFAULT 0X50, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
7
Local High
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt output to
be set. The status bit is not affected. Default = 0.
6
Local Low
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt output to
be set. The status bit is not affected. Default = 1.
5
Remote 1 High
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt output to
be set. The status bit is not affected. Default = 0.
4
Remote 1 Low
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt output to
be set. The status bit is not affected. Default = 1.
3
Remote 1 Diode Error
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt output to
be set. The status bit is not affected. Default = 0.
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ADM1033
Table 45. REGISTER 0X09, MASK REGISTER 2, POWER-ON DEFAULT 0X18, LOCK = N, S/W RESET = Y
Bit
<7:5>
Name
Unused
R/W
R
Description
Unused
4
THERM %
R/W
A 1 disables the corresponding interrupt status bit, preventing it from causing the
interrupt output. The status bit is not affected. Default = 1.
3
THERM Assert
R/W
A 1 disables the corresponding interrupt status bit, preventing it from causing the
interrupt output. The status bit is not affected. Default = 0.
2
THERM_State
R/W
A 1 disables the corresponding interrupt status bit, preventing it from causing the
interrupt output. The status bit is not affected. Default = 0. This bit has no effect in
ALERT comparator mode, because the corresponding status bit does not generate an
ALERT in that mode.
<1:0>
Unused
R
Unused
Table 46. REGISTER 0X0A, MASK REGISTER 3, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
7
Fan 1 Stalled
R/W
A 1 disables the corresponding interrupt status bit, preventing it from causing the
interrupt output. The status bit is not affected. Default = 0.
6
Fan Alarm Speed
R/W
A 1 disables the corresponding interrupt status bit, preventing it from causing the
interrupt output. The status bit is not affected. Default = 0.
4
Reserved
R
Reserved. Default = 0.
3
Reserved
R
Reserved. Default = 0.
2
Reserved
R
Reserved. Default = 0.
1
Reserved
R
Reserved. Default = 0.
0
Reserved
R
Reserved. Default = 0.
Table 47. REGISTER 0X0B, LOCAL HIGH LIMIT, POWER-ON DEFAULT 0X8B, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Local High Limit
R/W
R/W
Description
When the local temperature exceeds this temperature, the corresponding interrupt
status bit is set.
Table 48. REGISTER 0X0C, LOCAL LOW LIMIT, POWER-ON DEFAULT 0X54, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Local Low Limit
R/W
R/W
Description
When the local temperature falls below this temperature, the corresponding interrupt
status bit is set.
Table 49. REGISTER 0X0D, LOCAL THERM LIMIT, POWER-ON DEFAULT 0X95, LOCK = Y, S/W RESET = Y
Bit
<7:0>
Name
Local THERM Limit
R/W
R/W
Description
When the local temperature exceeds this temperature, the corresponding status bit is
set and the THERM output is activated.
Table 50. REGISTER 0X0E, REMOTE 1 HIGH LIMIT, POWER-ON DEFAULT 0X8B, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Remote 1 High Limit
R/W
Description
R/W
When the Remote 1 temperature exceeds this temperature, the corresponding interrupt
status bit is set.
Table 51. REGISTER 0X0F, REMOTE 1 LOW LIMIT, POWER-ON DEFAULT 0X54, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Remote 1 Low Limit
R/W
R/W
Description
When the Remote 1 temperature falls below this temperature, the corresponding
interrupt status bit is set.
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ADM1033
Table 52. REGISTER 0X10, REMOTE 1 THERM LIMIT, POWER-ON DEFAULT 0X95, LOCK = Y, S/W RESET = N
Bit
<7:0>
Name
Remote 1 THERM
Limit
R/W
Description
R/W
When the Remote 1 temperature exceeds this temperature, the corresponding status bit
is set and the THERM output is activated.
Table 53. REGISTER 0X16, LOCAL OFFSET REGISTER, POWER-ON DEFAULT 0X00, LOCK = Y, S/W RESET = N
Bit
<7:0>
Name
Local Offset
R/W
R/W
Description
Allows a twos compliment offset to be automatically added to or subtracted from the
local temperature measurement. Resolution = 0.125C. Maximum offset from -16C to
+15.875C. Default = 0.
Table 54. REGISTER 0X17, REMOTE 1 OFFSET REGISTER, POWER-ON DEFAULT 0X00, LOCK = Y, S/W RESET = N
Bit
<7:0>
Name
Remote 1 Offset
R/W
R/W
Description
Allows a twos compliment offset to be automatically added to or subtracted from the
Remote 1 temperature measurement. Resolution = 0.125C. Maximum offset from
-16C to +15.875C. Default = 0.
Table 55. REGISTER 0X19, THERM TIMER % LIMIT, POWER-ON DEFAULT 0XFF, LOCK = Y, S/W RESET = N
Bit
<7:0>
Name
THERM Timer on %
Limit
R/W
R/W
Description
If the THERM is asserted for greater than this limit on the time window, the
corresponding status bit is set.
Table 56. REGISTER 0X1A, THERM HYSTERESIS, POWER-ON DEFAULT 0X05, LOCK = Y, S/W RESET = N
Bit
Name
<7:4>
Reserved
<3:0>
THERM Hysteresis
R/W
R
R/W
Description
Reserved
An unsigned THERM hysteresis value, LSB = 1C. Once THERM has been activated
on a temperature channel, the THERM limit – hysteresis is deactivated if the
temperature drops below THERM.
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ADM1033
Table 57. LOOK-UP TABLE REGISTERS, LOCK = Y, S/W RESET = Y
Register Address
R/W
0x22
R/W
Look-up Table, T1
Description
Power-On Default
0xFF
0x23
R/W
Look-up Table, T2
0xFF
0x24
R/W
Look-up Table, T3
0xFF
0x25
R/W
Look-up Table, T4
0xFF
0x26
R/W
Look-up Table, T5
0xFF
0x27
R/W
Look-up Table, T6
0xFF
0x28
R/W
Look-up Table, T7
0xFF
0x29
R/W
Look-up Table, T8
0xFF
0x2A
R/W
Look-up Table, FS1, LSB
0xFF
0x2B
R/W
Look-up Table, FS1, MSB
0xFF
0x2C
R/W
Look-up Table, FS2, LSB
0xFF
0x2D
R/W
Look-up Table, FS2, MSB
0xFF
0x2E
R/W
Look-up Table, FS3, LSB
0xFF
0x2F
R/W
Look-up Table, FS3, MSB
0xFF
0x30
R/W
Look-up Table, FS4, LSB
0xFF
0x31
R/W
Look-up Table, FS4, MSB
0xFF
0x32
R/W
Look-up Table, FS5, LSB
0xFF
0x33
R/W
Look-up Table, FS5, MSB
0xFF
0x34
R/W
Look-up Table, FS6, LSB
0xFF
0x35
R/W
Look-up Table, FS6, MSB
0xFF
0x36
R/W
Look-up Table, FS7, LSB
0xFF
0x37
R/W
Look-up Table, FS7, MSB
0xFF
0x38
R/W
Look-up Table, FS8, LSB
0xFF
0x39
R/W
Look-up Table, FS8, MSB
0xFF
Table 58. REGISTER 0X3A, LOOK-UP TABLE HYSTERESIS, POWER-ON DEFAULT 0X05, LOCK = Y, S/W RESET = Y
Bit
Name
R/W
<7:4>
Reserved
<3:0>
Look-up Table Hysteresis
R/W
R
Description
Reserved
These bits determine the hysteresis applied to the temperature thresholds in the
Look-up table. LSB size = 1C.
Table 59. REGISTER 0X3C, FAN RESPONSE REGISTER, POWER-ON DEFAULT 0X01, LOCK = Y, S/W RESET = Y
Bit
Name
R/W
Description
7
Res
R
Reserved
3
Res
R
Reserved
<2:0>
Fan 1 Response
R/W
These bits set the fan’s response in the fan speed control mode.
000 = 1.25 updates/second
001 = 2.5 updates/second = Default
010 = 5 updates/second
011 = 10 updates/second
100 = 20 updates/second
101 = 40 updates/second
110 = 80 updates/second
111 = 160 updates/second
Table 60. REGISTER 0X3D, DEVICE ID, POWER-ON DEFAULT 0X34, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Device ID
R/W
R
Description
This read-only value contains the device ID, which is 0x34.
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ADM1033
Table 61. REGISTER 0X3E, COMPANY ID, POWER-ON DEFAULT 0X41, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Company ID
R/W
R
Description
This read-only value contains the company ID, which is 0x41.
Table 62. REGISTER 0X3F, REVISION REGISTER, POWER-ON DEFAULT 0X02, LOCK = N, S/W RESET = N
Bit
<7:0>
Name
Revision ID
R/W
R
Description
This read-only value contains the revision ID.
Table 63. REGISTER 0X40/41, LOCAL TEMP REGISTERS, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
<4:0>
Local Temperature LSB
R
This register contains the LSBs of the last measured local temperature value.
Resolution = 0.03125C.
<12:5>
Local Temperature MSB
R
This register contains the MSBs of the last measured local temperature value.
Resolution = 1C.
Table 64. REGISTER 0X42/43, REMOTE 1 TEMP REGISTERS, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
<4:0>
Remote 1 Temperature LSB
R
This register contains the LSBs of the last measured Remote 1 temperature
value. Resolution = 0.03125C.
<12:5>
Remote 1 Temperature MSB
R
This register contains the LSBs of the last measured Remote 1 temperature
value. Resolution = 1C.
Table 65. REGISTER 0X4A/4B, TACH1 PERIOD, POWER-ON DEFAULT 0XFF, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
<7:0>
Fan 1 Period Count, LSB
R
This register contains the LSBs of the last measured Fan 1 revolution count.
<15:8>
Fan 1 Period Count, MSB
R
This register contains the MSBs of the last measured Fan 1 revolution count.
Table 66. REGISTER 0X4E, THERM % ON-TIME, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
<7:0>
Name
THERM % On-Time
R/W
R
Description
Represents the % time of THERM activity within the time window set by the
configuration bits.
Table 67. REGISTER 0X4F, STATUS 1, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
7
Local Temp High
R
A 1 indicates that the local high limit has been tripped.
6
Local Temp Low
R
A 1 indicates that the local low limit has been tripped.
5
Remote 1 Temp High
R
A 1 indicates that the Remote 1 high limit has been tripped.
4
Remote 1 Temp Low
R
A 1 indicates that the Remote 1 low limit has been tripped.
3
Remote 1 Diode Error
R
A 1 indicates that a short or an open has been detected on the Remote 1
temperature channel. This test is completed once on each conversion.
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ADM1033
Table 68. REGISTER 0X50, STATUS 2, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
7
Local THERM
R
A 1 indicates that the local THERM limit has been tripped.
6
Remote 1 THERM
R
A 1 indicates that the Remote 1 THERM limit has been tripped.
4
THERM % Exceeded
R
A 1 indicates that the THERM signal has been asserted for longer than the programmed
limit. Clear on Read. If THERM % Limit = 0x00 and THERM is asserted, it is reasserted
immediately.
3
THERM Asserted
R
A 1 indicates that the THERM signal has been asserted low as an input only.
2
THERM_State
R
A 1 indicates that the THERM pin has been asserted low as an output.
1
Reserved
R
Reserved
0
Reserved
R
Reserved
Table 69. REGISTER 0X51, STATUS REGISTER 3, POWER-ON DEFAULT 0X00, LOCK = N, S/W RESET = Y
Bit
Name
R/W
Description
7
Fan 1 Stalled
R
A 1 indicates that Fan 1 has stalled.
6
Fan Alarm Speed
R
A 1 indicates that the fans are running at full speed due to an alarm condition, for
instance, when a THERM temperature limit is exceeded.
4
Reserved
R
Reserved
3
Reserved
R
Reserved
2
Reserved
R
Reserved
1
Reserved
R
Reserved
0
ALERT Low
R
A 1 indicates that the ADM1033 has pulled the ALERT output pin low. This allows
polling of a single status register to determine if an ALERT condition in any of the status
registers has occurred.
Table 70. ORDERING INFORMATION
Device Number*
Temperature Range
Package Type
Package Option
Shipping†
ADM1033ARQZ−REEL
−40C to +125C
16-lead QSOP
RQ−16
2,500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*The “Z’’ suffix indicates Pb-Free part.
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ADM1033
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE A
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.005 PER SIDE. D AND E1 ARE
DETERMINED AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
0.20 C D
D
16
L2
D
A
9
GAUGE
PLANE
SEATING
PLANE
E
E1
C
L
C
DETAIL A
2X
2X 10 TIPS
0.20 C D
1
8
16X
e
B
A2
0.10 C
0.10 C
16X
b
0.25
A1
C
0.25 C D
M
C A-B D
h x 45 _
H
A
SEATING
PLANE
DETAIL A
M
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
INCHES
MIN
MAX
0.053
0.069
0.004
0.010
0.049
---0.008
0.012
0.007
0.010
0.193 BSC
0.237 BSC
0.154 BSC
0.025 BSC
0.009
0.020
0.016
0.050
0.010 BSC
0_
8_
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
1.24
---0.20
0.30
0.19
0.25
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.22
0.50
0.40
1.27
0.25 BSC
0_
8_
SOLDERING FOOTPRINT
16X
16X
0.42
16
1.12
9
6.40
1
8
0.635
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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ADM1033/D
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