A8426 Datasheet

A8426
High Performance Photoflash Capacitor Charger
with IGBT Driver
Features and Benefits
Description
▪ Wide battery voltage range: 1.5 to 11 V
▪ Integrated 55 V DMOS switch with 3.2 A current capability
▪ User-adjustable peak current limit, from 1 to 3.2 A
▪ Secondary-side voltage sensing for easily-adjustable
output voltage
▪ >75% efficiency
▪ Fast charging time
▪ Charge complete indication
▪ Flexible, high current IGBT driver
▫ Independent IGBT driver supply
▫ Separate sink and source pins with 6 Ω pull-up and
20 Ω pull-down
▫ Interlocked trigger pins improve noise immunity
▪ No primary-side Schottky diode needed
The A8426 is a highly integrated IC that rapidly charges
photoflash capacitors for SLR cameras, digital cameras, and
camcorders with integrated digital cameras. A flexible IGBT
driver is integrated to save board space.
The A8426 integrates a 3.2 A-capable, 55 V-rated DMOS switch
that drives the transformer in flyback configuration, allowing
optimized design with tight coupling and high efficiency. The
peak switch current is user-adjustable between 1 and 3.2 A,
using a resistor to ground. A proprietary control scheme
optimizes the capacitor charging time. Low quiescent current
and low-power Standby mode current further improve system
efficiency and extend battery life.
The A8426 is available in a 16-contact 3 mm × 3 mm TQFN
package with exposed pad for enhanced thermal performance.
This small, very thin profile (0.75 mm nominal overall height)
package is ideal for space-constrained applications. It is lead
(Pb) free, with 100% matte-tin leadframe plating.
Package: 16-contact TQFN (suffix ES)
Applications include:
▪ SLR camera flash
▪ Digital camcorder/DSC combo flash
▪ 2 Li+ input strobe
Approximate Scale 1:1
Typical Application
Bias Input
3.0 to 5.5 V
Battery Input
1.5 to 11 V
VBAT
1 : 10
+
C2
COUT
C1
100 μF
330 V
VIN
TLIM
SW
R1
150 k7
ISET
Control
Block
R2
150 k7
ISW sense
RSET
FB
VPULLUP
CHARGE
R3
1.20 k7
DONE
100 kΩ
DONE
TRIGGER1
VDRV
IGBT Driver
GSOURCE
IGBT Gate
TRIGGER2
GSINK
GND
Figure 1. Typical application circuit with resistor bridge control of feedback.
A8426-DS, Rev. 1
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Selection Guide
Part Number
A8426EESTR-T
Packing*
Tape and reel, 1500 pieces/reel
*Contact Allegro for additional packing options.
Absolute Maximum Ratings
Characteristic
Symbol
SW Pin
VSW
VIN Pin
VIN
Notes
Remaining Pins
Characteristic
V
–0.3 to 7
V
–0.3 to VIN + 0.3 V
V
–40 to 85
ºC
150
ºC
Tstg
–55 to 150
ºC
TA
Storage Temperature
Package Thermal Resistance
Range E
Units
TJ(max)
Operating Ambient Temperature
Maximum Junction
Rating
–0.3 to 55
Symbol
RθJA
Test Conditions*
On 4-layer PCB based on JEDEC standard
Value
Units
47
ºC/W
*Additional thermal information available on Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
13 NC
14 FB
8
9
TRIGGER2
4
10 TRIGGER1
7
GND
11 DONE
EP
NC
3
6
VIN
12 TLIM
5
2
NC
1
GSINK
CHARGE
GSOURCE
15 ISET
16 VDRV
Pin-out Diagram
SW
(Top View)
Terminal List Table
Number
1
2
3
Name
GSOURCE
GSINK
VIN
4
GND
5
CHARGE
Function
IGBT gate drive – source connection
IGBT gate drive – sink connection
IC bias input, connect to a 3.0 to 5.5 V supply; for single Li+ battery applications this pin may be connected to the
battery with sufficient decoupling
Ground connection
Pull high to initiate charging; pull low to enter low-power standby mode
6, 7, 13
NC
8
TRIGGER2
No connection
9
SW
10
TRIGGER1
11
¯N̄¯Ē¯
D̄¯Ō
12
TLIM
14
FB
15
ISET
Sets the maximum switch current; connect an external resistor to GND to set the target peak current
16
VDRV
Supply for IGBT gate driver
–
EP
IGBT input trigger 2; internally ANDed with TRIGGER1 pin
Swtich pin; drain connection of internal power DMOSFET switch
IGBT input trigger 1; internally ANDed with TRIGGER2 pin
Open drain pin; indicates charge complete when pulled low by internal MOSFET
For production test only; connect to GND on PCB
Output feedback
Exposed pad for enhanced thermal dissipation
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Functional Block Diagram
SW
VIN
DCM‫ޓ‬Detector
tOFF(max)
DMOS
18 μs
OCP
H→L
Triggered
‫ޓ‬Timer
㧗
VDS Ref
ISET
㧙
ISET
Buffer
S
Q
R
㧙
Q
Enable
tON(max)
18 μs
DONE
VFB
㧗
Vth
㧙
CHARGE
S
Q
R
㧙
Q
One-Shot
VDRV
GSOURCE
TRIGGER1
GSINK
TRIGGER2
Exposed Pad
GND
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115 Northeast Cutoff, Box 15036
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4
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
ELECTRICAL CHARACTERISTICS typical values valid at VIN = 3.6 V, RSET = 33.2 kΩ, ISWlim = 2.0 A, and TA=25°C, unless otherwise noted
Characteristics
VBAT Pin Voltage
Range1
VIN Pin Voltage Range1
UVLO Enable Threshold
Symbol
Min.
Typ.
VBAT
1.5
VIN
3.0
VINUV
UVLO Hysteresis
Test Conditions
VIN rising
VINUVhys
Switch Current Limit2
SW Current Limit to ISET Current Ratio
ISET Pin Voltage While Charging
Unit
–
11
V
–
5.5
V
2.55
2.65
2.75
V
–
150
–
mV
2.9
3.2
3.5
A
ISWlimMAX
Maximum, RSET = 21.8 kΩ
ISWlimMIN
Minimum, RSET = 72 kΩ
–
1.0
–
A
RSET = 21.8 kΩ, CHARGE = high
–
58.5
–
kA/A
RSET = 35 kΩ, CHARGE = high
–
1.2
–
V
–
330
–
Ω
VIN = 3.6 V, ID = 800 mA, TA = 25°C
–
0.2
–
Ω
VSW = VBAT(max), in shutdown
–
–
1
μA
Shutdown (CHARGE = low, TRIGGER = low)
–
0.01
1
μA
¯N̄¯Ē¯ = low)
Charging done (CHARGE = high, D̄¯Ō
–
25
100
μA
Charging (CHARGE = high, TRIGGER = low)
–
2
–
mA
CHARGE = VIN
–
36
–
μA
V
ISWlim/ISET
VSET
ISET Pin Internal Resistance
RSET(INT)
Switch On-Resistance
RSWDS(on)
Switch Leakage Current1
ISWlk
VIN Pin Supply Current
IVIN
CHARGE Pin Input Current
Max.
ICHARGE
High1
ICHARGE(H)
Over input supply range, VIN
1.4
–
–
CHARGE Pin Input Voltage Low1
ICHARGE(L)
Over input supply range, VIN
–
–
0.4
V
CHARGE Pin Pull-down Resistor
RCHARGE
–
100
–
kΩ
Maximum Switch-off Timeout
toffMAX
–
18
–
μs
Maximum Switch-on Timeout
tonMAX
–
18
–
μs
CHARGE Pin Input Voltage
¯N̄¯Ē¯ Pin Output Leakage
D̄¯Ō
Current1
¯N̄¯Ē¯ Pin Output Low Voltage1
D̄¯Ō
FB Threshold1
IDONElk
VDONEL
¯N̄¯Ē¯ pin
32 μA into D̄¯Ō
VFBth
IFB
FB Input Current
Minimum dV/dt for ZVS Comparator
dV/dt
–
–
1
μA
–
–
100
mV
1.187
1.205
1.223
V
VFB = 0 V to VIN
–
12
–
nA
Measured at SW pin
–
20
–
V/μs
3
–
5.5
V
–
36
–
μA
–
–
V
IGBT Driver
VDRV Pin Supply Voltage (for IGBT Driver)1
VDRV
TRIGGERx Pins Input Current
ITRIG
TRIGGERx Pins High Input Voltage1
VTRIGGER = VIN
VTRIG(H)
Over input supply range, VIN
1.4
Voltage1
VTRIG(L)
Over input supply range, VIN
–
–
0.4
V
TRIGGERx Pins Pull-down Resistor
RTRIGPD
–
100
–
kΩ
TRIGGERx Pins Low Input
GSOURCE On-Resistance to VDRV
RSrcDS(on)
VDRV = 3.6 V, VGSOURCE= 1.8 V
–
6
–
Ω
GSINK On-Resistance to GND
RSnkDS(on)
VDRV = 3.6 V, VGSINK= 1.8 V
–
20
–
Ω
Propagation Delay (Rising)
tdr
–
30
–
ns
Propagation Delay (Falling)
tdf
–
140
–
ns
Output Rise Time
tr
Output Fall Time
tf
Connect GSOURCE to GSINK, RGATE = 12 Ω,
CLOAD= 6500 pF, VDRV = 3.6 V
–
80
–
ns
–
320
–
ns
1Specifications
2Current
over the range TA= –40°C to 85°C; guaranteed by design and characterization.
limit guaranteed by design and correlation to static test. Refer to Application Information section for peak current in actual circuits.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Symbol
Parameter Units/Division
C1
VOUT
50 V
C2
VBAT
2V
C3
IIN
250 mA
t
time
500 ms
Conditions Parameter
Value
VIN
3.6 V
VBAT
3.6 V
COUT
100 μF/330 V
Transformer = DCT9.5/5ER, LP = 7 μH, N = 10
VOUT
VBAT
Conditions
Parameter
RSET
IP
Value
25 kΩ
≈3.15 A
C1
C2
C3
C1
C2
IIN
C3
tCHARGE= 1.77 s
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
IP
Value
30 kΩ
≈2.6 A
C1
C2
C3
C2
IIN
C3
tCHARGE= 2.17 s
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
IP
Value
45 kΩ
≈1.8 A
C1
C2
C3
C2
IIN
tCHARGE= 3.58 s
C3
t
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Performance Characteristics
0 to 325 V Efficiency versus Battery Voltage
Charge Time versus Battery Voltage
Transformer SBL-5.6-1; VIN= 3 V; Diode = BAV23S; COUT= 100 μF UCC; TA=22°C
Transformer Lp= 7 μH, N = 10; VIN = 3.6 V; COUT= 100 μF / 330 V UCC; TA=25°
82
RSET
(kΩ)
58
4.5
4.0
Time (s)
3.5
80
IP
(A)
≈ 1.4
78
45
≈ 1.8
76
36.5
≈ 2.2
74
30
≈ 2.6
25
≈ 3.2
Efficiency (%)
5.0
3.0
2.5
72
70
68
RSET
(kΩ)
22.1
66
2.0
64
1.5
62
1.0
IP
(A)
≈ 1.5
33.2
≈1
45
≈ 0.77
55
≈ 0.65
60
0.5
58
2.0
3.0
4.0
5.0
6.0
7.0
8.0
1
VBAT (V)
COUT= 100 μF. For larger or smaller capacitances, charging time
scales proportionally.
2
3
4
5
6
VBAT (V)
7
8
9
10
11
This data was obtained using a Kijima-Musen SBL-5.6-1 transformer
(LP = 9.8 μH, N = 10.2). Highest efficiency is achieved at high battery
voltage and large peak current (1 to 1.5 A). At lower current (< 1 A),
switching frequency increases and so do switching losses. Therefore a
transformer with higher primary inductance is preferred when operating
at lower current.
Average Input Current versus Battery Voltage
VIN = 3.6 V, Transformer Lp= 7 μH,
N = 10, COUT= 100 μF 330 V UCC, TA= 25°C
1.50
1.40
1.30
1.20
IIN (A)
1.10
RSET
(kΩ)
25
30
36.5
45
58
1.00
0.90
0.80
IP
(A)
≈ 3.2
≈ 2.6
≈ 2.2
≈ 1.8
≈ 1.4
0.70
0.60
0.50
0.40
0.30
2.0
3.0
4.0
5.0
6.0
7.0
8.0
VBAT (V)
The average input current decreases with higher VBAT. .
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Timing and IGBT Interlock Function
The two TRIGGER signals are internally ANDed together. As
shown in the timing diagram, below, triggering is prohibited during the initial charging process. This prevents premature firing
of the flash before the output capacitor has been charged to its
target voltage. Refer to the section IGBT Gate Driver Interlock
for details.
UVLO
VIN
CHARGE
SW
Target VOUT
VOUT
DONE
TRIGGER
T1
T3
T2
IGBTDRV
A
B
C
D
E
F
Explanation of Events
A
Start charging process by pulling CHARGE pin high, provided that VIN is above the UVLO level.
¯N̄¯Ē
¯ pins are both high).
Triggering (T1) is blocked during the charging process (CHARGE and D̄¯Ō
B
Charging stops when VOUT reaches the target voltage level. Triggering (T2) is enabled after
¯N̄¯Ē¯ pin is low).
completion of charging (CHARGE pin is high and D̄¯Ō
C
Start a new charging process with a low-to-high transition at the CHARGE pin.
D
Pull the CHARGE pin low to put the controller into the low-power Standby mode. Triggering (T3) is
always enabled when CHARGE is low.
E
Charging does not start, because VIN is below the UVLO level when the CHARGE pin goes high.
F
After VIN goes above the UVLO level, another low-to-high transition at the CHARGE pin is required
to start the charging process.
IGBT Drive Timing Definition
TRIGGER
50%
tdr
GSOURCE
or GSINK
50%
tr
tdf
90%
10%
tf
90%
10%
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115 Northeast Cutoff, Box 15036
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A8426
High Performance Photoflash Capacitor Charger
with IGBT Driver
Application Information
mended values are:
Circuit Description
The A8426 is a photoflash capacitor charger control
IC with a high current limit (up to 3.2 A) and low
RDS(on) (0.23 Ω maximum). The IC also integrates an
IGBT driver for strobe operation of the flash, dramatically saving board space in comparison with discrete
solutions for strobe flash operation.
R1 = R2 = 150 kΩ (type 1206), and
R3 = 1.20 kΩ (type 0603),
which together yield a target voltage of 300 V.
Using higher resistance ratings for R1, R2, and R3
does not offer significant efficiency improvement,
because the power loss of the feedback network occurs
mainly during switch off-time, and off-time is only a
small fraction of each charging cycle. Furthermore, if
values of R1 and R2 are too high, effects of parasitic
capacitance from the sensing network to GND may
affect the accuracy of the target voltage.
The IC is turned on by a low-to-high signal on the
CHARGE pin, provided that VIN is above the UVLO
level. Note that if CHARGE is already high before
VIN reaches the UVLO threshold, charging will not
start until CHARGE goes through another low-to-high
transition. When the charging cycle is initiated, the
primary current ramps up linearly at a rate determined
by the battery voltage and the primary side inductan
ce. When the primary current reaches the set limit, the
internal MOSFET is turned off immediately to allow
the energy to be dumped into the photoflash capacitor
through the secondary winding. The secondary current
drops linearly as the output capacitor is charged. The
charging cycle starts again when the transformer flux
is reset or after a predetermined time period (18 μs
maximum off-time) has passed, whichever occurs first.
When the designated output voltage is reached, the
A8426 stops the charging until the CHARGE pin is
toggled again. Alternatively, pulling the CHARGE
pin low also stops the charging. The D̄¯¯ Ō¯¯N̄¯Ē¯ pin is an
open-drain indicator of when the designated output is
reached. Pulling the CHARGE pin low puts the A8426
into the low-current Standby mode and it forces the
¯ pin into a high impedence mode, irrespective of
D̄¯¯ Ō¯¯N̄¯Ē
the output voltage.
Target Output Voltage
Switch Current Limiting
Output voltage sensing is done using a resistor divider
network (see figure 1: R1, R2 and R3) on the secondary side of the transformer. The target output voltage
is determined by the ratio of the voltage divider:
The peak switch current limit is determined by a resistor, RSET, connected between the ISET pin and GND.
The value of RSET can be between 22 and 72 kΩ.
This generates an ISET current between 17 and 55 μA,
which corresponds to a desired peak switch current in
a range from 1 to 3.2 A.
(R1 + R2 + R3) / R3 = (VOUT + Vd ) / VFB ,
(1)
where Vd is the diode voltage drop (typically 1 to 2 V).
R1 and R2 together must have a breakdown voltage
of at least 300 V. A typical type 1206 surface mount
resistor has a 150 V breakdown voltage rating. It is
recommended that R1 and R2 have similar values to
ensure an even voltage stress between them. Recom-
Smart Current Limit (Optional)
With the help of some simple external logic, the user
can change the charging current according to the battery voltage. For example, assume that ISET is normally 50 μA (for ISWlim = 2.75 A). Referring to the
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115 Northeast Cutoff, Box 15036
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9
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
following illustration, when the battery voltage drops
below 2.5 V, the signal at BL (battery-low) should go
high. The resistor RBL, connecting BL to the ISET
pin, then injects 20 μA into RSET. This effectively
reduces ISET current to 30 μA (for ISWLIM = 1.65 A).
The disadvantage of this method is that 20 μA flows
continuously while BL is high.
BL
RBL
ISET
Selection of Transformer
1. The primary inductance, LP , determines the on-time
of the switch, as follows:
ton = –LP / R × ln (1 – ISWlim × R / VBAT) , (2)
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
If VBAT is much larger than ISWlim × R, then ton can be
approximated using the following formula:
RSET
ton = ISWlim × LP / VBAT .
In another example of a possible application, we can
make use of a PTC thermistor to decrease the switch
current limit when the board temperature exceeds
65°C. Refering to the following figure, R3 is a
PTC type thermistor such as the Murata
PRF18BG471QB1RB.
RSET
R1
54.9 kΩ
+t°
ISET
R2
45.3 kΩ
R3
470 Ω
In this configuration, the peak currents at various PCB
temperatures are as follows:
TPCB
(°C)
R3
(kΩ)
RSET
(kΩ)
ISWpeak
(A)
25
0.470
25.0
3.2
65
4.7
26.2
3.0
80
47.0
34.4
2.3
(3)
2. The secondary inductance, LS, determines the offtime of the switch, as follows:
toff = (ISWlim / N ) × LS / VOUT .
(4)
Because LS / LP = N × N:
toff = (ISWlim × LP × N ) / VOUT .
(5)
The minimum pulse width for toff determines the
minimum primary inductance required for the transformer. For example, if ISWlim = 1.0 A, N = 10, and
VOUT = 315 V, then LP must be at least 6.3 μH in order
to keep toff at 200 ns or longer. In general, choosing a
transformer with larger LP results in higher efficiency
(because the higher the value of LP , the lower the
switch frequency, and hence the lower the switching
loss). But transformers with higher LP ratings also
require more windings and larger magnetic cores.
Therefore a trade-off must be made between transformer size and efficiency.
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Selection of Switching Current Limit
The A8426 features continuously adjustable peak
switching current between 1.0 and 3.2 A. This is done
by selecting the value of the external resistor RSET
(connected between the ISET pin and GND), which
determines the ISET bias current, and therefore the
switching current limit, ISWlim.
To the first order approximation, ISWlim is related to
ISET and RSET by the following equation:
transformer primary inductance, LP . If necessary, the
following expressions can be used to determine ISWlim
more accurately:
ISET = VSET / (RSET + RSET(INT) – K × RG(INT) ) ,(7)
where RSET(INT) is the internal resistance of the ISET
pin (330 Ω typical), RG(INT) is the internal resistance
of the bonding wire for the GND pin (27 mΩ typical),
and:
ISWlim = ISET × (K' + VIN × K")
+ (VBAT / LP ) × td ,
ISWlim = ISET × K
= (VSET × RSET ) × K ,
(6)
where K ≈ 60000 when the IC bias voltage, VIN , is
3.6 V.
In real applications, the switching current limit is
affected by bias voltage, battery voltage, and the
(8)
where K' = 47500, K" = 3500, and td = delay in SW
turn-off (0.12 μs typical).
Figure 2 shows the relationship between RSET and
ISWlim at different bias voltages, VIN, when battery
voltage, VBAT, is fixed at 3.6 V.
Peak Current Limit versus ISET Resistance at Various Bias Voltages
VBAT = 3.6 V, Transformer LP = 7.5 μH, TA=25°C
3.4
3.2
3.0
2.8
VIN = 5.0 V
2.6
ISWlim (A)
2.4
VIN = 3.6 V
2.2
VIN = 3.0 V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
RSET (kΩ)
Figure 2. Chart of current versus limit settings, at fixed battery voltage
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Figure 3 shows the relation between RSET and ISWlim
at different battery voltages, when bias voltage is fixed
at 3.6 V). Note that the spread is inversely proportional to the primary inductance of transformer used.
Fast Charging and Timer Modes
The A8426 achieves fast charging time and high
efficiency by operating in discontinuous conduction
mode (DCM) with zero-voltage-switching (ZVS). This
operation is shown in figure 4.
The IC operates in the Timer mode when beginning to
charge a completely discharged photoflash capacitor,
usually when the output voltage, VOUT, is less than
approximately 35 V (depending on the inductance of
transformer used). Timer mode is a fixed 18 μs offtime control. One advantage of the timer mode is that
it limits the initial battery current surge and thus acts
as a “soft-start,” as shown in figure 5.
As soon as sufficient voltage has built up at the output
capacitor, the IC changes into fast-charging mode.
Peak Current Limit versus ISET Resistance
VIN = 3.6 V, Transformer LP = 7 μH, TA = 25°C
3.4
3.2
3.0
2.8
VBAT = 8.0 V
2.6
VBAT = 3.6 V
ISWlim (A)
2.4
2.2
VBAT = 1.5 V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
RSET (kΩ)
Figure 3. Chart of current versus limit settings, at fixed bias voltage
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8426
High Performance Photoflash Capacitor Charger
with IGBT Driver
As shown in figure 6, in this mode the next switching cycle starts after the secondary-side current has
stopped flowing, and the switch voltage has dropped
to a minimum value. A special dV/dt detection circuit
is used to allow minimum-voltage switching, even if
the SW voltage does not drop to zero volts. This
enables fast-charging to start earlier than previously
possible, thereby reducing the overall charging time.
When output voltage is high enough (such that
Vr = VOUT/ N is greater than VBAT ), true zero-voltage
switching is achieved, which further improves efficiency as well as reducing switching noises (figure 7).
VOUT
Timer Mode
VSW
Fast Charging Mode
VOUT
VBAT
VBAT
IIN
t =500 ms/div; VOUT =50 V/div; VBAT =1 V/div.; IIN =250 mA/div.
VBAT =3.6 V; COUT =100 μF/330 V; RSET=36.5 kΩ (IP ≈ 2.2 A)
Figure 4. Relationship of Timer mode and Fast Charging mode
ISW
t = 2 μs/div; VOUT =10 V/div; VBAT =3 V/div.; VSW =3 V/div;
ISW =500 mA/div. VIN = 3.6 V; VBAT =8.0 V; RSET=36.5 kΩ (IP ≈ 2.2 A);
Transformer =DCT9.5/5ER, LP= 7 μH, N = 10
Figure 6. Fast-charging mode (DCM), VOUT > 35 V
VSW
VOUT
VSW
VSW
VOUT
VOUT
VBAT
VBAT
VBAT
ISW
ISW
ISW
t = 2 μs/div; VOUT =10 V/div; VBAT =3 V/div.; VSW =3 V/div;
ISW =500 mA/div. VIN = 3.6 V; VBAT =8.0 V; RSET=36.5 kΩ (IP ≈ 2.2 A);
Transformer =DCT9.5/5ER, LP= 7 μH, N = 10
Figure 5. Timer mode (CCM), VOUT < 35 V
t = 1 μs/div; VOUT =20 V/div; VBAT =3 V/div.; VSW =3 V/div;
ISW =500 mA/div. VIN = 3.6 V; VBAT =8.0 V; RSET=36.5 kΩ (IP ≈ 2.2 A);
Transformer =DCT9.5/5ER, LP= 7 μH, N = 10
Figure 7. Zero-voltage switching
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Components Recommendation
IGBT Gate Driver Interlock
The A8426 uses secondary-side sensing, so the turns
ratio, N, of the transformer is not critical for the final
target voltage. However, using transformers with
higher turns ratios (N = 12 or higher) generally results
in lower efficiency and longer charge time.
The TRIGGER1 and TRIGGER2 pins are ANDed
together inside the IC to control the IGBT gate driver.
If only one TRIGGER pin is used, the other TRIGGER pin must be tied to the VIN pin to ensure that the
unused TRIGGER pin is at logic high.
Selection of the flyback transformer should be based
on the peak current, according to the following table:
IPeak Range
Sup-
(A)
plier
LP
1.0 to 2.0
TDK
LDT565630T-001
6
10.4
1.0 to 3.2
TDK
DCT9.5/5ER-UxxS003
7.6
10
1.4 to 3.2
TCE
T-17-160 (TTRN-060)
5.6
Part Number
(μH)
N
10.2
Triggering is disabled (locked) during charging. This
is to prevent switching noise from interfering with the
IGBT driver. After the CHARGE pin goes high (at the
start of a charging cycle), the IC must wait for comple¯¯¯¯ Ō¯¯N̄¯Ē
¯ goes low) before
tion of the charging cycle (D
triggering can be enabled, according to the following
chart:
Conditions
IGBT Gate Driver Application
The integrated IGBT driver is used to drive an external
flash trigger IGBT. A dedicated VDRV pin is provided
to supply optimum voltage for the internal IGBT.
Separate GSOURCE and GSINK pins allow the user
to adjust IGBT turn-on and turn-off rise times. For
the Electrical Characteristics table in this document,
IGBT drive timing is defined with the GSOURCE and
GSINK pins connected together, and supplying a load
comprising a 12 Ω resistor and a 6500 pF capacitor.
ton
Resulting State
CHARGE
¯N̄¯Ē¯
D̄¯Ō
IGBT Gate Driver
Low
Don’t Care
Enabled
High
High
Disabled
High
Low
Enabled
The IGBT gate driver is always enabled when the
CHARGE pin is low.
It is up to the system-level programming to ensure that
a trigger signal is not applied without sufficient voltage at the output capacitor.
toff
VSW
ISW
Vr
tf
VIN
VIN
ISW
VSW
tneg
Figure 8. Relationship of toff and switch output.
14
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Package ES, 3 mm x 3 mm 16-Contact TQFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.90
16
1
2
A
0.50
16
1
3.00 ±0.15
1.70
3.10
1.70
17X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
3.10
C
PCB Layout Reference View
0.75 ±0.05
0.50
For reference only
(reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.15
0.40 –0.10
A Terminal #1 mark area
B
1.70
2
1
16
1.70
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
High Performance Photoflash Capacitor Charger
with IGBT Driver
A8426
Revision History
Revision
Revision Date
Description of Revision
Rev. 1
April 19, 2012
Update Selection Guide, miscellaneous format changes
Copyright ©2008-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
16
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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