BELASIGNA200 D

BelaSigna 200
1.0 General Description
BelaSigna 200 is a high-performance, programmable, mixed-signal digital signal processor (DSP) that is based on
ON Semiconductor’s patented second-generation SignaKlara™ technology.
This single-chip solution is ideally suited for embedded applications where audio performance, low power consumption and
miniaturization are critical. BelaSigna 200 targets a wide variety of digital speech- and audio-centric applications, including:
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Communication headsets
Smart phones
Personal digital assistants (PDAs)
Hands-free car kits
Bluetooth™ wireless technology systems
BelaSigna 200 provides numerous analog and digital interfaces including parallel, serial, synchronous, and asynchronous interfaces to
facilitate the connection with transducers from various applications.
BelaSigna 200 contains two primary processing blocks, which all work together to provide a complete audio processing chain. The
analog section includes two 16-bit A/D converters and two 16-bit D/A converters. Two on-chip direct digital output stages allow
BelaSigna 200 to drive various output transducers directly, eliminating the need for external power amplifiers.
BelaSigna 200 features internal clock generation and power regulation for excellent noise and power performance. Two DSP
subsystems operate concurrently: the RCore, which is a fully programmable DSP core, and the weighted overlap-add (WOLA)
filterbank coprocessor, which is a dedicated, configurable processor that executes time-frequency domain transforms and other vectorbased computations. In addition to these processors, there are several other peripherals, which optimize the architecture to audio
processing, such as the onput/output processor (IOP) – an audio-targeted direct memory access (DMA) processor, which runs in the
background and manages the data flow between the converters and the two processors. The BelaSigna 200 functional block diagram is
shown in Figure 1.
Figure 1: BelaSigna 200 Functional Block Diagram
©2008 SCILLC. All rights reserved.
June 2008 – Rev. 16
Publication Order Number:
BELASIGNA200/D
BelaSigna 200
2.0 Key Features
2.1 System
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16-bit programmable fixed-point DSP core
Configurable WOLA filterbank coprocessor optimized for filterbank calculations
12-Kword program memory (PRAM)
Two 4-Kword data memories (XRAM and YRAM)
Two 384-word dual-port FIFO memories
Two 128-word dual-port 18-bit memories dedicated to WOLA output results
576-word memory dedicated to WOLA gain values, WOLA windows and other configuration data
Internal oscillator
Operating voltage of 1.8V nominal
Ultra-low power: less than 1mW @ 1.28MHz system clock frequency, 1.8V nominal operating voltage, both processors running
Available in a QFN package; other packages available upon request
2.2 RCore DSP
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Dual-Harvard architecture, 16-bit programmable fixed-point DSP with three execution units
Single-cycle multiply-accumulate (MAC) with 40-bit accumulator
Highly parallel instruction set with powerful addressing modes
Flexible address generation (including modulo addressing) for accessing program memory and data memories, plus control and
configuration registers
Separate system and user stacks with dedicated stack pointers
Fast normalization and de-normalization operations optimized for signal level calculation and block-floating point calculations
Supports time-domain pre- and post-processing of input data stream and frequency-domain processing of WOLA output
Master processor for entire system
2.3 WOLA Filterbank Coprocessor
• Mono and stereo time-frequency transforms providing real or complex data results
• Standard library of overlap-add (OLA) and WOLA filterbank configurations
o Configurable number of frequency bands
o Configurable number of frequency bands
o Configurable oversampling and decimation factors
o Configurable windows
• Low group delay (< 4ms for 16 bands possible)
• Fast real and complex gain application for magnitude and phase processing
• Block floating-point calculations (4-bit exponent, 18-bit mantissa) to achieve high fidelity
• Maximum digital gain of 90dB possible
• High-fidelity time-frequency domain processing
• Low-overhead interaction with the RCore through shared memories, control registers and interrupts
2.4 Input Output Processor (IOP)
• Block-based DMA for all audio data provides automatic management of input and output FIFOs that reduces processor overhead
• Mono (one in, one out), simple stereo (two in, one out), full stereo (two in, two out) and digital mixed (two in, one out) operating
modes
• Interacts with the RCore through interrupts and shared memories
• Normal and smart FIFO audio data accessing schemes available
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BelaSigna 200
2.5 Input Stage
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Two separate input channels, each with two multiplexed inputs
Two configurable preamplifiers for improved input dynamic range matching
Two analog third-order anti-aliasing filters
Two 16-bit oversampling ΣΔ A/D converters
Two ninth-order low-delay wave digital filters (WDFs) for decimation and DC removal with configurable digital gains for optimal
channel matching
2.6 Output Stage
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Two output channels (full stereo)
Two 16-bit oversampling ΣΔ D/A converters
Two line-level analog outputs
Two configurable output attenuators for improved output dynamic range matching
Two analog third-order anti-aliasing filters
Two pulse-density modulation (PDM)-based direct digital outputs capable of driving low-impedance loads
2.7 Peripherals and Interfaces
2.7.1. Analog Interfaces
• Six external low-speed A/D converter (LSAD) inputs can be used with analog trimmers (e.g., potentiometers, analog switches, etc.)
• Two internal LSAD inputs tied directly to ground and supply can be used for supply monitoring
2.7.2. Digital Interfaces
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16-pin general-purpose I/O (GPIO) interface
Serial peripheral interface (SPI) communications port with interface speeds up to 640kbps at 1.28MHz system clock
Pulse-code modulation (PCM) interface for high-bandwidth digital audio I/O
Configurable RS-232 universal asynchronous receiver/transmitter (UART)
RS-232-based communications port for debugging and in-circuit emulation
Two-wire synchronous serial (TWSS) interface with speeds up to 100kbps at 1.28MHz system clock and up to 400kbps at higher
system clocks (slave mode support only)
2.7.3. System
• Integrated watchdog timer
• General-purpose timer
• External clock input division circuitry to support a wide range of external clock speeds
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BelaSigna 200
3.0 BelaSigna 200 Design and Layout Strategies
BelaSigna 200 is designed to allow both digital and analog processing in a single system. Due to the mixed-signal nature of this
system, the design of the printed circuit board (PCB) layout is critical to maintain the high audio fidelity of BelaSigna 200. To avoid
coupling noise into the audio signal path, keep the digital traces away from the analog traces. To avoid electrical feedback coupling,
isolate the input traces from the output traces.
3.1 Recommended Ground Design Strategy
The ground plane should be partitioned into two: the analog ground plane (AGND) and the digital ground plane (DGND). These two
planes should be connected together at a single point, known as the star point. The star point should be located at the ground terminal
of a capacitor on the output of the power regulator as illustrated in Figure 2.
Figure 2: Schematic of Ground Scheme
The DGND plane is used as the ground return for digital circuits and should be placed under digital circuits.
The AGND plane should be kept as noise-free as possible. It is used as the ground return for analog circuits and it should surround
analog components and pins. It should not be connected to or placed under any noisy circuits such as RF chips, switching supplies or
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BelaSigna 200
digital pads of BelaSigna 200 itself. Analog ground returns associated with the audio output stage should connect back to the star point
on separate individual traces.
For more information on the recommended ground design strategy, see Table 1.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
3.2 Internal Power Supplies
Power management circuitry in BelaSigna 200 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details are provided in Table 1. Non-critical signals are outlined in Table 2.
Table 1: Critical Signal
Pin Name
Description
VBAT
Power supply
VREG, VDBL
Internal regulator for analog
sections
AGND
Analog ground return
VDDC
Internal regulator for digital
sections
GNDO, GNDC
Digital ground return (pads and
core)
Routing Guideline
Place 1μF (min) decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND plane.
Place separate 1μF decoupling capacitors close to each pin. Connect
negative capacitor terminal to AGND. Keep away from digital traces and
output traces. VREG may be used to generate microphone bias. VDBL
shall not be used to supply external circuitry.
Connect to AGND plane.
Place 10μF decoupling capacitor close to pin. Connect negative terminal
of capacitor to DGND. Should be connected to VDDO pins and to
EEPROM power.
Connect to digital ground.
AIR
Input stage reference voltage
AO0, AO1
RCVR0+, RCVR0-, RCVR1+,
RCVR1AOR
Analog audio output
Output stage reference voltage
Keep as short as possible. Keep away from all digital traces and audio
outputs. Avoid routing in parallel with other traces. Connect unused inputs
to AGND.
Connect to AGND. If no analog ground plane, should share trace with
microphone grounds to star point.
Keep away from microphone inputs.
Keep away from analog traces, particularly microphone inputs.
Corresponding traces should be of approximately the same length.
Connect to star point. Share trace with power amplifier (if present).
RCVRGND
Output stage ground return
External clock input / internal
clock output
Infrared receiver input
Connect to star point.
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
If used, minimize trace length to photodiode.
AI0, AI1 / LOUT, AI2, AI3
EXT_CLK
AI_RC
Microphone inputs
Direct digital audio output
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BelaSigna 200
Table 2: Non-Critical Signal
Pin Name
Description
Routing Guideline
CAP0, CAP1
Internal charge pump - capacitor connection
DEBUG_TX, DEBUG_RX
Debug port
Place 100nF capacitor close to pins
Not critical
Connect to test points
Not critical
TWSS_SDA, TWSS_CLK
TWSS port
GPIO[14..0]
General-purpose I/O
General-purpose I/O
Determines voltage mode during boot. For 1.8V operation,
should be connected to DGND
General-purpose UART
Not critical
Pulse code modulation port
Not critical
Philips I²S compatible port
Not critical
GPIO[15]
UART_RX, UART_TX
PCM_FRAME, PCM_CLK, PCM_OUT,
PCM_IN
I2S_INA, I2S_IND, I2S_FA, I2S_FD,
I2S_OUTA, I2S_OUTD
DCLK
Programmable clock output
LSAD[5..0]
SPI_CLK, SPI_CS, SPI_SERI,
SPI_SERO
Low-speed A/D converters
Serial peripheral interface port
Connect to EEPROM
Not critical
Not critical
Not critical
If used, keep away from analog
inputs/outputs
Not critical
Not critical
3.3 Audio Inputs
The audio input traces should be as short as possible. The input impedance of each audio input pad (e.g., AI0, AI1, etc.,) is high
(approximately 500kΩ); therefore a 10nF capacitor is sufficient to decouple the DC bias 1 . Keep audio input traces strictly away from
output traces. Microphone ground terminals should be connected to the AGND plane (if present) or share a trace with the input ground
reference voltage pin (AIR) to the star point.
Analog and digital outputs MUST be kept away from microphone inputs.
3.4 Audio Outputs
The audio output traces should be as short as possible. If the direct digital output is used, the trace length of RCVRx+ and RCVRxshould be approximately the same to provide matched impedances. If the analog audio output is used, the ground return for the
external power amplifier should share a trace with the output ground reference voltage pin (AOR) to the star point.
1
The capacitor and the internal resistance form a first-order analog high pass filter whose cutoff frequency can be calculated by f3dB (Hz) = 1/(RC–2π), which results with
~30Hz for 10nF capacitor.
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BelaSigna 200
4.0 Mechanical and Environmental Information
BelaSigna 200 is available in two packages:
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The QFN package measures 8x8mm, has easy-to-probe signals and all I/O available.
The CSP package is the ultra-miniature option, measuring only 2.3x3.7mm; this package has reduced I/O and flexibility, but
still meets a wide range of application needs.
4.1 QFN Package Option
4.1.1. QFN Mechanical Information
Figure 3: QFN Mechanical Drawings
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BelaSigna 200
4.1.2. QFN Pad Out
Pad #
Pad Name
Pad Function
I/O
U/D
1
2
3
4
5
6
7
8
9
10
11
12
13
CAP0
VDBL
A|0
A|1/LOUT
A|R
A|2
A|3
VREG
AGND
AI_RC
AOR
AO1/RCVR1AO0/RCVR1+
Charge pump capacitor pin 0
Double voltage
Audio signal input to ADC0
Audio signal input to ADC0/line level output signal from preamp 0
Reference voltage for microphone
Audio signal input to ADC1
Audio signal input to ADC1
Regulated voltage for microphone bias
Analog ground
Remote control input
Reference voltage for DAC
Audio signal output from DAC1/output from direct digital drive 1Audio signal output from DAC0/output from direct digital drive 1+
N/A
O
I
I/O
N/A
I
I
O
N/A
I
N/A
O
O
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Pad #
Pad Name
Pad Function
I/O
U/D
14
15
16
17
VBAT
RCVR0RCVR0+
RCVRGND
GPIO[3]/
NCLK_DIV_RESET/I2S_FA
GPIO[2]/I2S_INA
GPIO[1]/I2S_IND
GPIO[0]/I2S_FD
VDDO
GNDO
EXT_CLK
DEBUG_RX
DEBUG_TX
Positive power supply
Output from direct digital drive 0
Output from direct digital drive 0
Receiver return current
General-purpose I/O/clock divider reset/I2S interface
analog blocks frame output
General-purpose I/O/I2S interface analog blocks input
General-purpose I/O/I2S interface analog blocks input
General-purpose I/O/I2S interface digital blocks frame
Digital pads supply input
Digital pads ground
External clock input/internal clock output
Debug port receive
Debut port transmit
I
O
O
N/A
N/A
N/A
N/A
N/A
18
19
20
21
22
23
24
25
26
I/O
U
I/O
I/O
I/O
I
N/A
I/O
I
O
U
U
U
N/A
N/A
U
U
U
Pad Function
I/O
U/D
TWSS data
TWSS clock
Core logic ground
Core logic, EEPROM and pad supply output
Serial peripheral interface serial data out
Serial peripheral interface serial data in
Serial peripheral interface chip select
Serial peripheral interface clock
General-purpose I/O
General-purpose I/O/PCM interface frame
General-purpose I/O/PCM interface output
General-purpose I/O/PCM interface input
N/A
I/O
I
N/A
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
N/A
U
U
N/A
N/A
D
U
D
N/A
U
U
U
U
Pad #
Pad Name
27
28
29
30
31
32
33
34
35
36
37
38
39
RESERVED
TWSS_SDA
TWSS_CLK
GNDC
VDDC
SPI_SERO
SPI_SERI
SPI_CS
SPI_CLK
GPIO[15]
GPIO[14]/PCM_FRAME
GPIO[13]/PCM_OUT
GPIO[12]/PCM_IN
Pad #
Pad Name
Pad Function
I/O
U/D
40
41
42
43
44
45
N/C
N/C
GPIO[11]/PCM_CLK
GNDO
VDDO
GPIO[10]/DCLK
N/A
N/A
I/O
N/A
I
I/O
N/A
N/A
U
N/A
N/A
U
46
LSAD[5]/GPIO[9]/UART_RX
I/O
U
47
LSAD[4]/GPIO[8]/UART_TX
48
49
LSAD[3]/GPIO[7]
LSAD[2]/GPIO[6]
50
LSAD[1]/GPIO[5]/I2S_OUTA
51
LSAD[0]/GPIO[4]/I2S_OUTD
52
CAP1
No connection
No connection
General-purpose I/O/PCM interface clock
Digital pads ground
Digital pads supply input
General-purpose I/O/class D receiver clock
Low-speed A/D/general-purpose I/O/general-purpose
UART receive
Low-speed A/D input/general-purpose I/O/generalpurpose UART transmit
Low-speed A/D input/general purpose I/P
Low-speed A/D input/general purpose I/P
Low-speed A/D inputs/general-purpose I/O/I2S interface
analog blocks output
Low-speed A/D inputs/general-purpose I/O/I2S interface
analog blocks output
Charge pump capacitor pin 1
I/O
U
I/O
I/O
U
U
I/O
U
I/O
U
N/A
N/A
Rev. 16 | Page 8 of 43 | www.onsemi.com
BelaSigna 200
4.1.3. QFN Environmental Characteristics
All parts supplied against this specification have been qualified as follows:
Table 3: Environmental Characteristics
Characteristics
Packaging Level
Moisture sensitivity level
Pressure cooker test (PCT)
Thermal cycling test (TCT)
Highly accelerated stress test (HAST)
High temperature stress test (HTST)
Board Level
Temperature
Drop
Bending
JEDEC Level 3
30°C / 60% RH for 192 hours
121°C / 100% RH / 2 atm for 168 hours
-65°C to 150°C for 1000 cycles
130°C / 85% RH for 100 hours
150°C for 1000 hours
-40°C to 125°C for 2500 cycles with no failures
1m height with no failures
1mm deflection / 2Hz
4.1.4. QFN Carrier Information
ON Semiconductor offers tape and reel packing for BelaSigna 200 QFN packages. The packing consists of a pocketed carrier tape, a
cover tape, and a molded anti-static polystyrene reel. The carrier and cover tape create an ESD safe environment, protecting the QFNs
from physical and electro-static damage during shipping and handling.
Reel Top View
Carrier Tape
ESD Label
Lokreel
Reel Diameter: 13 inches
Quantity Per Reel: 500 pieces
Date Codes: Max. of two date codes can
be combined into one reel
Protective
Retainer
Mfg. Packing Label
Figure 4: QFN Reel Format
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Q.A. Inspection
Passed Stamp
BelaSigna 200
All Dimensions in Millimeters
Ao = 8.3 mm
Bo = 8.3 mm
Ko = 2.0 mm
K1 = 1.0 mm
Figure 5: QFN Tape Dimensions
Notes:
1.
2.
3.
4.
5.
6..
10 sprocket hole pitch cumulative tolerance ± 0.02.
Camber not to exceed 1 mm in 100 mm.
Material: PS+C.2.
Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket.
Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Figure 6: QFN Orientation in Tape
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BelaSigna 200
4.2 CSP Package Option
4.2.1. CSP Mechanical Information
Figure 7: CSP Mechanical Drawings
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BelaSigna 200
4.2.2. CSP Pad Out
Table 4: Pad Out (Advance Information)
Pad
Index
Pad Name
B2
CAP0
Charge pump capacitor pin 0
N/A
N/A
A2
CAP1
Charge pump capacitor pin 1
N/A
N/A
A1
VDBL
Double voltage
O
N/A
C3
VREG
Regulated voltage for microphone bias
O
N/A
Pad Function
I/O
B3
A|0
Audio signal input to ADC0
B1
A|1/LOUT
Audio signal input to ADC0/line level output signal from preamp 0
U/D
I
N/A
I/O
N/A
C2
A|2
Audio signal input to ADC1
I
N/A
C1
A|3
Audio signal input to ADC1
I
N/A
B4
A|R
Reference voltage for microphone
N/A
N/A
C4
AGND
Analog ground
N/A
N/A
D1
AOR
Reference voltage for DAC
N/A
N/A
E1
AO1/RCVR1-
Audio signal output from DAC1/output from direct digital drive 1-
O
N/A
D2
AO0/RCVR1+
Audio signal output from DAC0/output from direct digital drive 1+
O
N/A
D3
RCVR0-
Output from direct digital drive 0
O
N/A
E3
RCVR0+
Output from direct digital drive 0
O
N/A
D4
RCVRGND
Receiver return current
N/A
N/A
E2
VBAT
Positive power supply
I
N/A
E5
VDD
Core logic, EEPROM and pad supply
I
N/A
A6
GNDO
Digital pads ground
N/A
N/A
E6
GNDC
Core logic and pads ground
N/A
N/A
I/O
U
I
U
D6
EXT_CLK
External clock input/internal clock output
E7
DEBUG_RX
Debug port receive
D7
DEBUG_TX
Debut port transmit
O
U
E8
TWSS_SDA
TWSS data
I/O
U
D8
TWSS_CLK
TWSS clock
I
U
C8
SPI_SERO
Serial peripheral interface serial data out
I/O
D
C7
SPI_SERI
Serial peripheral interface serial data in
B8
SPI_CS
Serial peripheral interface chip select
I
U
I/O
D
N/A
C6
SPI_CLK
Serial peripheral interface clock
I/O
A8
GPIO[14]/PCM_FRAME
General-purpose I/O/PCM interface frame
I/O
U
B7
GPIO[13]/PCM_OUT
General-purpose I/O/PCM interface output
I/O
U
A7
GPIO[12]/PCM_IN
General-purpose I/O/PCM interface input
I/O
U
B6
GPIO[11]/PCM_CLK
General-purpose I/O/PCM interface clock
I/O
U
A5
GPIO[10]/DCLK
General-purpose I/O/class D receiver clock
I/O
U
B5
LSAD[5]/GPIO[9]/UART_RX
Low-speed A/D/general-purpose I/O/general-purpose UART receive
I/O
U
A4
LSAD[4]/GPIO[8]/UART_TX
Low-speed A/D input/general-purpose I/O/general-purpose UART
transmit
I/O
U
C5
LSAD[3]/GPIO[7]
Low-speed A/D input/general purpose I/P
I/O
U
A3
LSAD[1]/GPIO[5]/I2S_OUT
A
Low-speed A/D inputs/general-purpose I/O/I2S interface analog
blocks output
I/O
U
D5
LSAD[0]/GPIO[4]/I2S_OUT
D
Low-speed A/D inputs/general-purpose I/O/I2S interface analog
blocks output
I/O
U
E4
GPIO[3]/
NCLK_DIV_RESET/I2S_FA
General-purpose I/O/clock divider reset/I2S interface analog blocks
frame output
I/O
U
Rev. 16 | Page 12 of 43 | www.onsemi.com
BelaSigna 200
4.2.3. CSP Environmental Characteristics
All parts supplied against this specification have been qualified as follows:
Table 5:
Packaging Level
Moisture sensitivity level (MSL)
Pressure cooker test (PCT)
Thermal cycling test (TCT)
Highly accelerated stress test (HAST)
High temperature stress test (HTST)
Board Level
Temperature
Drop
JEDEC Level 3
30°C / 60% RH for 192 hours
121°C / 100% RH / 2 atm for 168 hours
-65°C to 150°C for 1000 cycles
130°C / 85% RH for 100 hours
150°C for 1000 hours
-40°C to 125°C for 1000 cycles with no failures
(for board thickness <40mils and underfilled CSP)
1m height with no failures
4.2.4. CSP Carrier Information
The devices will be provided in standard 7” Tape & Reel carrier with 5,000 parts per reel.
Note: all dimensions in millimeters
Figure 8: CSP Tape Dimensions
4.2.5. CSP Design Considerations
In order to achieve the highest level of miniaturization, the CSP package is constrained in ways that will factor into design decisions.
The CSP will only operate in HV mode, and therefore requires a 1.8V operating voltage. The number of pins is reduced to 40
(compared to 49 active pins on the QFN). This reduction eliminates access to GPIOs (0,1,2,6,15), LSAD 2, the I2S interface, and the IR
remote receiver.
For PCB manufacture with BelaSigna 200 CSP, ON Semiconductor recommends Solder-on-Pad (SoP) surface finish. With SoP, the
solder mask opening should be solder mask-defined and copper pad geometry will be dictated by the PCB vendor’s design
requirements.
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BelaSigna 200
Alternative surface finishes are ENiG and OSP; volume of screened solder paste (#5) should be less than 0.0008mm^3. If no prescreening of solder paste is used, then following conditions must be met:
(i) the solder mask opening should be >0.3mm in diameter,
(ii) the copper pad will have 0.25mm diameter, and
(iii) soldermask thickness should be less than 1mil thick above the copper surface.
ON Semiconductor can provide BelaSigna 200 CSP landpattern CAD files to assist your PCB design upon request.
Rev. 16 | Page 14 of 43 | www.onsemi.com
BelaSigna 200
5.0 Development Tools
5.1 Evaluation and Development Kit (EDK)
BelaSigna 200 is supported by a set of development tools included in the evaluation and development kit (EDK).
The EDK is intended for use by DSP software developers and hardware systems integrators. It consists of the following components:
• Hardware
• Software
•
BelaSigna 200 evaluation and development board (contains BelaSigna 200 device)
•
•
•
•
•
•
•
•
•
Complete assembly tool chain (assembler, linker, librarian, etc.)
Low-level hardware-specific libraries
Basic algorithm toolkit (BAT)
Basic operating system libraries (BOS)
WOLA windows and microcode
Real-time debugger
EEPROM file system manager
UltraEdit IDE
WOLA toolbox for Matlab for rapid application development and prototyping
BAT and BOS provide all the common processing routines in an easy-to-call macro structure. This streamlines the assembly level
coding by encapsulating redundant work, while maintaining the true efficiency of hardware-level coding.
For advanced DSP developers or application developers, ON Semiconductor provides an application development extension to the
EDK, which contains the following:
•
•
•
•
Python language installer (version 2.2)
The wxPython GUI toolkit
Embedding toolkit (used to build standalone Python applications)
ON Semiconductor extension
•
Python interface (pyLLCOM) to ON Semiconductor’s low-level communications library (LLCOM)
•
File I/O library (supports standard ON Semiconductor file formats)
•
EEPROM access library
•
DSH (ON Semiconductor Python Shell – standard command-line shell with customizations for BelaSigna 200)
5.2 BelaSigna 200 Rapid Prototyping Module
The rapid prototyping module (RPM) is fast and easy for designers to integrate with existing and future products that are not yet DSPenabled. It also allows for the quick implementation of field trials and rapid prototyping to evaluate the benefits of BelaSigna 200. The
RPM features BelaSigna 200 along with a 256-Kbit EEPROM for storing a variety of custom algorithms. On-board power regulation
circuitry allows the RPM to run off a wide variety of power supplies. A fast oscillator (included on the RPM) running at 24.576MHz
provides a choice of many sampling frequencies and can be enabled for when heavy-duty signal processing is required.
5.3 BelaSigna 200 Demonstrator
The BelaSigna 200 demonstrator lets device manufacturers quickly and easily assess the speech- and audio-centric benefits delivered
by BelaSigna 200 in a full-featured, self-contained portable unit. The demonstrator is housed in a durable, portable, lightweight package
complete with belt clip to facilitate demonstrations in the field. This tool can be easily utilized in real world scenarios to experience the
benefits of noise reduction, signal enhancement and a variety of other algorithms. The demonstrator can be connected to a wired
headset and function like a dongle to communicate with a Bluetooth mobile phone.
Contact your account manager for more information.
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BelaSigna 200
6.0 Architecture Overview
6.1 RCore DSP
The RCore is a 16-bit fixed-point, dual-Harvard-architecture DSP. It includes efficient normalize and de-normalize instructions, plus
support for double-precision operations to provide the additional dynamic range needed for many applications. All memory locations in
the system are accessible by the RCore using several addressing modes including indirect and circular modes. The RCore generally
assumes master functionality of the system.
6.1.1. RCore DSP Architecture
Internal Router
DCU
Y
X
D_AUX_REG0
D_AUX_REG4
EXT3
D_INT_STATUS
D_INT_EBL
D_SYS_CTRL
MU
PH
PL
LC 0
LC 1
RE P
X_Bus
XRAM
X_AGU
R0
R1
R2
R3
CTRL
PCU
ALU
EXP
ST
PCFG0
PCFG1
PCFG2
Y_Bus
YRAM
PRAM
AE
AH
AL
Y_AGU
Barrel
Shifter
Limiter
P_Bus
IMM/SIMM
PC
R4
R5
R6
R7
PCFG4
PCFG5
PCFG6
Data registers
Internal Router
Figure 9: RCore Programming Model
The RCore is a single-cycle pipelined multiply-accumulate (MAC) architecture that feeds into a 40-bit accumulator complete with barrel
shifter for fast normalization and de-normalization operations. Program execution is controlled by a sequencer that employs a threestage pipeline (FETCH, DECODE, EXECUTE). Furthermore, the RCore incorporates pointer configuration registers for low cycle-count
address generation when accessing the three memories: program memory (PRAM), X data memory (XRAM) and Y data memory
(YRAM).
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BelaSigna 200
6.1.2. Instruction Set
The RCore instruction set can be divided into the following three classes:
1. Arithmetic and Logic Instructions
The RCore uses two's complement fractional as a native data format. Thus, the range of valid numbers is [-1; 1), which is represented
by 0x8000 to 0x7FFF. Other formats can be utilized by applying appropriate shifts to the data.
The multiplier takes 16-bit values and performs a multiplication every time an operand is loaded into either the X or Y register. A
number of instructions that allow loading of X and Y simultaneously and addition of the new product to the previous product (a MAC
operation), are available. Single-cycle MAC with data pointer update and fetch is supported.
The arithmetic logic unit (ALU) receives its input from either the accumpulator (AE|AH|AL) or the product register (PH|PL). Although the
RCORE is a 16-bit system, 32-bit additions or subtractions are also supported. Bit manipulation is also available on the accumulator as
well as operations to perform arithmetic or logic shifts, toggling of specific bits, limiting, and other functions.
2. Data Movement Instructions
Data movement instructions transfer data between RAM, control registers and the RCore’s internal registers (accumulator, PH, PL, etc).
Two address generators are available to simultaneously generate two addresses in a single cycle. The address pointers R0..2 and
R4..6 can be configured to support increment, decrement, add-by-offset, and two types of modulo-N circular buffer operations. Singlecycle access to low X memory or low Y memory as well as two-cycle instructions for immediate access to any address are also
available.
3. Program Flow Control Instructions
The RCore supports repeating of both single-word instructions and larger segments of code using dedicated repeat instructions or
hardware loop counters. Furthermore, instructions to manipulate the program counter (PC) register such as calls to subroutines,
conditional branches and unconditional branches are also provided.
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BelaSigna 200
7.0 Instruction Set
Table 6: Instruction Set
Instruction
Description
Instruction
Description
ABS A [,Cond] [,DW]
Calculate absolute value of A on condition
DCMP
Compare PH | PL to A
ADD A, Reg [,C]
Add register to A
DEC A [,Cond] [,DW]
Decrement A on condition
ADD A, (Rij) [,C]
Add memory to A
DEC Reg [Cond]
Decrement register on condition
ADD A, DRAM [,B]
Add (DRAM) to A
DEC (Rij) [,Cond]
Decrement memory on condition
ADD A, (Rij)p [,C]
Add program memory to A
DSUB [Cond] [,P]
Subtract PH | PL from A,
update PH | PL on condition
ADD A, Rc [,C]
Add Rc register to A
EOR A, Reg
Exclusive-OR register with AH to AH
ADDI A, IMM [,C]
Add IMM to A
EOR A, (Rij)
Exclusive-OR memory with AH to AH
ADSI A, SIMM
Add signed SIMM to A
EOR A, DRAM [,B]
Exclusive-OR (DRAM) with AH to AH
AND A, Reg
AND register with AH to AH
EOR A, (Rij)p
AND A, (Rij)
AND memory with AH to AH
EOR A, Rc
AND A, DRAM [,B]
AND (DRAM) with AH to AH
EORI A, IMM
Exclusive-OR IMM with AH to AH
AND A, (Rij)p
AND program memory with AH to AH
EOSI A, SIMM
Exclusive-OR unsigned SIMM with AH
to AH
AND A, Rc
AND Rc register with AH to AH
INC A [,Cond] [,DW]
Increment A on condition
ANDI A, IMM
AND IMM with AH to AH
INC Reg [,Cond]
Increment register on condition
ANSI A, SIMM
AND unsigned SIMM with AH to AH
INC (Rij) [,Cond]
Increment memory on condition
BRA PRAM [,Cond]
Branch to new address on condition
LD Rc, Rc
Load Rc register with Rc register
BREAK
Stop the DSP for debugging purposes
LD Reg, Reg
Load register with register
CALL PRAM [,Cond] [,B]
Push PC and branch to new address
on condition
LD Reg, (Rij)
Load register with memory
CLB A
Calculate the leading bits on A
LD (Rij), Reg
Load memory with register
CLR A [,DW]
Clear accumulator
LD A, DRAM [,B]
Load A with (DRAM)
CLR Reg
Clear register
LD DRAM, A [,B]
Load (DRAM) with A
CMP A, Reg [,C]
Compare register to A
LD Rc, (Rij)
Load Rc register with memory
CMP A, (Rij) [,C]
Compare memory to A
LD (Rij), Rc
Load memory with Rc register
CMP A, DRAM [,B]
Compare (DRAM) to A
LD Reg, (Rij)p
Load register with program memory
CMP A, (Rij)p [,C]
Compare program memory to A
LD (Rij)p, Reg
Load program memory with register
Exclusive-OR program memory with
AH to AH
Exclusive-OR Rc register with AH to
AH
CMP A, Rc [,C]
Compare Rc register to A
LD Reg, (Reg)p
Load register with program memory via
register
CMPI A, IMM [,C]
Compare IMM to A
LD Reg, Rc
Load register with Rc register
CMSI A, SIMM
Compare signed SIMM to A
LD Rc, Reg
Load Rc register with register
CMPL A [,Cond] [,DW]
Calculate logical inverse of A on condition
LDI Reg, IMM
Load register with IMM
DADD [Cond] [,P]
Add PH | PL to A, update PH | PL
on condition
LDI Rc, IMM
Load Rc register with IMM
DBNZ0/1 PRAM
Branch to new address if LC0/1 <> 0
LDI (Rij), IMM
Load memory with IMM
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BelaSigna 200
Table 7: Instruction Set Continued
Instruction
Description
Instruction
Description
LDLC0/1 SIMM
Load loop counter with 8-bit unsigned
SIMM
PUSH IMM [,B]
Push IMM on stack
LDSI A, SIMM
Load A with signed SIMM
REP n
Repeat next instruction n+1 times
(9-bit unsigned)
LDSI Rij, SIMM
Load pointer register with unsigned
SIMM
REP Reg
Repeat next instruction Reg+1 times
MLD (Rj), (Ri) [,SQ]
Multiplier load and clear A
REP (Rij)
Repeat next instruction (Rij)+1 times
MLD Reg, (Ri) [,SQ]
Multiplier load and clear A
RES Reg, Bit
Clear bit in register
MODR Rj, Ri
Pointer register modification
RES (Rij), Bit
Clear bit in memory
MPYA (Rj), (Ri) [,SQ]
Multiplier load and accumulate
RET [B]
Return from subroutine
Multiplier load and accumulate
RND A
Round A with AL
SET Reg, Bit
Set bit in register
SET (Rij), Bit
Set bit in memory
MPYA Reg, (Ri) [,SQ]
MPYS (Rj), (Ri) [,SQ]
MPYS Reg, (Ri) [,SQ]
Multiplier load and accumulate
negative
Multiplier load and accumulate
negative
MSET (Rj), (Ri) [,SQ]
Multiplier load
SET_IE
Set interrupt enable flag
MSET Reg, (Ri) [,SQ]
Multiplier load
SHFT n
Shift A by +/- n bits (6-bit signed)
SHFT A [,Cond] [,INV]
Shift A by EXP bits on condition
SLEEP [IE]
Sleep
MUL [Cond] [,A] [,P]
NEG A [,Cond] [,DW]
Update A and/or PH | PL with X*Y on
condition
Calculate negative value of A on
condition
NOP
No operation
SUB A, Reg [,C]
Subtract register from A
OR A, Reg
OR register with AH to AH
SUB A, (Rij) [,C]
Subtract memory from A
OR A, (Rij)
OR memory with AH to AH
SUB A, DRAM [,B]
Subtract (DRAM) from A
OR A, DRAM [,B]
OR (DRAM) with AH to AH
SUB A, (Rij)p [,C]
Subtract program memory from A
OR A, (Rij)p
OR program memory with AH to AH
SUB A, Rc [,C]
Subtract Rc register from A
OR A, Rc
OR Rc register with AH to AH
SUBI A, IMM [,C]
Subtract IMM from A
ORI A, IMM
OR IMM with AH to AH
SUSI A, SIMM
Subtract signed SIMM from A
ORSI A, SIMM
OR unsigned SIMM with AH to AH
SWAP A [,Cond]
Swap AH, AL on condition
POP Reg [,B]
Pop register from stack
TGL Reg, Bit
Toggle bit in register
POP Rc [,B]
Pop Rc register from stack
TGL (Rij), Bit
Toggle bit in memory
PUSH Reg [,B]
Push register on stack
TST Reg, Bit
Test bit in register
PUSH Rc [,B]
Push Rc register on stack
TST (Rij), Bit
Test bit in memory
Table 8: Notation
Symbol
Meaning
Symbol
Meaning
A
B
Accumulator update
Memory bank selection (X or Y)
INV
Inverse shift
C
Carry bit
P
PRAM
PH | PL update
Program memory address (16 bits)
Cond
Condition in status register
Rc
Rc register (R0..7, PCFG0..2, PCFG4..6, LC0/1)
DRAM
Low data (X or Y) memory address (8 bits)
Reg
Data register (AL, AH, X, Y, ST, PC, PL, PH, EXT0, EXP, AE,
EXT3..EXT7)
DW
Double word
Ri / Rj / Rij
Pointer to X / Y / either data memory
IE
Interrupt enable flag
SIMM
Short immediate data (10 bits)
IMM
Immediate data (16 bits)
SQ
Square
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BelaSigna 200
7.1 Weighted Overlap-Add (WOLA) Filterbank Coprocessor
The WOLA coprocessor performs low-delay, high-fidelity filterbank processing to provide efficient time-frequency processing. The
coprocessor stores intermediate data values, program code and window coefficients in its own memory space. Audio data are
accessed directly from the input and output FIFOs where they are automatically managed by the IOP.
The WOLA coprocessor can be configured to handle different sizes and types of transforms, such as mono, simple stereo or full stereo
configurations. The number of bands, the stacking mode (even or odd), the oversampling factor, and the shape of the analysis and
synthesis windows used are all configurable. The selected set of parameters affects both the frequency resolution, the group delay
through the WOLA coprocessor and the number of cycles needed for complete execution.
The WOLA coprocessor can generate both real and complex data. Either real or complex gains can be applied. The RCore always has
access to these values through shared memories. All parameters are configurable with microcode, which is used to control the WOLA
during execution.
The RCore initiates all WOLA functions (analysis, gain applications, synthesis) through dedicated control registers. A dedicated
interrupt is used to signal completion of a WOLA function.
Many standard WOLA microcode configurations are delivered with the EDK. These configurations have been specially designed for low
group delay and high fidelity.
7.2 Input Output Processor (IOP)
The IOP is an audio-optimized configurable DMA unit for audio data samples. It manages the collection of data from the A/D converters
to the input FIFO and feeds digital data to the audio output stage from the output FIFO. The IOP can be configured to access data in
the FIFOs in four different ways:
• Mono mode: Input samples are stored sequentially in the input FIFO. Output samples are stored sequentially in the output FIFO.
• Simple stereo mode: Input samples from the two channels are stored interleaved in the input FIFO. Output samples for the single
output channel are stored in the lower part of the output FIFO.
• Digital mixed mode: Input samples from the two channels are stored in each half of the input FIFO. Output samples for the single
output channel are stored in the lower half of the output FIFO.
• Full stereo mode: Input samples from the two channels are stored interleaved in the input FIFO. Output samples for the two output
channels are stored interleaved in the output FIFO. (Note: A one-in, two-out configuration can be achieved in this mode by leaving
the second input unused).
Figure 10: Four Audio Modes
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BelaSigna 200
The IOP places and retrieves FIFO data in memories shared with the RCore. Each FIFO (input and output) has two memory interfaces.
The first corresponds with the normal FIFO. Here the address of the most recent input block changes as new blocks arrive. The second
corresponds with the Smart FIFO. In this scheme the address of the most recent input block is fixed. The smart FIFO interface is
especially useful for time-domain filters.
In the case where the WOLA and the IOP no longer work together as a result of a low battery condition, an IOP end-of-battery-life automute feature is available.
7.3 General-Purpose Timer
The general-purpose timer is a 12-bit countdown timer with a 3-bit prescaler that interrupts the RCore when it reaches zero. It can
operate in two modes, single-shot or continuous. In single-shot mode the timer counts down only once and then generates an interrupt.
It will then have to be restarted from the RCore. In continuous mode the timer restarts with full timeout setting every time it hits zero and
interrupts are generated continuously. This unit is often useful in scheduling tasks that are not part of the sample-based signal
processing scheme, such as checking a battery voltage, or reading the value of a volume control.
7.4 Watchdog Timer
The watchdog timer is a configurable hardware timer that operates from the system clock and is used to prevent unexpected or
unstable system states. It is always active and must be periodically acknowledged as a check that an application is still running. Once
the watchdog times out, it generates an interrupt. If left to time out a second consecutive time without acknowledgement, a system reset
will occur.
7.5 RAM and ROM
There are 20 Kwords of on-chip program and data RAM on BelaSigna 200. These are divided into three entities: a 12-Kword program
memory, and two 4-Kword data memories ("X" and "Y" as are common in a dual-Harvard architecture).
There are also three RAM banks that are shared between the RCore and WOLA coprocessor. These memory banks contain the input
and output FIFOs, gain tables for the WOLA coprocessor, temporary memory for WOLA calculations, WOLA coprocessor results, and
the WOLA coprocessor microcode.
There is a 128-word lookup table (LUT) ROM that contains log2(x), 2x, 1/x and sqrt(x) values, and a 1-Kword ProgramROM that is used
during booting and configuration of the system.
Complete memory maps for BelaSigna 200 are shown in Figure 11.
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BelaSigna 200
Figure 11: Memory Maps
7.6 Interrupts
The RCore DSP has a single interrupt channel that serves eleven interrupt sources in a prioritized manner. The interrupt controller also
handles interrupt acknowledge flags. Every interrupt source has its own interrupt vector. Furthermore, the priority scheme of the
interrupt sources can be modified. Refer to Table 9 for a description of all the interrupts.
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BelaSigna 200
Table 9: Interrupts
Interrupt
Description
WOLA_DONE
WOLA function done
IO_BLOCK_FULL
IOP interrupt
PCM
PCM interface interrupt
UART_RX
General-purpose UART receive interrupt
UART_TX
General-purpose UART transmit interrupt
GP_TIMER
General-purpose timer interrupt
WATCHDOG_TIMER
Watchdog timer interrupt
SPI_INTERFACE
SPI interface interrupt
TWSS_INTERFACE
TWSS interface interrupt
EXT3_RX
EXT3 register receive interrupt
EXT3_TX
EXT3 register transmit interrupt
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BelaSigna 200
8.0 Description of Analog Blocks
8.1 Input Stage
The analog audio input stage is comprised of two individual channels. For each channel, one of two possible inputs is routed to the
input of the programmable preamplifier that can be configured for bypass or gain values of 12 to 30dB (3-dB steps).
The analog signal is filtered to remove frequencies above 10kHz before it is passed into the high-fidelity 16-bit oversampling ΣΔ A/D
converter. Subsequently, any necessary sample rate decimation is performed to downsample the signal to the desired sampling rate.
During decimation the level of the signal can be adjusted digitally for optimal gain matching between the two input channels. Any
undesired DC component can be removed by a configurable DC-removal filter that is part of the decimation circuitry. The DC removal
filter can be bypassed or configured for cut-off frequencies at 5, 10 and 20Hz.
A built-in feature allows a sampling delay to be configured between channel zero and channel one. This is useful in beam-forming
applications.
For power consumption savings either of the input channels can be disabled via software.
Figure 12: Input Stage
8.2 Output Stage
The analog audio output stage is composed of two individual channels. The first part of the output stage interpolates the signal for
highly oversampled D/A conversion and automatically configures itself for the desired oversampling rate. Here, the signal is routed to
both the ΣΔ D/A converter and the direct digital outputs. The D/A converter translates the signal into a high-fidelity analog signal and
passes it into a reconstruction filter to smooth out the effects of sampling. The reconstruction filter has a fixed cut-off frequency at
10kHz.
From the reconstruction filter, the signal passes through the programmable output attenuator, which can adjust the signal for various
line-level outputs or mute the signal altogether. The attenuator can be bypassed or configured to a value in the interval -12 to -30dB (3dB steps).
The direct digital output provides a bridge driven by a pulse-density modulated output that can be used to directly drive an output
transducer without the need for an external power amplifier.
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BelaSigna 200
Two analog outputs designed to drive external amplifiers are also available.
Figure 13: Output Stage
8.3 Clock-Generation Circuitry
BelaSigna 200 operates with two main clock domains: a domain running on the system clock (SYS_CLK) and a domain running on the
main clock (MCLK). SYS_CLK can either be internally generated or externally delivered. It is used to drive all on-chip processors such
as the RCore, the WOLA coprocessor and the IOP. MCLK is generated by division of SYS_CLK and is used to drive all A/D converters,
D/A converters and external interfaces (except SPI, PCM, I2S, and GPIO interfaces). The division factor used to create the desired
MCLK from SYS_CLK is configurable to support external clocks with a wide range of frequencies.
The sampling frequency of all A/D converters and D/A converters also depends on MCLK. When MCLK is 1.28MHz, sampling
frequencies in the interval 10.7kHz to 20kHz can be selected. Sampling frequencies up to 60kHz can be obtained with other MCLK
frequencies.
8.4 Battery Monitor
A programmable on-chip battery monitor is available for power management. The battery monitor works by incrementing a counter
value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an
application-specific power-management algorithm running on the RCore. The RCore can initiate any desired actions in case the battery
hits a predetermined value.
8.5 Multi-Chip Sample Clock Synchronization
BelaSigna 200 allows MCLK synchronization between two or more BelaSigna 200 chips connected in a multi-chip configuration.
Samples on multiple chips occur at the same instant in time. This is useful in applications using microphone arrays where synchronous
sampling is required. The sample clock synchronization is enabled using a control bit and a GPIO assignment that brings all MCLKs
across chips to zero phase at the same instant in time.
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BelaSigna 200
9.0 External Interfaces
9.1 External Digital Interfaces
9.1.1. Pulse-Code Modulation Interface (PCM I/F)
The PCM interface is a bi-directional, four-wire synchronous serial interface suitable for high-speed digital audio transfer. This
externally-clocked interface is capable of sending data serially at rates up to the clock speed of the RCore, providing the necessary
bandwidth for digital audio. This interface can also be used for a number of other functions, including multi-processing BelaSigna 200
chips. The interface is configurable for glueless connections to four-wire PCM interfaces as well as other BelaSigna 200 chips in a
BelaSigna 200 multi-chip configuration. Both master and slave modes are supported. The interface is configured via a memory-mapped
configuration register and interacts with the RCore through memory-mapped control registers and interrupts. Refer to Section 12.1 for
timing specifications.
9.1.2. General-Purpose Input/Output (GPIO)
Up to 16 GPIO pins are available to be configured as inputs or as outputs. All GPIO pins are pulled up internally. Data are read or
written via a memory-mapped control register. GPIO pins can be used to interface to digital switches, other devices, etc. The direction
of each bit is programmable via a direction register. Refer to Section 12.2 for timing specifications.
9.1.3. Serial Peripheral Interface (SPI) Port
The SPI port allows BelaSigna 200 to communicate synchronously with other devices such as external memory or EEPROM. This SPI
interface conforms to the standard SPI bus protocol supporting modes zero and two as a master, and transfer speeds up to half the
system clock frequency. The interface is configured via a memory-mapped configuration register and interacts with the RCore through
memory-mapped control registers and interrupts. Refer to Section 12.3 for timing specifications.
9.1.4. RS-232 Universal Asynchronous Receiver/Transmitter (UART)
The general-purpose UART is a low-voltage RS-232-compatible interface. All data are transmitted and received with eight data bits, no
parity and one stop bit (8N1). A range of standard data rates, up to a maximum of 115.2kbps, is supported. The interface is configured
via a memory-mapped configuration register and interacts with the RCore through memory-mapped control registers and interrupts.
9.1.5. Debug Port
The debug port is also a low-voltage RS-232-based UART, and it interfaces directly to the program controller. This interface differs from
the general-purpose UART in its access path to the RCore. It is used primarily by the evaluation and development tools to interface to,
program and debug BelaSigna 200 applications. Data rates up to 115.2kbps are supported. The protocol uses eight data bits, no parity
and one stop bit (8N1).
9.1.6. Two-Wire Synchronous Serial (TWSS) Interface
This industry standard two-wire high-speed synchronous serial interface allows communication to a variety of other integrated circuits
and memories. On BelaSigna 200, this interface operates in slave mode only. Data rates up to 400kbps are supported for MCLK
frequencies higher than 1.28MHz; for lower MCLK frequencies, the maximum rate is 100kbps. The interface is configured via memory
mapped configuration registers and interacts with the RCore through memory-mapped control registers and interrupts. The TWSS
2
interface is compatible with the Philips' I C protocol.
9.1.7. I2S Interface
This industry standard digital audio interface uses a three-wire serial protocol to transmit and receive audio between BelaSigna 200 and
other systems. The interface operates at the system clock frequency and BelaSigna 200 always assumes master functionality.
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BelaSigna 200
9.2 External Analog Interfaces
9.2.1. Low-Speed A/D Converters (LSAD)
Six LSAD inputs are available on BelaSigna 200. Combined with two internal LSAD inputs (supply and ground) this gives a total of eight
multiplexed inputs to the LSAD converter. The multiplexed inputs are sampled sequentially at 1.6kHz per channel. The native data
format for the LSAD is 10-bit two's complement. However, a total of eight operation modes are provided that allow a configurable input
dynamic range in cases where certain minimum and maximum values for the converted inputs are desired; such as in the case of a
volume control where only input values up to a certain magnitude are allowed.
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BelaSigna 200
10.0 Boot Sequence
BelaSigna 200 boots in a two-stage boot sequence. The ProgramROM begins loading the bootloader from an external SPI EEPROM
200ms after power is applied to the chip. In this process the ProgramROM checks the EEPROM file structure to ensure validity. If the
file structure is validated, the bootloader is written to PRAM. In case of an error while reading the external EEPROM, all outputs are
muted. The system will then reset due to a watchdog timeout.
Once the bootloader is loaded into PRAM the program counter is set to point to the beginning of the bootloader code. Subsequently,
the signal-processing application that is stored in the EEPROM is downloaded to PRAM by the bootloader. The boot process generally
takes less than one second. ON Semiconductor provides a standard full-featured bootloader.
An alternative to bootloading is often used in development - program code can be loaded through the debug port after powering
BelaSigna 200. In this case, an SPI EEPROM may or may not be attached, and the debug port takes over control of the system. Some
products use this technique when an EEPROM is not suitable to the application.
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BelaSigna 200
11.0 Electrical Characteristics
11.1 Absolute Maximum Ratings
Table 10: Absolute Maximum Ratings
Parameter
Min.
Supply voltage
Operating temperature range
2
Max.
Unit
2.0
V
-40
85
°C
Storage temperature range
-55
125
°C
Voltage at any input pin
-0.3
2.1
V
Caution: Class 2 ESD sensitivity, JESD22-A114-B (2000V)
11.2 Electrical Characteristics
Conditions: Temperature = 25°C, fSYS_CLK = 1.28MHz (internal), fMCLK = 1.28MHz, fSAMP = 16kHz, Vbat = 1.8V
Table 11: Electrical Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
1.03
1.25
1.8
V
Overall (1µF VBAT external capacitor)
Supply voltage
Vbat
Current consumption 4
Ibat
Vbat = 1.8V
VREG
unloaded
0.9
1.0
@ 1kHz
35
50
μA
650
VREG (1µF external capacitor)
Regulated output
PSRR
Load current
Ireg
1.1
V
dB
2
mA
Load regulation
12
18
mV/mA
Line regulation
2
5
mV/V
2.0
2.2
V
VDBL (1µF external capacitor)
Regulated output
VDBL
PSRR
Load current
1.8
@ 1kHz
45
Ireg
Charge pump cap
= 100nF
Load regulation
Line regulation
dB
2
mA
130
200
mV/mA
5
8
mV/V
VDDC (1µF external capacitor)
HV output
2
3
4
HV
HV mode
Vbat
Audio performance parameters may degrade outside the range of 0 to 70 degrees C. Internal oscillator speed will vary with temperature
Device will operate down to 0.9V but with degraded system specifications
DSP core active; single channel; direct digital output enabled and connected to 100kΩ resistance
Rev. 16 | Page 29 of 43 | www.onsemi.com
V
BelaSigna 200
11.3 Analog Characteristics
Conditions: Temperature = 25°C, fSYS_CLK = 1.28MHz (internal), fMCLK = 1.28MHz, fSAMP = 16kHz, Vbat = 1.8V
Table 12: Analog Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
1
Vp
715
kΩ
Input Stage
Input voltage
Vin
Input impedance 5
Rin
Input referred noise
IRN
Input dynamic range
Input THD+N
Preamplifier gain tolerance
(0, 12, 15, 18, 21, 24, 27, 30dB)
AI0, AI1, AI2, AI3 inputs
0dB preamp gain
Preamplifier gain 12, 15, 18, 21,
24, 27, 30dB
Unweighted, 20Hz to 8kHz BW,
30dB preamp gain
Unweighted, 20Hz to 8kHz BW,
0dB preamp gain
Unweighted, 20Hz to 8kHz BW,
0dB preamp gain,
input at 1 kHz
50% re. FS input at 1kHz
-1
385
550
3
μVrms
85
dB
-60
dB
-1.5
1.5
dB
-1
1
Vp
Output Stage
Line out output level
Vlo
Line out output impedance
Rlo
Output impedance 6
Rao
Output dynamic range
Output THD+N
Output attenuator tolerance
(0,12,15,18,21,24,27,30dB)
AI1
AI1
AO0. Attenuator = 12, 15, 18, 21,
24, 27, 30dB
Unweighted, 100Hz to 22kHz BW,
0dB output attenuation
Unweighted, 100Hz to 22kHz BW,
0dB output attenuation,
input at 1kHz
50% re. FS input at 1kHz
5
8.9
12.8
kΩ
16.6
kΩ
75
dB
-60
dB
-2
2
dB
-0.3
2.1
V
Low-Speed A/D
Input voltage
Sampling frequency
Channel frequency
Peak input voltage, HV mode
All channels sequentially
MCLK = 1.28MHz
8 channels
12.8
kHz
1.6
kHz
Anti-Aliasing Filters (Input and Output)
Cut-off frequencies
7
Passband flatness
-1
Stopband attenuation
5
6
10
80
Depends slightly on the preamp gain
Depends strongly on the attenuator
Rev. 16 | Page 30 of 43 | www.onsemi.com
13
kHz
1
dB
dB
BelaSigna 200
11.4 Digital Characteristics
Conditions: Temperature = 25°C, fSYS_CLK = 1.28MHz (internal), fMCLK = 1.28MHz, fSAMP = 16kHz, Vbat = 1.8V
Table 13: Digital Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
25
mA
20
Ω
Output Stage
Direct digital output load current
Ido
Direct digital output resistance
Rdo
10
Direct digital output 0 dynamic
range
Unweighted, 100Hz to 22kHz BW
Unweighted, 100Hz to 10kHz BW
input at 1kHz
Unweighted, 100Hz to 22kHz BW
Direct digital output 0 THD+N
Direct digital output 1 dynamic
range
Unweighted, 100Hz to 10kHz BW
input at 1kHz
Direct digital output 1 THD+N
77
dB
-63
dB
75
dB
-62
dB
1.28
MHz
Internal Oscillator Characteristics
Clock frequency (internal)
fSYS_CLK
Oscillator jitter
Oscillator start-up voltage
0.55
Time required for frequency change
of ±20%
Oscillator settling time
0.4
1.0
ns
0.7
0.85
V
1
ms
Other
Clock frequency (external)
fSYS_CLK
High-level input voltage
VIH 7
Low-level input voltage
VIL
High-level output voltage
Rout = 50ohm
Low-level output voltage
Rout = 50ohm
Input capacitance
(digital I/O pads)
Output capacitance
(digital I/O pads)
7
HV mode
1.45
7
VOH
7
VOL
Isource = 1mA
1.45
Isink = 1mA
33
MHz
1.8
2.0
V
0
0.35
V
1.8
0.05
CIN
COUT
Maximum load
V
0.1
V
5
pF
100
pF
Pull-up resistors
Rup
215
430
645
KΩ
Pull-down resistors
Rdown
215
430
645
kΩ
Digital low (0) represented below 20% of Vbat. Digital high (1) represented above 80% of Vbat.
Rev. 16 | Page 31 of 43 | www.onsemi.com
BelaSigna 200
12.0 Timing Diagrams
12.1 PCM Interface Timing Diagrams
12.1.1. 16-bit
Figure 14: LSB Advanced Short
Figure 15: LSB Advanced Wide
Rev. 16 | Page 32 of 43 | www.onsemi.com
BelaSigna 200
Figure 16: LSB Del Short
Figure 17: LSB Del Wide
Rev. 16 | Page 33 of 43 | www.onsemi.com
BelaSigna 200
Figure 18: MSB Advanced Short
Figure 19: MSB Advanced Wide
Rev. 16 | Page 34 of 43 | www.onsemi.com
BelaSigna 200
Figure 20: MSB Del Short
Figure 21: MSB Del Wide
Rev. 16 | Page 35 of 43 | www.onsemi.com
BelaSigna 200
12.1.2. 32-bit
Figure 22: LSB Advanced Short
Figure 23: LSB Advanced Wide
Rev. 16 | Page 36 of 43 | www.onsemi.com
BelaSigna 200
Figure 24: LSB Del Short
Figure 25: LSB Del Wide
Rev. 16 | Page 37 of 43 | www.onsemi.com
BelaSigna 200
Figure 26: MSB Advanced Short
Figure 27: MSB Advanced Wide
Rev. 16 | Page 38 of 43 | www.onsemi.com
BelaSigna 200
Figure 28: MSB Del Short
Figure 29: MSB Del Wide
Table 14: PCM Interface Descriptions
Parameter
Description
PCM_CLK high to data valid
Tdv
Ts
Tfr
Tch
Tcl
Min.
Max.
50
Unit
ns
Setup time before PCM_CLK high
10
ns
PCM_CLK high to PCM_FRAME high
50
ns
PCM_CLK high period (1.28MHz)
390
ns
PCM_CLK low period (1.28MHz)
390
ns
Rev. 16 | Page 39 of 43 | www.onsemi.com
BelaSigna 200
12.2 GPIO Timing Diagram
Figure 30: GPIO Timing Diagram
Table 15: GPIO Interface Descriptions
Parameter
Description
Tdv
Ts
Tch
Tcl
Min.
Max.
Unit
SYS_CLK high to data valid
50
ns
Setup time before SYS_CLK high
10
ns
SYS_CLK high period (1.28MHz)
390
ns
SYS_CLK low period (1.28MHz)
390
ns
Rev. 16 | Page 40 of 43 | www.onsemi.com
BelaSigna 200
12.3 SPI Port Timing Diagram
Figure 31: SPI Port Timing Diagram
Table 16: SPI Interface Descriptions
Parameter
Description
Tdv
Ts
Tfce
Max.
Unit
SPI_CLK high to output data valid
50
ns
Setup time before SPI_CLK high
10
SPI_CS low to first SPI_CLK high
Min.
ns
ns
Rev. 16 | Page 41 of 43 | www.onsemi.com
BelaSigna 200
13.0 Re-flow Information
The re-flow profile depends on the equipment that is used for the reflow and the assembly that is being reflowed. Use the following
table from the JEDEC Standard 22-A113D Para 3.1.6 for Sn-Pb Eutectic Assembly as a guideline:
Table 17: Re-flow Information
Profile Feature
Sn-Pb Eutectic Assembly
Pb-free Assembly
3°C/second maximum
3°C/second maximum
Temperature minimum (TSMIN)
100°C
150°C
Temperature maximum (TSMAX)
150°C
200°C
Time (min. to max.) (ts)
60-120 seconds
60-180 seconds
Average Ramp-Up Rate (TL to TP)
Preheat
TSMAX to TL
Ramp-up rate
3°C/second maximum
Time Maintained Above
Temperature (TL)
183°C
217°C
Time (tL)
60-150 seconds
60-150 seconds
Peak Temperature (TP)
240 +0/-5°C
260 +0/-5°C
Time within 5°C of Actual Peak Temperature
10-30 seconds
10-30 seconds
Ramp-Down Rate
6°C/second maximum
6°C/second maximum
Time 25°C to Peak Temperature
6 minutes maximum
8 minutes maximum
All BelaSigna 200 QFNs with part number revisions 003 (i.e. 0W344-003-XTP) and higher are Pb-free and should follow the re-flow
guidelines for Pb-free assemblies. All BelaSigna 200 CSPs are Pb-free.
14.0 ESD Sensitive Device
CAUTION: Electrostatic discharge (ESD) sensitive device. Permanent damage may occur on devices subjected
to high-energy electrostatic discharges. Proper ESD precautions in handling, packaging and testing are
recommended to avoid performance degradation or loss of functionality.
15.0 Training
To facilitate development on the BelaSigna 200 platform, training is available upon request. Contact your account manager for more
information.
Rev. 16 | Page 42 of 43 | www.onsemi.com
BelaSigna 200
16.0 Ordering Information
Part Number
Package
Shipping Configuration
Temperature Range
0W344-004-XTP
8x8mm QFN
Tape & Reel (500 parts per reel)
-85 to 40 °C
0W344-005-XTP
8x8mm QFN
Tape & Reel (1000 parts per reel)
-85 to 40 °C
0W588-002-XUA
2.3x2.8mm WLCSP
Tape & Reel (5000 parts per reel)
-85 to 40 °C
17.0 Company or Product Inquiries
For more information about ON Semiconductor’s products or services visit our Web site at http://onsemi.com.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Literature Distribution Center for ON Semiconductor
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Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
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Phone: 421 33 790 2910
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Phone: 81-3-5773-3850
Rev. 16 | Page 43 of 43 | www.onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative