ENA2351 D

Ordering number : ENA2351
LC823425
CMOS LSI
Low Power Consumption
1 chip Audio LSI
for Portable Sound Solution
http://onsemi.com
Overview
LC823425 is an audio processing solution for portable devices such as IC recorders. This product features a built-in
hardwired MP3 encoder/decoder system, enabling the industry’s lowest power consumption of 5mW and supporting
advanced functionality via a built-in digital signal processor (DSP).
Function
 ARM7TDMI-STM1, AMBA® (AHB/APB) system
 Internal SRAM(512kbyte), Internal ROM(128kbyte).
Boot code and built-in standard function
 MultiPort Memory Controller (one CS),
External Memory Controller (two CS)
 DMA controller (2ch), Interrupt controller
(external 5ch + enhancing 16ch, and internal 31ch factor)
 SIO(2ch), UART(2ch),
TQFP128 14x14 / TQFP128L
I2C (1ch Single Master and Full/Standard conforming)
 General-purpose port (I/O 40ch+1ch (FBGA221J is selected)).
 Plain timer (1ch) and multiple timer (2ch3), Watch dog timer (1ch)
 10bit A/D converter (6ch)
 SD card IF(2ch) (w/o CPRM), MemoryStick IF(1ch)
 USB2.0(480Mbps/12Mbps) device IF. Built-in PHY
 RTC (real time clock)
 MP32 hard wired encoder/decoder
 DSP system
WMA3 (Microsoft WMA Decoder Profile Level3 conforming)
AAC (MPEG4 LC-AAC)
LFBGA211 11x11 / FBGA221J
Variable speed playback (0.5-2.0)
 Six band equalizer (EQ3), Highband replication circuit(YY filter), Surround (+EQ2) circuit
 16/24bit PCM interface, Sampling rate converter, BEEP circuit, Digital mic interface
 DA converter and 16bit audio D class amplifier (LC LPF necessity in the outside)
1
ARM7TDMI-STM is the trademark of ARM Limited
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license nor imply any right to distribute content created with this product in
revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications
(via Internet, intranets and/or networks), other content distribution systems (pay-audio or audio-on-demand applications and the
like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like).
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer
Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent
license for such use is required. For details, please visit http://mp3licensing.com/.
3 This product contain technology of Microsoft company ownership, and you cannot distribute or use without getting license from
Microsoft Licensing company.
2
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014
70914HK 20130617-S00001, 20130425-S00003 No.A2351-1/29
LC823425
Specifications
Absolute Maximum Ratings at VSS=0V
Item
Symbol
Maximum power
supply voltage
Condition
Ratings
Vdd1
VddRTC
VddXT1
AVddUSBPHY1
AVddPLL1
AVddDAMPL
AVddDAMPR
Vdd2
VddSD0
VddSD1
AVddADC
AVddPLL2
AVddUSBPHY2
VI
Input voltage
0.5 to 1.8
V
0.5 to 2.5
V
0.5 to 4.6
V
0.5 to VDD+0.5
V
0.5 to AVddUSBPHY2+0.5
V
Topr
20 to +75
C
Tstg
55 to +125
C
VIUSB
Operating ambient
temperature
Ambient temperature of
preservation
Unit
USBDDP, USBDDM terminal
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta=20C to +75C
Item
Power-supply
voltage
Symbol
Low voltage operation
High voltage operation
Unit
Min
Typ
Max
Min
Typ
Max
Vdd1
0.93
1.0
1.1
1.1
1.2
1.3
V
VddXT1
0.93
1.0
1.1
1.1
1.2
1.3
V
AVddPLL1
AVddPLL2
0.93
2.7
1.0
3.3
1.1
3.6
1.1
2.7
1.2
3.3
1.3
3.6
V
V
VddRTC
0.9
1.0
1.3
0.9
1.0
1.3
V
2.7
1.7
2.7
1.7
2.7
1.7
2.7
0.93
2.7(*2)
0.93
0.93
0
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.0
3.3
1.2
1.2
3.6
1.95
3.6
1.95
3.6
1.95
3.6
1.1
3.6
1.65
1.65
VDD
2.7
1.7
2.7
1.7
2.7
1.7
2.7
1.1
2.7(*2)
0.93
0.93
0
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.2
3.3
1.2
1.2
3.6
1.95
3.6
1.95
3.6
1.95
3.6
1.3
3.6
1.65
1.65
VDD
V
V
V
V
V
V
V
V
V
V
V
V
Vdd2
VddSD0
VddSD1
Input voltage range
Condition
AVddADC
AVddUSBPHY1
AVddUSBPHY2
AVddDAMPL
AVddDAMPR
VIN
(*1) Follow the operating frequency specifications because the operating frequency ranges are specified according to the operating
voltage ranges.
(*2) When USB is used (include USB suspend state), this should be 3.0V(MIN).
(*3) At any state
-Vdd1=AVddUSBPHY1=AVddPLL1=VddXT1
-Vdd2, VddSD0, VddSD1, AVddPLL2, AVddADC, AVddUSBPHY2, and AVddDAMPL=AVddDAMPR can be supplied with
different voltages.
However, whenever Vdd1=AVddUSBPHY1=AVddPLL1=VddXT1Vdd2 is supplied, Vdd2, VddSD0, VddSD1,AVddPLL2,
AVddADC, AVddUSBPHY2, and AVddDAMPL=AVddDAMPR must be supplied.
-When only RTC operates, VddRTC can be supplied while *Vdd*=0V(exclude VddRTC) and the BACKUPB=Low input.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A2351-2/29
LC823425
Item
Oscillation input
frequency
Symbol
Fxin1
FxinRTC
Frc
Time to
stabilize of
oscillation
Internal operation
frequency
Condition
ARM7TDMI-S
Surrounding of
ARM
RTC
RC
Min
Low voltage operation
Typ
Max
High voltage operation
Min
Typ
Max
Unit
The same left
MHz
The same left
The same left
kHz
MHz
4
The same left
ms
5
The same left
ms
48MHz±200ppm
0.4
32.768
1
Txin1
2
20
TxinRTC
20
Farm
ARM7TDMI-S
0
55
0
80
MHz
Fahb
ARM AHB
0
55
0
80
MHz
Fapb
ARM APB
0
55
0
80
MHz
Fdsp
DSP
0
110.592
0
110.592
MHz
Faud(*1)
AUDIO(768fs)
0
33.8688
73.728
The same left
MHz
Fdec
MP3 Decoder
0
16.9344
36.864
The same left
MHz
Fenc
MP3 Encoder
0
16.9344
18.432
The same left
MHz
(*1) Almost all of audio functions operate on 256*Fs (sampling frequency) clock,
while SRC(sampling rate converter) and D class amplifier operate on 384*Fs clock.
256*Fs and 384*Fs clocks are generated from 768*Fs base clock.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
4
5
Reference value @Ta=25 celsius degree and Vdd1=1.0V, and depends on circumstances.
Reference value @Ta=25 celsius degree and VddRTC =1.0V, and depends on circumstances.
No.A2351-3/29
LC823425
Electrical Characteristics
at Vdd2=2.7V to 3.6V, VddRTC=0.9V to 1.3V, VddSD0=2.7V to 3.6V, VddSD1=2.7V to 3.6V,
Ta=20C to +75C
Item
Input H level
voltage
Input L level
voltage
Symbol
VIH
VIL
Pin
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Condition
Schmidt
Schmidt
VOH
(12)
IOH=2mA
Output L level
voltage
VOL
Rup
Pull-up resistor
Pull-down resistor
IOH=4mA
Rdn
Input Leake current
IIL
Output leakage
current
IOZ
(12)
(13)
(7)
(8)
(9)
(10)
(12)
(13)
(11)
(12)
(13)
(14)
Max
0.3Vdd2
0.3VddSD0
0.3VddSD1
0.25Vdd2
0.2VddRTC
0.2VddRTC
Schmidt
(13)
(11)
Typ
Schmidt
(10)
Output H level
voltage
Min
0.7Vdd2
0.7VddSD0
0.7VddSD1
0.75Vdd2
0.7VddRTC
0.7VddRTC
Vdd20.4
VddSD00.4
VddSD10.4
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Vdd20.4
V
VddSD00.4
V
VddSD10.4
V
IOH=8mA
Vdd20.4
V
IOH=12mA
VddSD00.4
VddSD10.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.3
V
V
V
V
V
V
V
V
V
V
V
V
IOL=2mA
IOL=4mA
IOL=8mA
IOL=12mA
IOL=0.3mA
(15)
50
80
170
kΩ
(16)
50
80
170
kΩ
(17)
25
50
75
kΩ
(16)
10
17
40
kΩ
(17)
10
17
40
kΩ
(18)
(1)(2)
(3)(4)
(5)(6)
(7)(8)
(9)(10)
(11)(12)
(13)(14)
10
17
40
KΩ
VI=VDD*=VSS
10
10
μA
When Hi-Z is output
10
10
μA
No.A2351-4/29
LC823425
at Vdd2=1.7V to 1.95V, VddSD0=1.7V to 1.95V, VddSD1=1.7V to 1.95V,
Ta=20C to +75C
Item
Input H level
voltage
Input L level
voltage
Output H level
voltage
Symbol
VIH
VIL
VOH
Pin
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
(7)
(8)
(9)
(10)
(12)
Pull-up resistor
Pull-down resistor
Schmidt
VOL
Rup
Rdn
Input Leake current
IIL
Output leakage
current
IOZ
(12)
(13)
(7)
(8)
(9)
(10)
(12)
(13)
(11)
(12)
(13)
(15)
Min
0.7×Vdd2
0.7×VddSD0
0.7×VddSD1
0.75×Vdd2
Typ
IOH=1mA
IOH=2mA
Max
0.3×Vdd2
0.3×VddSD0
0.3×VddSD1
0.25×Vdd2
Schmidt
(13)
(11)
Output L level
voltage
Condition
Vdd20.4
VddSD00.4
VddSD10.4
Unit
V
V
V
V
V
V
V
V
V
V
V
Vdd20.4
V
VddSD00.4
V
VddSD10.4
V
IOH=4mA
Vdd20.4
V
IOH=6mA
VddSD00.4
VddSD10.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
IOL=1mA
IOL=2mA
IOL=4mA
IOL=6mA
90
175
350
kΩ
(16)
90
175
350
kΩ
(17)
10
50
100
kΩ
(16)
20
40
100
kΩ
(17)
20
40
100
kΩ
(18)
20
40
100
KΩ
(1)(2)
(3)(4)
(5)(6)
(7)(8)
(9)(10)
(11)(12)
(13)(14)
VI=VDD*=VSS
10
10
μA
When Hi-Z is output
10
10
μA
No.A2351-5/29
LC823425
(1) TDI, TMS, TCK, PHI, SDI0, SDO0, DIN, DOUT, MPMCDATA[15:0], MPMCADDR14, EXD[15:0]
(2) SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDWP0, SDCD0
(3) SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13, SDWP1, SDCD1
(4) TEST, BMODE[2:0], NRES, NTRST, MCLK, BCK, LRCK, EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03,
EXTINT04, SCK0, SCK1, SDI1, SDO1, TXD1, RXD1, TXD2, RXD2, SCL, SDA, TIOCA0, TIOCA1, TIOCB0, TIOCB1,
TCLKA, TCLKB
(5) VDET
(6) BACKUPB
(7) RTCK, TDO, EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03, EXTINT04, SCK0, SDI0, SDO0, SCK1, SDI1,
SDO1, SCL, SDA, TXD1, RXD1, TXD2, RXD2, TIOCA0, TIOCA1, TIOCB0, TIOCB1, BCK, LRCK, DIN, DOUT, NCS0,
NCS1, NRD, NWRENWRL, NHBNWRH, NLBEXA0, EXA[20:1], EXD[15:0]
(8) SDWP0, SDCD0
(9) SDWP1, SDCD1
(10) MCLK, MPMCCKE, MPMCCS, MPMCWE, MPMCCAS, MCMCRAS, MPMCDQM[1:0], MPMCADDR14,
MPMCADDR13, MPMCADDR[10:0], MPMCDATA[15:0], TCLKA, TCLKB
(11) MPMCCLK, PHI
(12) SDCLK0, SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03
(13) SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13
(14) RTCINT
(15) NTRST, TDI, TMS, TCK
(16) EXTFIQ, EXTINT00, EXTINT01, EXTINT02, EXTINT03, EXTINT04, SCK0, SDI0, SDO0, SCK1, SDI1, SDO1, SCL,
SDA, TXD1, RXD1, TXD2, RXD2, TIOCA0, TIOCA1, TIOCB0, TIOCB1, TCLKA, TCLKB, MCLK, BCK, LRCK, DIN,
DOUT, MPMCADDR14, SDWP0, SDCD0, SDWP1, SDCD1, PHI
(17) SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDCLK1, SDCMD1, SDAT10, SDAT11, SDAT12, SDAT13
(18) EXD[15:0], MPMCDATA[15:0]
(note 1)
Because the following pins can switch the drive ability when it outputs it by the register setting
VOH and two kinds of VOL are provided for. SDCMD0, SDAT00, SDAT01, SDAT02, SDAT03, SDCLK0, SDCMD1,
SDAT10, SDAT1, SDAT12, SDAT13, SDCLK1
(note 2)
It is not included in the DC characteristic about the following pins.
VR, VRH, VRL, USBDDM, USBDDP, USBDEXT12, VCNT1, VCNT2, AN0, AN1, AN2, AN3, AN4, AN5, XIN1, XIN32K,
XOUT1, XOUT32K, LOUT, ROUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2351-6/29
LC823425
Package Dimensions
unit : mm
LC823425-12G1-H : TQFP128L
TQFP128 14x14 / TQFP128L
CASE 932BA
ISSUE O
No.A2351-7/29
LC823425
LC823425-13W1-E : FBGA221J
LFBGA221 11x11 / FBGA221J
CASE 566DJ
ISSUE O
No.A2351-8/29
LC823425
Pin Assignment
I/O
Terminal characteristic
I
O
B
Input pin
Output pin
Interactive pin
3IC
3IS
3ICU
3.3 V CMOS input
3.3V Schmidt input
3.3 V CMOS input pull-up
P
Power supply
pin
Non Connect
3ISU
3.3V Schmidt input pull-up
NC
3ICUD
3ISUD
3O4
3O8
3T2
3T4
3T4(12)
FBGA221J
TQFP128L
No.
1IC
1IS
OD3
3.3 V CMOS input pull-down
Pull-up both correspondences
3.3V Schmidt input pull-down
Pull-up both correspondences
3.3 V 4mA output
3.3 V 8mA output
3.3 V 2mA tristate output
3.3 V 4mA tristate output
3.3 V 4mA/12mA switch tristate output
Pin Name
I/O
Characteristic
1.0 V CMOS input
1.0V Schmidt input
0.3mA open drain output
X
Oscillation amplifier
3A
3.3V analogue
1A
1.0V analogue
3R
3.6V tolerant
Tolerant
IO
Power
supply
Function
No.
Ball
1
C3
-
MPMCDATA0
B
3ICD/3T4
3R
b
SDRAM data bus bit0
2
A1
1
BMODE0
I
3IS
3R
b
Boot mode selector bit0
3
D3
-
MPMCDATA1
B
3ICD/3T4
3R
b
SDRAM data bus bit1
4
E4
-
MPMCDATA2
B
3ICD/3T4
3R
b
SDRAM data bus bit2
5
B2
2
BMODE1
I
3IS
3R
b
6
E3
-
VSS
P
7
B1
-
MPMCDATA3
B
3ICD/3T4
3R
b
8
C1
-
MPMCDATA4
B
3ICD/3T4
3R
b
SDRAM data bus bit4
b
External FIQ
interrupt/general-purpose port
b
SDRAM address bit0 output
9
C2
10
11
12
3
EXTFIQ/GPIO2A
I/B
3ISUD/3T2
D2
-
MPMCADDR0
O
3O4
F4
4
VSS
P
F5
-
Vdd2
P
13
E2
-
MPMCADDR1
O
14
D1
-
MPMCADDR2
O
15
F3
3R
SDRAM data bus bit3
Digital ground
b
Digital IO power supply
3O4
b
SDRAM address bit1 output
3O4
b
5
EXTINT00/GPIO2B
I/B
3ISUD/3T2
3R
b
I/B
3ISUD/3T2
3R
b
16
G4
6
EXTINT01/GPIO2
C
17
E1
-
MPMCADDR3
O
3O4
F2
7
EXTINT02/GPIO2
D
I/B
3ISUD/3T2
19
F1
-
MPMCADDR4
O
3O4
20
G5
-
VSS
P
21
G3
-
MPMCADDR5
O
18
Boot mode selector bi1
Digital ground
3R
SDRAM address bit2 output
External interrupt 0bit0/general-purpose port
External interrupt 0bit1/general-purpose port
b
SDRAM address bit3 output
b
External interrupt 0bit2/general-purpose port
b
SDRAM address bit4 output
Digital ground
3O4
3R
b
SDRAM address bit5 output
b
External interrupt 0bit3/general-purpose port
SDRAM address bit6 output
22
H4
8
EXTINT03/GPIO2E
I/B
3ISUD/3T2
23
G2
-
MPMCADDR6
O
3O4
b
24
G1
-
MPMCADDR7
O
3O4
b
SDRAM address bit7 output
b
External interrupt 0bit4/general-purpose port
25
H3
9
EXTINT04/GPIO2F
I/B
3ISUD/3T2
3R
26
H1
-
MPMCADDR8
O
3O4
b
SDRAM address bit8 output
27
H2
-
MPMCADDR9
O
3O4
b
SDRAM address bit9 output
28
H5
10
Vdd2
P
29
J5
11
VSS
P
30
J1
-
MPMCADDR10
O
3O4
b
SDRAM address bit10 output
31
J4
-
MPMCADDR13
O
3O4
b
SDRAM address bit13 output
b
Digital IO power supply
Digital ground
No.A2351-9/29
LC823425
SD card Ch1 detecting
/general-purpose port
SD card Ch1 write-protection
/Memory Stick
INS/general-purpose port
SD card Ch1 command line
/Memory Stick
BS/general-purpose port
SD card Ch1 data bit0
/Memory Stick data
bit0/general-purpose port
SD card Ch1 data bit1
/Memory Stick data
bit1/general-purpose port
Digital IO power supply (SDI/F Ch1
exclusive use)
SD card Ch1 data bit2
/Memory Stick data
bit2/general-purpose port
SD card Ch1 data bit3
/Memory Stick data
bit3/general-purpose port
SD card Ch1 clock output
/Memory Stick clock
/general-purpose port
32
J2
12
SDCD1/GPIO20
I/B
3ICUD/3T2
3R
s1
33
J3
13
SDWP1/INS
/GPIO21
I/I/B
3ICUD/3T2
3R
s1
34
K1
14
SDCMD1/BS
/GPIO23
B/I
/B
3ICUD
/3T4(12)
3R
s1
35
K2
15
SDAT10/DATA0
/GPIO24
B/B
/B
3ICUD
/3T4(12)
3R
s1
36
K3
16
SDAT11/DATA1
/GPIO25
B/B
/B
3ICUD
/3T4(12)
3R
s1
37
K4
17
VddSD1
38
L1
18
SDAT12/DATA2
/GPIO26
B/B
/B
3ICUD
/3T4(12)
3R
s1
39
L2
19
SDAT13/DATA3
/GPIO27
B/B
/B
3ICUD
/3T4(12)
3R
s1
40
L3
20
SDCLK1/SCLK
/GPIO22
O/O
/B
3ICUD
/3T4(12)
3R
s1
41
K5
21
VSS
P
Digital ground
42
L4
22
Vdd1
P
Digital internal power supply
43
M1
23
SDCLK0
O
P
s1
3T4(12)
3ICUD
/3T4(12)
3ICUD
/3T4(12)
3ICUD
/3T4(12)
s0
SD card I/FCh0 clock output
3R
s0
SD card I/FCh0 command line
3R
s0
SD card I/FCh0 data bit0
3R
s0
SD card I/FCh0 data bit1
s0
Digital IO power supply (SDI/F Ch0
exclusive use)
3R
s0
SD card I/FCh0 data bit2
3R
s0
SD card I/FCh0 data bit3
44
M2
24
SDCMD0
B
45
M3
25
SDAT00
B
46
N1
26
SDAT01
B
47
M4
27
VddSD0
P
48
N2
28
SDAT02
B
49
N3
29
SDAT03
B
50
P1
30
SDCD0/GPIO29
I/B
3ICUD/3T2
3R
s0
51
P2
31
SDWP0/GPIO28
I/B
3ICUD/3T2
3R
s0
52
R1
32
VSS
P
3ICUD
/3T4(12)
3ICUD
/3T4(12)
SD card I/FCh0 detecting
/general-purpose port
SD card I/FCh0 write-protection
/general-purpose port
Digital ground
53
T1
33
AVddUSBPHY1
P
54
R3
34
AVssUSBPHY
P
u1
1.0V power supply for USB-PHY
55
P4
35
AVssUSBPHY
P
56
T2
36
USBDDM
B
3A
u2
USB D-
57
T3
37
USBDDP
B
3A
u2
USB D+
58
R4
38
AVddUSBPHY2
P
u2
3.3V power supply for USB-PHY
Ground for USB-PHY
Ground for USB-PHY
59
T4
39
AVssUSBPHY
P
Ground for USB-PHY
60
R5
40
AVssUSBPHY
P
Ground for USB-PHY
61
T5
41
USBDEXT12
O
u2
USB-PHY reference resistance
62
P3
42
AVddUSBPHY2
P
3A
u2
3.3V power supply for USB-PHY
u1
63
N4
43
AVddUSBPHY1
P
64
R2
44
AVssUSBPHY
P
65
P5
45
VddXT1
P
66
M5
46
XOUT1
O
67
N5
47
VssXT1
P
Ground for oscillation amplifier
I
48MHz oscillation amplifier input
for system
68
L5
48
XIN1
69
T6
49
AVddPLL1
P
70
P6
50
VCNT1
O
71
R6
51
AVssPLL1
P
72
M6
52
Vdd2
P
73
M7
-
MPMCDATA5
B
74
N8
53
TCLKA/GPIO00
/MPMCADDR11
/EXTINT10
I/B
/O
/I
1.0V power supply for USB-PHY
Ground for USB-PHY
x1
X
x1
X
x1
1A
Power supply for oscillation
amplifier
48MHz oscillation amplifier output
for system
p1
Analog power supply for PLL1
p1
VCO control for PLL1
Analog ground for PLL1
b
3ICD/3T4
3ISUD/3T4
3R
3R
Digital IO power supply
b
SDRAM data bus bit5
b
MTM external clock
A/general-purpose port
/SDRAM address bit11
/external interrupt 1- bit0
No.A2351-10/29
LC823425
75
P7
-
76
R7
54
MPMCDATA6
B
3ICD/3T4
3R
b
SDRAM data bus bit6
TCLKB/GPIO01
/MPMCADDR12
/EXTINT11
I/B
/O
/I
3ISUD/3T4
3R
b
MTM external clock
B/general-purpose port
/SDRAM address bit12
/external interrupt 1- bit1
77
T7
-
MPMCDATA7
B
3ICD/3T4
3R
b
SDRAM data bus bit7
78
N7
-
MPMCDATA8
B
3ICD/3T4
3R
b
SDRAM data bus bit8
79
T8
55
O/B
/I
3ICUD/3T8
3R
b
System clock
output/general-purpose port
/external interrupt 1- bit6
80
N6
-
81
P8
56
PHI/GPIO06
/EXTINT16
VSS
P
RTCK
O
Digital ground
3O2
b
JTAG test returned clock
82
N9
-
MPMCDATA9
B
3ICD/3T4
3R
b
SDRAM data bus bit9
83
R8
-
MPMCDATA10
B
3ICD/3T4
3R
b
SDRAM data bus bit10
84
M8
57
TDO
O
3O2
b
JTAG test data output
85
T9
-
MPMCCAS
O
3O4
b
SDRAMCAS output
MPMCRAS
O
3O4
b
VSS
P
MPMCWE
O
3O4
NTRST
I
3ISU
86
R9
-
87
M9
58
88
P9
-
89
T10
59
90
N10
-
Vdd2
P
91
M10
60
Vdd1
P
92
R10
-
MPMCCKE
O
93
P10
-
94
M11
61
SDRAMRAS output
Digital ground
3R
b
SDRAM write enable output
b
JTAG test reset input
b
Digital IO power supply
Digital internal power supply
3O4
MPMCDQM0
O
3O4
NRES
I
3IS
3R
b
SDRAM clock enable output
b
SDRAM data mask byte lane
selector bit0
b
External reset input
95
T11
-
MPMCDQM1
O
3O4
b
SDRAM data mask byte lane
selector bit1
96
R11
-
MPMCCS
O
3O4
b
SDRAM chip selection output
97
T12
-
MPMCCLK
O
3O8
b
98
N11
-
VSS
P
MPMCDATA11
B
3ICD/3T4
3R
b
SDRAM data bus bit11
TDI
I
3ICU
3R
b
JTAG test data input
99
P11
-
100
T13
62
SDRAM clock output
Digital ground
101
R12
-
MPMCDATA12
B
3ICD/3T4
3R
b
SDRAM data bus bit12
102
M12
-
MPMCDATA13
B
3ICD/3T4
3R
b
SDRAM data bus bit13
103
N12
-
MPMCDATA14
B
3ICD/3T4
3R
b
SDRAM data bus bit14
104
P12
63
TMS
I
3ICU
3R
b
JTAG test mode selection
105
R14
-
MPMCDATA15
B
3ICD/3T4
3R
b
106
R13
-
MPMCADDR14
/GPIO17
O
/B
3ICUD/3T4
3R
b
107
P13
-
NHBNWRH
O
3T2
3R
b
108
P14
64
TCK
I
3ICU
3R
b
JTAG test clock
b
External memory chip selection
bit1
109
P15
-
110
T15
111
112
NCS1
O
65
VSS
P
R15
66
Vdd2
P
b
R16
67
VddRTC
P
r
Power supply for RTC
r
32.768KHz oscillation amplifier
input for RTC
113
T16
68
XIN32K
I
114
N13
69
VssRTC
P
3T2
SDRAM data bus bit15
SDRAM address
bit14/general-purpose port
External memory high byte
selection/external memory write
Digital ground
X
Ground for RTC
115
T14
70
XOUT32K
O
X
r
116
M13
71
VDET
I
1IC
r
117
N14
72
RTCINT
O
OD3
118
P16
73
BACKUPB
I
1IS
119
L12
74
Vdd1
120
N15
-
121
M14
75
Digital IO power supply
r
RTC interrupt signal output
r
RTC operation mode (only RTC
operating or entire LSI operating)
P
Digital internal power supply
NCS0
O
b
External memory chip selection
bit0
VSS
P
3T2
3R
32.768KHz oscillation amplifier
output for RTC
RTC power supply down detect
input
Digital ground
No.A2351-11/29
LC823425
122
K12
76
Vdd2
P
123
N16
124
L13
-
NRD
O
3T2
77
TEST
I
3IS
125
M15
-
126
L14
78
NWRENWRL
O
3T2
BMODE2
I
3IS
127
M16
-
EXA1
O
3T2
b
External memory address bit1
128
K13
-
EXA2
O
3T2
b
External memory address bit2
129
L15
79
O/B
/I
3ISUD/3T2
b
I2C clock output/general-purpose
port
/external interrupt 1- bit7
130
J14
-
EXA3
O
3T2
b
External memory address bit3
3T2
b
SCL/GPIO07
/EXTINT17
b
b
3R
b
b
3R
3R
b
Digital IO power supply
External memory lead
Test mode input (connect to digital
ground usually)
External memory low byte external
memory write/selection
Boot mode selector bit2
131
L16
-
EXA4
O
132
K14
80
VSS
P
133
K15
-
EXA5
O
3T2
b
External memory address bit5
134
J12
-
EXA6
O
3T2
b
External memory address bit6
135
K16
81
B/B
/I
3ISUD/3T2
b
I2C data/general-purpose port
/external interrupt 1- bit8
136
J16
-
O
3T2
SDA/GPIO08
/EXTINT18
EXA7
External memory address bit4
Digital ground
3R
b
External memory address bit7
137
J13
82
B/B
3ISUD/3T4
b
PCM master
clock/general-purpose port
138
J15
-
EXA8
O
3T2
b
External memory address bit8
139
H14
-
EXA9
O
3T2
b
External memory address bit9
b
PCM bit clock/general-purpose
port
140
H12
83
141
H16
-
142
G15
84
143
H13
85
144
H15
-
MCLK/GPIO18
BCK/GPIO19
B/B
3ISUD/3T2
EXA10
O
3T2
VSS
P
Vdd2
P
EXA11
O
3R
3R
b
b
3T2
b
145
G16
86
LRCK/GPIO1A
B/B
3ISUD/3T2
3R
b
146
G12
87
DIN/GPIO1B
I/B
3ICUD/3T2
3R
b
147
F16
EXA12
O
3T2
148
G14
88
149
G13
-
VSS
P
150
E16
-
EXA13
O
151
D16
89
152
F12
-
DOUT/GPIO1C
TIOCA0/GPIO09
/EXTINT19
EXA14
TIOCA1/GPIO0A
/EXTINT1A
O/B
3T2
B/B
/I
3ISUD/3T2
EXA15
O
3T2
EXA16
O
3T2
Vdd2
P
154
E11
-
155
C16
-
156
F13
91
157
E15
92
VSS
P
158
F14
-
EXA17
O
E12
93
160
B16
-
161
E13
-
162
A16
94
163
D15
-
3T2
O
90
TXD1/GPIO04
/EXTINT14
EXA18
3R
3R
External memory address bit11
PCMLR clock/general-purpose
port
PCM data input/general-purpose
port
b
External memory address bit12
b
PCM data output/general-purpose
port
b
External memory address bit13
b
MTMCh0A input capture and
output capture/general-purpose
port
/external interrupt 1- bit9
b
External memory address bit14
b
MTMCh1A input capture and
output capture/general-purpose
port
/external interrupt 1- bit10
b
External memory address bit15
b
External memory address bit16
b
Digital IO power supply
Digital ground
3T2
b
External memory address bit17
b
UARTCh1 transmission
data/general-purpose port
/external interrupt 1- bit4
External memory address bit18
O/B
/I
3ISUD/3T2
O
3T2
b
3T2
b
External memory address bit19
b
UARTCh1 receive
data/general-purpose port
/external interrupt 1- bit5
EXA19
O
RXD1/GPIO05
/EXTINT15
I/B
/I
3ISUD/3T2
EXA20
O
3T2
NLBEXA0
3R
Digital IO power supply
Digital ground
3ISUD/3T2
F15
159
3ICUD/3T2
B/B
/I
153
External memory address bit10
Digital ground
164
E14
-
O
165
C15
95
Vdd1
P
166
B15
-
EXD0
B
3R
3R
b
External memory address bit20
External memory low byte
selection
3T2
3R
b
3ICD/3T2
3R
b
Digital internal power supply
External memory data bus bit0
No.A2351-12/29
LC823425
167
D14
-
168
A15
96
169
C14
-
170
D13
-
171
B14
97
172
A14
-
173
C13
-
174
B13
98
175
A13
99
VSS
P
Digital ground
B/B
/O
/I
3ISUD/3T2
3R
b
MTMCh0B input capture and
output capture/general-purpose
port
/digital mic clock output
/external interrupt 1- bit2
EXD1
B
3ICD/3T2
3R
b
External memory data bus bit1
EXD2
B
3ICD/3T2
3R
b
External memory data bus bit2
TIOCB0/GPIO02
/DMCKO
/EXTINT12
TIOCB1/GPIO03
/DMDIN/EXTINT13
EXD3
EXD4
SCK0/GPIO1D
EXD5
SDI0/GPIO1E
B/B
/I/I
3ISUD/3T2
3R
b
MTMCh1B input capture and
output capture/general-purpose
port
/digital mic data input
/external interrupt 1- bit3
B
3ICD/3T2
3R
b
External memory data bus bit3
B
3ICD/3T2
3R
b
External memory data bus bit4
B/B
3ISUD/3T2
3R
b
Cereal I/FCh0
clock/general-purpose port
B
3ICD/3T2
3R
b
External memory data bus bit5
b
Cereal I/FCh0 data
input/general-purpose port
176
C12
177
D12
-
EXD6
B
3ICD/3T2
3R
b
External memory data bus bit6
178
B12
-
EXD7
B
3ICD/3T2
3R
b
External memory data bus bit7
179
D10
100
VSS
P
180
D8
-
Vdd2
P
181
C11
101
182
D11
-
EXD8
183
A12
-
EXD9
184
B11
102
185
A11
-
186
C10
103
187
B10
-
SDO0/GPIO1F
SCK1/GPIO0D
/EXTINT1D
EXD10
I/B
3R
b
B
3ICD/3T2
3R
b
External memory data bus bit8
B
3ICD/3T2
3R
b
External memory data bus bit9
Cereal I/FCh1
clock/general-purpose port
/external interrupt 1- bit13
B/B
/I
3ISUD/3T2
3R
b
B
3ICD/3T2
3R
b
External memory data bus bit10
Cereal I/FCh1 data
input/general-purpose port
/external interrupt 1- bit14
SDI1/GPIO0E
/EXTINT1E
I/B
/I
3ISUD/3T2
3R
b
EXD11
B
3ICD/3T2
3R
b
External memory data bus bit11
Cereal I/FCh1 data
output/general-purpose port
/external interrupt 1- bit15
SDO1/GPIO0F
/EXTINT1F
O/B
/I
189
E10
-
VSS
P
190
A9
-
EXD12
B
192
C9
-
193
A8
106
194
B8
-
195
E9
107
196
C8
-
197
D9
198
E8
199
A7
110
Digital IO power supply
3ICUD/3T2
104
105
Digital ground
b
O/B
A10
B9
3R
Cereal I/FCh0 data
output/general-purpose port
188
191
3ICUD/3T2
TXD2/GPIO0B
/EXTINT1B
EXD13
3ISUD/3T2
3R
b
3ICD/3T2
3R
b
External memory data bus bit12
UARTCh2 transmission
data/general-purpose port
/external interrupt 1- bit11
Digital ground
O/B
/I
3ISUD/3T2
3R
b
B
3ICD/3T2
3R
b
External memory data bus bit13
RXD2/GPIO0C
/EXTINT1C
I/B
/I
3ISUD/3T2
3R
b
UARTCh2 receive
data/general-purpose port
/external interrupt 1- bit12
EXD14
B
3ICD/3T2
3R
b
External memory data bus bit14
b
Digital IO power supply
3ICD/3T2
3R
b
External memory data bus bit15
Vdd2
P
EXD15
B
108
VSS
P
Digital ground
109
AVssDAMPR
P
Analog ground for RchDAMP
ROUT
O
111
AVddDAMPR
3A
P
d1
RchDAMP output
d1
Analog power supply for
RchDAMP
200
E7
201
D7
112
AVddDAMPL
P
202
A6
113
LOUT
O
203
B7
114
AVssDAMPL
P
Ground for LChDAMP
204
B6
115
AVssPLL2
P
Analog ground for PLL2
205
C7
116
VCNT2
O
206
E6
117
AVddPLL2
P
207
C6
118
VSS
P
Digital ground
208
D6
119
Vdd1
P
Digital internal power supply
209
D5
120
AVddADC
P
210
A5
-
VRH
I
3A
3A
3A
d2
Analog power supply for LchDAMP
d2
LchDAMP output
p2
VCO control for PLL2
p2
Analog power supply for PLL2
a
Analog power supply for ADC
a
ADC high reference voltage
No.A2351-13/29
LC823425
211
B5
121
AN5
I
3A
a
ADC input Ch5
212
A4
122
AN4
I
3A
a
ADC input Ch4
213
C5
123
AN3
I
3A
a
ADC input Ch3
214
B4
124
AN2
I
3A
a
ADC input Ch2
215
A3
125
AN1
I
3A
a
ADC input Ch1
216
B3
126
AN0
I
3A
a
ADC input Ch0
217
C4
-
VR
O
3A
a
ADC standard voltage
VRL
I
3A
a
AVssADC
P
218
A2
-
219
E5
127
220
D4
128
221
F6
-
Vdd2
-
P
ADC [ro-rifarensu] voltage
Analog ground for ADC
b
Digital IO power supply
NC
No.A2351-14/29
LC823425
1
A
2
BMOD
VRL
E0
3
4
5
6
AN1
AN4
VRH
LOUT ROUT RXD2
MPMC BMOD
AN0 AN2
DATA E1
3
MPMC EXTFI MPMC
C
VR
DATA Q
DATA
4
MPMC MPMC 0
MPMC
D
Vdd2
ADDR ADDR DATA
2
MPMC 0
MPMC
MPMC 1
E
Vss
ADDR ADDR
DATA
3
1
MPMC EXTIN EXTIN 2
Vss
F
ADDR T02
T00
4
MPMC MPMC MPMC EXTIN
G
ADDR ADDR ADDR T01
7
MPMC 6
MPMC 5
EXTIN EXTIN
H
ADDR ADDR T04
T03
8
MPMC 9
MPMC
SDCD SDWP
J
ADDR 1
ADDR
1
10
13
SDCM SDAT SDAT VddS
K
D1
10
11
D1
B
L
M
N
P
R
T
AN5
AN3
7
8
9
10
11
12
13
14
15
16
EXD1
EXD1
TIOCB
SDO1
EXD9 EXD5 EXD3
RXD1
2
0
0
AVss AVss EXD1
EXD1
TIOCB
EXA1
TXD2
SCK1 EXD7 SCK0
EXD0
PLL2 DAMP 4
1
1
8
L
EXA1
VCNT EXD1 EXD1
SDI1 SDO0 SDI0 EXD4 EXD1 Vdd1
Vss
6
2
5
3
AVdd
AVdd
Vdd1
DAMP
ADC
L
AVss AVdd AVdd
ADC PLL2 DAMP
R
Vdd2 NC
Vdd2 Vss
Vss
AVss
Vdd2 Vss
DAMP
R
EXD8 EXD6 EXD2 Vss
EXA2 TIOC
0
A0
EXA1
EXA1 NLBE
TXD1
Vss
5
9
XA0
EXA1
3
EXA1
EXA1 TIOC EXA1
Vdd2
4
7
A1
2
Vss
DIN
Vss
Vdd2
BCK
Vdd2 EXA9
Vss
EXA6 MCLK EXA3 EXA8 EXA7
Vss
Vdd2 EXA2 Vss
SDAT SDAT SDCL
Vdd1 XIN1
12
13
K1
MPMC
SDCL SDCM SDAT VddS XOUT
Vdd2
DATA
K0
D0
00
D0
1
5
MPMC
SDAT SDAT SDAT AVdd VssX
Vss
DATA
USBP T1
01
02
03
HY1
8
SDCD SDWP AVdd AVss VddX VCNT MPMC
USBP USBP T1
DATA
0
0
1
HY2
HY
6
AVss AVss AVdd AVss AVss TCLK
Vss
USBP USBP USBP USBP PLL1 B
HY
HY
HY2 HY
AVdd USBD USBD
AVss
USBD AVdd MPMC
USBP DM
USBP
EXT1 PLL1 DATA
DP
HY1
HY
2
7
Vdd1 TEST
TDO
Vss
TCLK MPMC
DATA
A
9
MPMC
RTCK
WE
MPMC MPMC
DATA RAS
10
MPMC
PHI
CAS
MPMC
VDET
DATA
13
MPMC
VssR
Vdd2 Vss
DATA TC
14
MPMC MPMC
NHBN
TMS
DQM0 DATA
WRH
11
MPMC MPMC MPMC MPMC
DATA ADDR
CKE CS
12
14
NTRS MPMC MPMC
TDI
T
DQM1 CLK
Vdd1 NRES
DOUT Vss
EXA1 EXA1
1
0
EXA5 SDA
BMOD
SCL
E2
Vss
LRCK
EXA4
NWRE
EXA1
NWRL
RTCIN
NCS0 NRD
T
TCK
NCS1
BACK
UPB
MPMC
VddR
Vdd2
DATA
TC
15
XOUT
XIN32
Vss
32K
K
Top View
No.A2351-15/29
LC823425
Block Diagram
Top View
No.A2351-16/29
LC823425
Audio
No.A2351-17/29
LC823425
Application Circuit Example
XTAL
Peripheral circuit when oscillation operates
XIN
R1
XOUT
R2
C1
Symbol
XIN1/XOUT1
(48MHz)
R1
R2
C1
C2
1MΩ
330Ω
6pF
6pF
C2
Value
XIN32K/XOUT32K
(32.768KHz)
10MΩ
0Ω
10pF
10pF
Notes
 Optimize the circuit constant for each product when you use this oscillation cell and ask to the
manufacturer of the crystal oscillator to investigate (matching investigation) because the best circuit
constant changes depending on the specification of the crystal oscillator used and the ambient
surrounding (parasitic capacitance etc. of an external substrate).
 The values of parts are for reference. There is a possibility that the adjustment is needed according
to the situation of the set.
 The following may be needed as the anti-noise measures of oscillation circuit.
(1) Be adjacent as much as possible, and shorten wiring between elements such as this LSI and
the crystal oscillator.
(2) GND of the oscillation circuit close to GND(VSS) of this LSI as much as possible.
(3) Do not bring the wiring pattern of the large current drive close around the oscillation circuit.
(4) Take wide pattern to avoid the effect of interference of other signals.
No.A2351-18/29
LC823425
When external clock is input
Do as follows when use the external clock signal that is generated outside of LSI by the oscillation module, etc.
XOUT
XIN
Left open
External
clock
Notes
 Input the signal of a full amplitude to XIN (external clock input).
“the signal of a full amplitude” means
VddXT1 = 0.93V to 1.3V, VddRTC = 0.9V to 1.3V, *Vss* = 0V
Ta =20C to +75C
 Maximum voltage (VIH) : 0.7*Vdd or more, and Vdd or less than Vdd.
 Minimum voltage (VIL) : 0.3*Vdd or less, and 0V or more than 0V.
(Vdd means VddXT1 in case of XIN1, and VddRTC in case of XIN32K.)
 There is a possibility of influencing the signal quality when there is a long wire pattern on an circuit
board of XOUT (The terminal opens).
Therefore, recommend to cut the wire pattern on an circuit board or no wire pattern on it.
When not use the oscillation cell
Do as follows when not use the oscillation cell.
XIN
XOUT
Left open
Low or High in
Notes
 Supply the voltage of recommended operating range of
VddRTC/VssRTC(XIN32K/XOUT32K) even if not use the oscillation cell.
(power supply to VddXT1/VssXT1(XIN1/XOUT1) is indispensable)
No.A2351-19/29
LC823425
PLL1 (for System)
The figure below shows the PLL1 circuit. Place the decoupling capacitor in the terminal neighborhood on the board,
and keep low noise by apart from other power supply lines.
AVssPLL1
AVddPLL1
VCNT1
C4
+
R2
C3
R1
AVddPLL1
C2
C1
AVssPLL1
Symbol
R1
R2
C1
C2
C3
C4
Value
100Ω
*MΩ
0.1F
0.001F
0.1F
33F
Serial number or accuracy
±5%
±5%
10% of volume error : ±
10% (20C to +75C) of
temperature property : ±
16CV33BS
C4 : refers to the part of mounting on the catalog of our company (CV-B S Series).
Notes
 Use R2 basically by unmounting. The characteristic of PLL might be improved by mounting R2.
Place the wire pattern.
 The values of parts are for reference. There is a possibility that the adjustment is needed according
to the situation of the set.
 Connect with decoupling capacitor in the terminal neighborhood on the board, and keep low noise
by apart from other power supply lines.
No.A2351-20/29
LC823425
PLL2 (for Audio)
The figure below shows the PLL2 circuit. Place the decoupling capacitor in the terminal neighborhood on the board,
and keep low noise by apart from other power supply lines.
AVssPLL2
AVddPLL2
VCNT2
C4
+
R2
C3
R1
C2
C1
AVddPLL2
AVssPLL2
Symbol
R1
R2
C1
C2
C3
C4
Value
100 to 220Ω
*MΩ
4.7F
0.01 About F
0.1F
33F
Serial number or accuracy
±5%
±5%
10% of volume error : ±
10% of temperature property : ±
(20C to +75C)
16CV33BS
C4 : refers to the part of mounting on the catalog of our company (CV-B S Series).
Notes
 Use R2 basically by unmounting. The characteristic of PLL might be improved by mounting R2.
Place the wire pattern.
 The values of parts are for reference. There is a possibility that the adjustment is needed
according to the situation of the set.
Connect with decoupling capacitor in the terminal neighborhood on the board, and keep low noise
by apart from other power supply lines.
No.A2351-21/29
LC823425
10bit AD converter
ADC Analog Power Supply
This LSI
AVddAD
(*1)
VRH(*3)
AN5-0
VR(*2)(*3)
(*2)
VRL(*3)
AVssAD
ADC Analog Ground
(*1) It is important to get the correct ADC conversion result that the wiring resistance is accurate. Pay
attention to keeping low noize.
It is recommended that the ceramic capacitor of the high frequency type to be used as a decoupling
capacitor between AVddADC and AVssADC.
Place the capacitor close to the terminal of LSI as much as possible so that the wiring length may be
shorten as much as possible.
(*2) When the terminal VR is prepared (LC823425-13W1-E:FBGA221J is used), the ADC conversion speed
(operation clock frequency) is different depending on the value of the capacitor used. Confirm specs of
ADC.
(*3) LC823425-12G1-H:TQFP128L connects VRH and VRL with AVddADC and AVssADC in the package.
VR terminal is open in the package.
No.A2351-22/29
LC823425
USB Device
Refer to "USB20PCB design guideline" document .
No.A2351-23/29
LC823425
Example of circuit in surrounding of terminal JTAG (for ICE use and unused)
Vdd2
Vdd2
JTAG
This LSI
Connector
TCK
TCK
TDI
TDI
TMS
TMS
nTRS
Power on reset(*1)
(open drain output)
nSRS
NTRS
NRES
System reset(*2)
(open drain output)
33
RTCK
TDO
RTCK
TDO
(*1) Power-on reset is a reset signal that becomes active Low only when the power supply is turned on. The
terminal NTRST must be reset only by reset and power-on reset from JTAG.
(*2) System reset is a reset signal that becomes power-on reset and active Low demanded in addition with
the system like manual reset etc. The terminal NRES must be reset by reset and system reset from
JTAG.
Refer to the data sheet for specs for terminal NRES reset. The terminal NTRST is the same specs as the
terminal NRES.
Power-on reset (open drain output) can be realized to connect it with the ground through the capacitor as one
example.
As for the ICE unconnection, TCK, TDI, and the terminal TMS open in the state of internal pull-up ON.
The above-mentioned circuit is an example in the surrounding to correspond to both the ICE use and ICE
unused cases on the assumption of the JTAG ICE use made of YDC (Yokokawa digital computer).
Ask the manufacturer when you use other products.
No.A2351-24/29
LC823425
Example of circuit in surrounding of terminal JTAG (ICE unused)
Vdd2
This LSI
TCK
TDI
TMS
NTRS
NRES
System reset(*1)
RTCK
TDO
(*1) System reset is a reset signal that becomes power-on reset (reset signal that becomes active Low only
when the power supply is turned on) and active Low demanded in addition with the system of manual
reset etc.
TCK, TDI, and the terminal TMS open for ICE unused in the state of internal pull-up ON.
Power-on reset is at least necessary for the terminal NTRST in the same specs as the terminal NRES even
when ICE unused.
The above-mentioned circuit is an example of the assumption of the case with ICE unused, and the
simplification of the circuit in the surrounding.
No.A2351-25/29
LC823425
D class amplifier
Ron
47 μH
220μF
L
15Ω
LOUT
ROUT
RL
Ipp(Irms)
1μF
Output wattmeter calculation
[Condition]
 The DC resistance element of the coil, capacitor is small.
 Maximum output amplitude =90%6 to power supply of PWM
 1.2V=(AVddDAMPL, AVddDAMPR), power-supply voltage of D class amplifier
 2Ω= Turning on resistance of internal transistor for D class amplifier (Ron).
 15Ω= Headphone load resistance (RL)
assume the current that flows to the headphone to be Ipp
Ipp = (1200/2) × 0.9 / (15+2) = 31.7(mA)
Irms = Ipp / SQRT(2) = 22.4(mA)
Prms = Irms2 × 15 = 7.53(mW)
External power supply
D class amplifier power supply (AVddDAMPL,AVddDAMPR) must use a transient response and good power supply.
When the power supply where the transient response is bad is used and the capacity of the capacitor is small, a peculiar
pumping phenomenon to D class amplifier is generated. The power-supply voltage change when the pumping
phenomenon is generated must not exceed the recommended operating range.
6
Theoretical value of Delta-sigma circuit
No.A2351-26/29
LC823425
Power supply sequence
Background
The basis of turn on/off of the power supply is the following order (It is acceptable simultaneously).
 At turning on

Vdd *(IO) 
Vsig (external signal)
Vsig (external signal) 
Vdd *(IO) 
Vdd *(internal)
Vdd *(internal)
 At turning off
Turning on of Vdd *(outside) while Vdd *(internal) are turning off might generate the glitch on IO signals and flow of
through current.To avoid it, the above-mentioned procedure is recommended as a basis of the sequence.
Recommendation
Example 1 of sequence
After grouping power supply terminals into four , , -1, -2 groups, the following order is recommended as a
sequence according to a basic policy in this LSI (It is acceptable simultaneously).
 At turning on




-1

Vsig
-1




 At turning off
Vsig 
(Note)
  (internal circuit operation voltage)The internal logic is reset by   (reset terminal input) and an
irregular state is canceled. Therefore, start up these two power supplies first of all in order of    (It is
acceptable simultaneously).
  -Two can be operated alone. Separately, it is assumed the RTC terminal control sequence, describes, and
refer.
No.A2351-27/29
LC823425
Example 2 of sequence
The following sequence that makes the power supply at same timing as much as possible and simplifies is possible (It
is acceptable simultaneously).
 At turning on


, -1

Vsig
, -1


 At turning off
Vsig 
(Note)
 Regarding -2, It is supposed that the signal collision with an external device cannot occur. In this case,
-2 starts up together with , -1.
Definition of power supply group
 Internal power supply and analog power supplies
 are entire simultaneous power supplies ON, and simultaneous power supplies OFF.
 Vdd1
 VddXT1
 AVddPLL1
 AVddUSBPHY1
 External IO power supply 1
 Vdd2
-1 External IO power supply2 and analog power supply
 VddSD0
 VddSD1
 AVddUSBPHY2
 AVddADC
 AVddPLL2
 AVddDAMPL
 AVddDAMPR
-2 Internal and external IO power supply (sharing)
 VddRTC
(Separately, RTC terminal control sequence is described)
No.A2351-28/29
LC823425
ORDERING INFORMATION
Device
LC823425-12G1-H
Package
TQFP128L
(Pb-Free / Halogen Free)
LC823425-13W1-E
FBGA221J
(Pb-Free)
Shipping (Qty / Packing)
450 / Tray JEDEC
840 / Tray JEDEC
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PS No.A2351-29/29
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