CAT24C32BAC4 D

CAT24C32BC4,
CAT24C32BAC4
32 Kb I2C CMOS Serial
EEPROM 4-ball WLCSP
Description
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The CAT24C32BC4 and CAT24C32BAC4 are 32−Kb CMOS
Serial EEPROM devices available in a 4−ball WLCSP package. Both
devices are internally organized as 4096 words of 8 bits each.
They feature a 32−byte page write buffer and support the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
The CAT24C32BC4 and CAT24C32BAC4 respond to a different
Slave Address and are therefore suitable in applications that require
two serial EEPROM devices with 4−ball WLCSP on the same I2C bus.
WLCSP−4
C4C SUFFIX
CASE 567JY
Features
•
•
•
•
•
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
4−ball WLCSP Package
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN CONFIGURATION (Top View)
1
VCC
A1
A2
VSS
SCL
B1
B2
SDA
WLCSP (C4C)
MARKING
DIAGRAM
X
X
YM
= Specific Device Code
= B: CAT24C32BC4
= J: CAT24C32BAC4
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
Y
M
For the location of Pin 1, please consult the
corresponding package drawing.
VCC
PIN FUNCTION
Pin Name
SCL
CAT24C32BC4
CAT24C32BAC4
SDA
SCL
VCC
VSS
SDA
Function
Serial Data
Serial Clock
Power Supply
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
VSS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
CAT24C32BAC4/D
CAT24C32BC4, CAT24C32BAC4
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Note 3)
TDR
Endurance
Data Retention
Min
Units
1,000,000
Program/Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 1 MHz
0.4
mA
ICCW
Write Current
Write
0.6
mA
ISB
Standby Current
All I/O Pins at GND or VCC
1
mA
IL
I/O Pin Leakage
Pin at GND or VCC
2
mA
Input Low Voltage
VCC ≥ 2.2 V
−0.5
VCC x 0.3
V
VCC < 2.2 V
−0.5
VCC x 0.25
V
VCC ≥ 2.2 V
VCC x 0.7
VCC + 0.5
V
VCC < 2.2 V
VCC x 0.75
VCC + 0.5
V
VCC ≥ 2.2 V, IOL = 3.0 mA
0.4
V
VCC < 2.2 V, IOL = 1.0 mA
0.2
V
VIL
VIH
VOL
Input High Voltage
Output Low Voltage
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 4)
Input Capacitance (other pins)
VIN = 0 V
6
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT24C32BC4, CAT24C32BAC4
Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C) (Note 5)
Standard
Parameter
Symbol
FSCL
tHD:STA
Min
Fast
Max
Clock Frequency
Min
100
START Condition Hold Time
Fast−Plus
Max
Min
400
Max
Units
1,000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
tHIGH
High Period of SCL Clock
4
0.6
0.35
ms
4.7
0.6
0.25
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
0
ms
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 6)
SDA and SCL Rise Time
tF (Note 6)
SDA and SCL Fall Time
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between
STOP and START
tAA
SCL Low to Data Out Valid
tDH (Note 6)
Ti (Note 6)
tWR
tPU (Notes 6, 7)
Data Out Hold Time
1,000
300
300
300
100
ns
100
ns
4
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
100
0.9
100
0.40
50
ms
ns
Noise Pulse Filtered at SCL
and SDA Inputs
50
50
50
ns
Write Cycle Time
4
4
4
ms
0.35
0.35
0.35
ms
Power−up to Ready Mode
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Test conditions according to “A.C. Test Conditions” table.
6. Tested initially and after a design or process change that affects this parameter.
7. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
VCC ≥ 2.2 V: 0.2 x VCC to 0.8 x VCC
VCC < 2.2 V: 0.15 x VCC to 0.85 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.3 x VCC, 0.7 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.2 V); IOL = 1 mA (VCC < 2.2 V); CL = 100 pF
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CAT24C32BC4, CAT24C32BAC4
Power−On Reset (POR)
Each CAT24C32BC4/CAT24C32BAC4 incorporates
Power−On Reset (POR) circuitry which protects the internal
logic against powering up in the wrong state. The device will
power up into Standby mode after VCC exceeds the POR
trigger level and will power down into Reset mode when
VCC drops below the POR trigger level. This bi−directional
POR behavior protects the device against ‘brown−out’
failure following a temporary loss of power.
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The first 4 bits of the Slave address are set to
1010. The next 3 bits are set to 0 0 0 ( CAT24C32BC4) or to
1 0 0 (CAT24C32BAC4). The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is to be performed.
Functional Description
The CAT24C32BC4/CAT24C32BAC4 supports the
Inter−Integrated Circuit (I2C) Bus protocol. The protocol
relies on the use of a Master device, which provides the clock
and directs bus traffic, and Slave devices which execute
requests. The CAT24C32BC4/CAT24C32BAC4 operates
as a Slave device. Both Master and Slave can transmit or
receive, but only the Master can assign those roles.
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
0
0
0
R/W
CAT24C32BC4
1
0
1
0
1
0
0
R/W
CAT24C32BAC4
Figure 3. Slave Address Bits
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4
CAT24C32BC4, CAT24C32BAC4
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY (RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tHD:DAT
tSU:STA
tSU:DAT
tHD:STA
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
Delivery State
The CAT24C32BC4/CAT24C32BAC4 is shipped erased,
i.e., all bytes are FFh.
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CAT24C32BC4, CAT24C32BAC4
BUS ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 − a0
d7 − d0
a15 − a8
S
S
T
O
P
P
* * * *
A
C
K
A
C
K
SLAVE
*a15 − a12 are don’t care bits.
A
C
K
A
C
K
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
BUS
ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n
ADDRESS
BYTE
DATA
BYTE
n+1
S
T
O
P
DATA
BYTE
n+P
P
S
SLAVE
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Sequence
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A
C
K
A
C
K
A
C
K
A
C
K
CAT24C32BC4, CAT24C32BAC4
READ OPERATIONS
Immediate Read
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 10).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 9). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 11). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
N
O
BUS ACTIVITY: S
T
A
MASTER R
T
S
A T
CO
K P
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
SCL
8
SDA
DATA
BYTE
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 9. Immediate Read Sequence and Timing
BUS ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
S
T
A
R
T
ADDRESS
BYTE
S
N
O
A
C
K
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
DATA
BYTE
Figure 10. Selective Read Sequence
N
O
A
C
K
BUS ACTIVITY:
MASTER
A
C
K
SLAVE
ADDRESS
A
C
K
A
C
K
S
T
O
P
P
SLAVE
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
Figure 11. Sequential Read Sequence
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7
S
T
O
P
DATA
BYTE
n+x
CAT24C32BC4, CAT24C32BAC4
PACKAGE DIMENSIONS
WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O
ÈÈ
ÈÈ
A
D
PIN A1
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
2X
0.05 C
2X
0.05 C TOP VIEW
DETAIL A
MILLIMETERS
DIM
MIN
MAX
A
−−−
0.35
A1 0.0415 0.0715
A2
0.255 REF
A3
0.025 REF
b
0.15
0.16
D
0.76 BSC
E
0.76 BSC
e
0.40 BSC
A3
DIE COAT
(OPTIONAL)
A2
DETAIL A
A2
0.05 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
A1
NOTE 3
4X
SEATING
PLANE
A1
PACKAGE
OUTLINE
e
b
0.05 C A B
C
SIDE VIEW
e
0.40
PITCH
B
0.03 C
A
4X
0.40
PITCH
0.16
DIMENSIONS: MILLIMETERS
1
2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
Package Type
Temperature Range
Lead Finish
Shipping
CAT24C32BC4CTR
B
WLCSP−4
with Die Coat
I = Industrial
(−40°C to +85°C)
SnAg
Tape & Reel,
5,000 Units / Reel
CAT24C32BAC4CTR (Note 10)
J
WLCSP−4
with Die Coat
I = Industrial
(−40°C to +85°C)
SnAg
Tape & Reel,
5,000 Units / Reel
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10. This WLCSP−4 option responds to a different Slave Address compared to CAT24C32BC4CTR.
11. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultra violet light. When exposed to ultra violet light
the EEPROM cells lose their stored data.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT24C32BAC4/D
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