CAS93C66VP2 D

CAS93C66VP2
4 Kb Microwire Serial CMOS
EEPROM
Description
The CAS93C66VP2 is a 4 kb CMOS Serial EEPROM device which
is organized as either 256 registers of 16 bits (ORG pin at VCC) or 512
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The device features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 4 MHz
1.7 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−pad TDFN Package
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
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TDFN−8
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
(Top View)
1
CS
8 VCC
SK
2
7 NC
DI
3
6 ORG
DO
4
5 GND
TDFN (VP2)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
VCC
ORG
CS
CAS93C66VP2
SK
DO
DI
GND
Figure 1. Functional Symbol
CAS93C66VP2 Selectable Organization:
When the ORG pin is connected to VCC, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 1
1
Publication Order Number:
CAS93C66VP2/D
CAS93C66VP2
Table 1. PIN FUNCTION
Pin Name
Function
Pin Name
Function
CS
Chip Select
VCC
Power Supply
SK
Clock Input
GND
Ground
DI
Serial Data Input
ORG
Memory Organization
DO
Serial Data Output
NC
No Connection
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 3. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
NEND (Note 3)
TDR
Endurance
Data Retention
Min
Units
1,000,000
Program / Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
(VCC = +1.7 V to +5.5 V, TA = −40°C to +85°C unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
1
mA
500
mA
ICC1
Power Supply Current
(Write)
ICC2
Power Supply Current
(Read)
fSK = 2 MHz
ISB1
Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC,
CS = GND ORG = GND
TA = −40°C to +85°C
2
mA
ISB2
Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
TA = −40°C to +85°C
1
mA
ILI
Input Leakage Current
VIN = GND to VCC
TA = −40°C to +85°C
1
mA
ILO
Output Leakage Current
VOUT = GND to VCC,
CS = GND
TA = −40°C to +85°C
1
mA
VIL1
Input Low Voltage
4.5 V ≤ VCC < 5.5 V
−0.1
0.8
V
VIH1
Input High Voltage
4.5 V ≤ VCC < 5.5 V
2
VCC + 1
V
VIL2
Input Low Voltage
1.7 V ≤ VCC < 4.5 V
0
VCC x 0.2
V
VIH2
Input High Voltage
1.7 V ≤ VCC < 4.5 V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
4.5 V ≤ VCC < 5.5 V, IOL = 3.0 mA
0.4
V
VOH1
Output High Voltage
4.5 V ≤ VCC < 5.5 V, IOH = −400 mA
VOL2
Output Low Voltage
1.7 V ≤ VCC < 4.5 V, IOL = 1 mA
VOH2
Output High Voltage
1.7 V ≤ VCC < 4.5 V, IOH = −100 mA
2.4
V
0.2
VCC − 0.2
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
CAS93C66VP2
Table 5. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Test
Conditions
Output Capacitance (DO)
Symbol
COUT (Note 4)
CIN (Note 4)
Max
Units
VOUT = 0 V
5
pF
VIN = 0 V
5
pF
Input Capacitance (CS, SK, DI, ORG)
Min
Typ
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. A.C. CHARACTERISTICS
(VCC = +1.7 V to +5.5 V, TA = −40°C to +85°C, unless otherwise specified.) (Note 5)
VCC . 4.5 V
VCC < 4.5 V
Symbol
Min
Parameter
Max
Max
Units
tCSS
CS Setup Time
tCSH
CS Hold Time
tDIS
DI Setup Time
tDIH
DI Hold Time
100
tPD1
Output Delay to 1
0.25
0.1
ms
tPD0
Output Delay to 0
0.25
0.1
ms
Output Delay to High−Z
100
100
ns
4
ms
tHZ (Note 6)
tEW
50
Min
50
ns
0
0
ns
100
50
ns
50
ns
Program/Erase Pulse Width
4
tCSMIN
Minimum CS Low Time
0.25
0.1
ms
tSKHI
Minimum SK High Time
0.25
0.1
ms
tSKLOW
Minimum SK Low Time
0.25
0.1
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
0.25
DC
2000
DC
0.1
ms
4000
kHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 7. POWER−UP TIMING (Notes 7, 8)
Parameter
Symbol
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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3
CAS93C66VP2
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V ≤ VCC ≤ 5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V ≤ VCC ≤ 5.5 V
Input Pulse Voltages
0.2 VCC to 0.7 VCC
1.7 V ≤ VCC ≤ 4.5 V
Timing Reference Voltages
0.5 VCC
1.7 V ≤ VCC ≤ 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL = 100 pF
Device Operation
The CAS93C66VP2 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAS93C66VP2 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The device operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
Table 9. INSTRUCTION SET
Address
Data
Instruction
Start Bit
Opcode
x8
x16
READ
1
10
A8−A0
A7−A0
Read Address AN – A0
ERASE
1
11
A8−A0
A7−A0
Clear Address AN – A0
WRITE
1
01
A8−A0
A7−A0
EWEN
1
00
11XXXXXXX
11XXXXXX
Write Enable
EWDS
1
00
00XXXXXXX
00XXXXXX
Write Disable
ERAL
1
00
10XXXXXXX
10XXXXXX
Clear All Addresses
WRAL
1
00
01XXXXXXX
01XXXXXX
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4
x8
D7−D0
D7−D0
x16
D15−D0
D15−D0
Comments
Write Address AN – A0
Write All Addresses
CAS93C66VP2
Read
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAS93C66VP2
will come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAS93C66VP2 after the initial data word has
been shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
tSKHI
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAS93C66VP2 write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read normally
from the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 4.
tSKLOW
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tPD0, tPD1
tDIS
DO
tCSMIN
DATA VALID
Figure 2. Synchronous Data Timing
SK
CS
Don’t Care
AN
DI
1
1
AN−1
A0
0
tPD0
DO
HIGH−Z
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Figure 3. READ Instruction Timing
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Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
CAS93C66VP2
Write
Erase
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the
CAS93C66VP2 can be determined by selecting the device
and polling the DO pin. Since this device features
Auto−Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAS93C66VP2 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
SK
STANDBY
CS
DI
1
0
0
* ENABLE = 11
DISABLE = 00
*
Figure 4. EWEN/EWDS Instruction Timing
SK
tCSMIN
CS
STATUS
VERIFY
AN AN−1
DI
1
0
A0
DN
STANDBY
D0
1
tSV
BUSY
HIGH−Z
DO
READY
tHZ
HIGH−Z
tEW
Figure 5. Write Instruction Timing
SK
CS
AN
DI
1
1
AN−1
A0
tCS
STATUS
VERIFY
1
tSV
DO
STANDBY
HIGH−Z
BUSY
tEW
Figure 6. Erase Instruction Timing
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6
tHZ
READY
HIGH−Z
CAS93C66VP2
Erase All
Write All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
1
0
0
tSV
tHZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
tEW
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
1
DN
D0
tSV
tHZ
DO
BUSY
READY
HIGH−Z
tEW
Figure 8. WRAL Instruction Timing
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CAS93C66VP2
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK
ISSUE A
D
e
A
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A3
b
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
L
BOTTOM VIEW
0.20 REF
e
FRONT VIEW
0.50 TYP
0.20
0.30
L
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAS93C66VP2
Table 10. ORDERING INFORMATION
OPN
Specific
Device
Marking
Pkg Type
Temperature Range
Lead Finish
Shipping
CAS93C66VP2I−GT3
FU
TDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10. The standard lead finish is NiPdAu.
11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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CAS93C66VP2/D
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