CAT1027 D

CAT1026, CAT1027
Dual Voltage Supervisory Circuits with
I²C Serial 2k-bit CMOS EEPROM
supply monitor and reset circuit protects memory and
systems controllers during power up/down and
against brownout conditions. If power supply voltages
are out of tolerance reset signals become active
preventing the system microcontroller, ASIC, or
peripherals from operating.
FEATURES
Precision VCC Power Supply Voltage Monitor
— 5 V, 3.3 V and 3 V systems
— Five threshold voltage options
Additional voltage monitoring
— Externally adjustable down to 1.25 V
The CAT1026 features two open drain reset outputs:
¯¯¯¯¯¯)
one (RESET) drives high and the other (RESET
drives low whenever VCC falls below the threshold.
Reset outputs become inactive typically 200ms after
the supply voltage exceeds the reset threshold value.
With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. CAT1027
¯¯¯¯¯¯ output. In addition, the RESET
¯¯¯¯¯¯ pin
has only a RESET
can be used as an input for push-button manual reset
capability.
Watchdog timer (CAT1027 only)
Active High or Low Reset
— Valid reset guaranteed at VCC = 1 V
400 kHz I2C Bus
2.7 V to 5.5 V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
The CAT1026 and CAT1027 provide an auxiliary
voltage sensor input, VSENSE, which is used to monitor a
second system supply. The auxiliary high impedance
comparator drives the open drain output, VLOW,
whenever the sense voltage is below 1.25 V threshold.
1,000,000 Program/Erase cycles
Manual Reset capability
100 year data retention
Industrial and extended temperature ranges
The CAT1027 is designed with a 1.6 second
watchdog timer circuit that resets a system to a known
state if software or a hardware glitch halts or “hangs”
the system. The CAT1027 features a watchdog timer
interrupt input, WDI.
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8 mm
For Ordering Information details, see page 19.
The on-chip 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
DESCRIPTION
The CAT1026 and CAT1027 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400 kHz I2C bus.
Available packages include 8-pin DIP and surface
mount, 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8 mm maximum. TDFN footprint is 3 x 3 mm.
The CAT1026 and CAT1027 provide a precision VCC
sense circuit with five reset threshold voltage options
that support 5 V, 3.3 V and 3 V systems. The power
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
BLOCK DIAGRAM
RESET THRESHOLD OPTION
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WORDADDRESS
BUFFERS
VSS
COLUMN
DECODERS
START/STOP
LOGIC
SDA
XDEC
2kbit
EEPROM
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
CONTROL
LOGIC
DATA IN STORAGE
VCC Monitor
HIGHVOLTAGE/
TIMING CONTROL
VCC
STATE COUNTERS
+
VREF
RESET
Controller
-
AuxiliaryVoltage Monitor
VSENSE
+
VREF
WDI
(CAT1027)
SCL
SLAVE
ADDRESS
COMPARATORS
RESET
RESET
(CAT1026)
VLOW
-
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (ZD4)
VCC
7
RESET
1 VLOW
1
¯¯¯¯¯¯
RESET
2
VSENSE
3
6
SCL
SCL 6
3 VSENSE
VSS
4
5
SDA
SDA 5
4 VSS
VLOW
1
8
VCC
VCC 8
1 VLOW
¯¯¯¯¯¯
RESET
2
7
WDI
WDI 7
Doc. No. MD-3010 Rev. P
8
VCC 8
VLOW
RESET 7
CAT1026
CAT1026
CAT1027
CAT1027
¯¯¯¯¯¯
2 RESET
¯¯¯¯¯¯
2 RESET
VSENSE
3
6
SCL
SCL 6
3 VSENSE
VSS
4
5
SDA
SDA 5
4 VSS
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
PIN FUNCTION
PIN DESCRIPTION
Pin
Name
¯¯¯¯¯¯
RESET
¯¯¯¯¯¯: RESET OUTPUTs
RESET/RESET
(RESET CAT1026 Only)
¯¯¯¯¯¯ can be used
These are open drain pins and RESET
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
¯¯¯¯¯¯ pin must be connected through a pull-up
RESET
resistor.
Ground
SDA
Serial Data/Address
SCL
Clock Input
VCC
Active High Reset Output
(CAT1026 only)
Power Supply
VSENSE
SCL: SERIAL CLOCK
Serial clock input.
Active Low Reset Input/Output
VSS
RESET
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Function
Auxiliary Voltage Monitor Input
VLOW
Auxiliary Voltage Monitor Output
WDI
Watchdog Timer Interrupt
(CAT1027 only)
OPERATING TEMPERATURE RANGE
VSENSE: AUXILIARY VOLTAGE MONITOR INPUT
The VSENSE input is a second voltage monitor which is
compared against CAT1026 and CAT1027 internal
reference voltage of 1.25 V typically. Whenever the
input voltage is lower than 1.25 V, the open drain VLOW
output will be driven low. An external resistor divider is
used to set the voltage level to be sensed. Connect
VSENSE to VCC if unused.
Industrial
-40ºC to 85ºC
Extended
-40ºC to 125ºC
VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when VSENSE is less
than 1.25 V and goes high when VSENSE exceeds the
reference voltage.
WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low
to high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
CAT10XX FAMILY OVERVIEW
Device
Manual
Reset
Input Pin
Watchdog
Watchdog
Monitor
Pin
SDA
SDA
WDI
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
EEPROM
2k
CAT1021
CAT1022
2k
2k
CAT1023
CAT1024
2k
2k
CAT1025
2k
CAT1026
WDI
CAT1027
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
ABSOLUTE MAXIMUM RATINGS (1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
VCC with Respect to Ground
Ratings
Units
–55 to +125
ºC
–65 to +150
ºC
–2.0 to VCC + 2.0
V
–2.0 to 7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 s)
300
ºC
100
mA
Output Short Circuit Current
(3)
D.C. OPERATING CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
ILI
Input Leakage Current
VIN = GND to VCC
ILO
Output Leakage Current
VIN = GND to VCC
ICC1
Power Supply Current
(Write)
ICC2
ISB
VIL(4)
VIH
(4)
Max
Units
-2
10
µA
-10
10
µA
fSCL = 400 kHz
VCC = 5.5 V
3
mA
Power Supply Current
(Read)
fSCL = 400 kHz
VCC = 5.5 V
1
mA
Standby Current
CAT1026
Vcc = 5.5 V,
VIN = GND or VCC CAT1027
Input Low Voltage
-0.5
50
60
0.3 x VCC
Input High Voltage
0.7 x VCC
VCC + 0.5
V
0.4
V
VOL
Output Low Voltage
¯¯¯¯¯¯)
(SDA, RESET
IOL = 3 mA
VCC = 2.7 V
VOH
Output High Voltage
(RESET)
IOH = -0.4 mA
VCC = 2.7 V
VTH
VRVALID
Typ
Reset Threshold
VCC - 0.75
V
V
CAT102x-45 (VCC = 5.0 V)
4.50
4.75
CAT102x-42 (VCC = 5.0 V)
4.25
4.50
CAT102x-30 (VCC = 3.3 V)
3.00
3.15
CAT102x-28 (VCC = 3.3 V)
2.85
3.00
CAT102x-25 (VCC = 3.0 V)
2.55
2.70
Reset Output Valid VCC
Voltage
µA
V
1.00
V
mV
VRT(5)
Reset Threshold Hysteresis
15
VREF
Auxiliary Voltage Monitor
Threshold
1.2
1.25
1.3
VS
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) VIL min and VIH max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. MD-3010 Rev. P
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
CAPACITANCE
TA = 25ºC, f = 1.0 MHz, VCC = 5 V
Symbol
COUT
CIN
(1)
(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
Max
Units
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
(1)
SDA and SCL Rise Time
300
ns
(1)
SDA and SCL Fall Time
300
ns
tR
tF
tHD; STA
Start Condition Hold Time
0.6
µs
tSU; STA
Start Condition Setup Time (for a Repeated Start)
0.6
µs
tHD; DAT
Data Input Hold Time
0
ns
tSU; DAT
Data Input Setup Time
100
ns
tSU; STO
Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
50
Time the Bus must be Free Before a New Transmission Can Start
1.3
tBUF
(1)
tWC(3)
900
Write Cycle Time (Byte or Page)
ns
ns
µs
5
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
tPURST
tRDP
tGLITCH
Test Conditions
Min
Typ
Max
Units
Reset Timeout
Note 2
130
200
270
ms
VTH to RESET Output Delay
Note 3
5
µs
Note 4, 5
30
ns
VCC Glitch Reject Pulse Width
tWD
tRPD2
1
Watchdod Timeout
Note 1
VSENSE to VLOW Delay
Note 5
1.0
1.6
2.1
s
5
µs
Max
Units
POWER-UP TIMING (6), (7)
Symbol
Parameter
Test Conditions
Min
Typ
tPUR
Power-Up to Read Operation
270
ms
tPUW
Power-Up to Write Operation
270
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
10 ns
Input Reference Voltages
0.3 x VCC, 0.7 x VCC
Output Reference Voltages
Output Load
0.5 x VCC
Current Source: IOL = 3 mA; CL = 100 pF
RELIABILITY CHARACTERISTICS
Symbol
NEND
(6)
TDR(6)
VZAP(6)
ILTH(6)(8)
Parameter
Reference Test Method
Min
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
JEDEC Standard 17
100
mA
Latch-Up
Max
Units
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5) 0 < VSENSE - VCC, VLOW Output Reference Voltage and Load according to “AC Test Conditions” Table.
(6) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(7) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(8) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.
Doc. No. MD-3010 Rev. P
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
DEVICE OPERATION
Reset Controller Description
The CAT1026 and CAT1027 precision RESET
controllers ensure correct system operation during
brownout and power up/down conditions. They are
configured with open drain RESET outputs.
reduce the system power consumption. The VLOW
output can be externally connected to the RESET
output to generate a reset condition when either of the
supplies is invalid. In other applications, VLOW signal
can be used to interrupt the system controller for an
impending power failure notification.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200 ms (tPURST)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
Data Protection
The CAT1026 and CAT1027 devices have been designed to solve many of the data corruption issues that
have long been associated with serial EEPROMs. Data
corruption occurs when incorrect data is stored in a
memory location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal nonvolatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5 ms) before VCC reaches the minimum value of 2 V.
During power-down, the RESET outputs will be active
¯¯¯¯¯¯ output will be
when VCC falls below VTH. The RESET
valid so long as VCC is >1.0 V (VRVALID). The device is
designed to ignore the fast negative going VCC transient pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Capability
¯¯¯¯¯¯ pin can operate as reset output and
The RESET
manual reset input. The input is edge triggered; that
¯¯¯¯¯¯ input will initiate a reset timeout after
is, the RESET
detecting a high to low transition.
In addition, to avoid data corruption due to the loss of
power supply voltage during the memory internal write
operation, the system controller should monitor the
unregulated DC power. Using the second voltage
sensor, VSENSE, to monitor an unregulated power
supply, the CAT1026 and CAT1027 signals an impending power failure by setting VLOW low.
¯¯¯¯¯¯ I/O is driven to the active state, the
When RESET
200 ms timer will begin to time the reset interval. If
external reset is shorter than 200 ms, Reset outputs
will remain active at least 200 ms.
Monitoring Two Voltages
The CAT1026 and CAT1027 feature a second voltage
sensor, VSENSE, which drives the open drain VLOW
output low whenever the input voltage is below
1.25 V. The auxiliary voltage monitor timing is shown
in Figure 2.
Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the
CAT1027 device will provide a reset signal after a
time-out interval of 1.6 seconds for a lack of activity.
CAT1027 is designed with the Watchdog timer feature
on the WDI pin. If WDI does not toggle within 1.6
second intervals, the reset condition will be generated
on reset output. The watchdog timer is cleared by any
transition on monitored line.
By using an external resistor divider the sense
circuitry can be set to monitor a second supply in the
system. The circuit shown in Figure 3 provides an
externally adjustable threshold voltage, VTH_ADJ to
monitor the auxiliary voltage. The low leakage current
at VSENSE allows the use of large value resistors, to
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
As long as reset signal is asserted, the watchdog
timer will not count and will stay cleared.
7
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
Figure 1. RESET Output Timing
t
GLITCH
VTH
VRVALID
t PURST
VCC
t RPD
t RPD
t PURST
RESE T
RESE T
Figure 2: Auxiliary Voltage Monitor Timing
VREF
VSENSE
tRPD2
tRPD2
tRPD2
tRPD2
VLOW
Figure 3: Auxiliary Voltage Monitor
VCC
VAUX
CAT1026/27
Externally adjustable
threshold
R1
VTH-ADJ
VLOW
Power Fail
Interrupt
VSENSE
R2
VTH-ADJ = VREF ×
Doc. No. MD-3010 Rev. P
R + R2
R1 + R2
= 1.25V × 1
R2
R2
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
EMBEDDED EEPROM OPERATION
The CAT1026 and CAT1027 feature a 2-kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter
or receiver, but the Master device controls which mode
is activated.
monitor the SDA and SCL lines and will not respond
until this condition is met.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
2
I C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT1026 and CAT1027
monitor the bus and responds with an acknowledge
(on the SDA line) when its address matches the
transmitted slave address. The CAT1026 and
CAT1027 then perform a Read or Write operation
depending on the R/W̄¯ bit.
START CONDITION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT1026 and CAT1027
Figure 3. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
START
CONDITION
ADDRESS
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W̄¯ bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1026 and CAT1027 acknowledge once more
and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle
to non-volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
The CAT1026 and CAT1027 respond with an
acknowledge after receiving a START condition and
its slave address. If the device has been selected
along with a write operation, it responds with an
acknowledge after receiving each 8-bit byte.
When the CAT1026 and CAT1027 begin a READ
mode it transmits 8 bits of data, releases the SDA
line and monitors the line for an acknowledge. Once
it receives this acknowledge, the CAT1026 and
CAT1027 will continue to transmit data. If no
acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 7: Slave Address Bits
Default Configuration
Doc. No. MD-3010 Rev. P
1
0
1
10
0
0
0
0
R/W
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
Page Write
The CAT1026 and CAT1027 write up to 16 bytes of
data in a single write cycle, using the Page Write
operation. The page write operation is initiated in the
same manner as the byte write operation, however
instead of terminating after the initial byte is
transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted,
the CAT1026 and CAT1027 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1026 and CAT1027 in a single write cycle.
Figure 8. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
A
C
K
A
C
K
Figure 9: Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
S
T
DATA n+15 O
P
DATA n+1
S
P
A
C
K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
A
C
K
11
A
C
K
A
C
K
A
C
K
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1026 and CAT1027
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write
operation, no ACK will be returned. If a write
operation has completed, an ACK will be returned
and the host can then proceed with the next read or
write operation.
READ OPERATIONS
The READ operation for the CAT1026 and CAT1027 is
initiated in the same manner as the write operation with
one exception, the R/W̄¯ bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Figure 10. Immediate Address Read Timing
BUS ACTIVIT Y:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
SCL
SDA
8
N
O
A
C
K
9
8TH BI T
DATA OUT
Doc. No. MD-3010 Rev. P
DATA
NO ACK
12
STOP
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
Immediate/Current Address Read
The CAT1026 and CAT1027 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1026and CAT1027 receive its
slave address information (with the R/W̄¯ bit set to
one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not
send an acknowledge, but will generate a STOP
condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave
address again, this time with the R/W̄¯ bit set to one.
The CAT1026 and CAT1027 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1026 and CAT1027 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1026 and CAT1027 address bits so that the entire
memory array can be read during one operation.
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
T
O
P
SLAVE
ADDRESS
S
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
A
C
K
A
C
K
13
A
C
K
N
O
A
C
K
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300 mils (L) (1)(2)
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
E1
6.10
eB
7.87
L
2.92
6.35
7.11
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
Doc. No. MD-3010 Rev. P
14
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
SOIC 8-Lead 150 mils (W)
(1)(2)
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
e
PIN # 1
IDENTIFICATION
NOM
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
TSSOP 8-Lead (V)
(1)(2)
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.90
e
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
1.05
0.75
8°
e
TOP VIEW
D
A2
A
A1
c
θ1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153
Doc. No. MD-3010 Rev. P
16
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
MSOP 8-Lead (Z)
(1)(2)
SYMBOL
MIN
NOM
MAX
A
E
E1
1.10
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
0.38
c
0.13
0.23
D
2.90
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
e
L
0.65 BSC
0.40
0.60
0.80
L1
0.95 REF
L2
0.25 BSC
θ
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
17
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
TDFN 8-Pad 3 x 3 mm (ZD4) (1)(2)
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
SIDE VIEW
TOP VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
A3
A1
0.23
0.30
0.37
D
2.90
3.00
3.10
D2
2.20
—
2.50
E
2.90
3.00
3.10
E2
1.40
—
1.80
e
BOTTOM VIEW
A
0.20 REF
b
L
D2
FRONT VIEW
0.65 TYP
0.20
0.30
0.40
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-229.
Doc. No. MD-3010 Rev. P
18
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1026, CAT1027
EXAMPLE OF ORDERING INFORMATION (1)
Prefix
Device # Suffix
CAT
1026
W
I
-30
–
Temperature Range
I = Industrial (-40ºC to 85ºC)
Company ID
Product
Number
1026: 2k
1027: 2k
Package
L: PDIP
W: SOIC
Y: TSSOP
Z: MSOP
ZD4: TDFN 3 x 3 mm (5)
Reset Threshold Voltage
-45: 4.50 V – 4.75 V
-42: 4.25 V – 4.50 V
-30: 3.00 V – 3.15 V
-28: 2.85 V – 3.00 V
-25: 2.55 V – 2.70 V
G
T3
Tape & Reel
T: Tape & Reel
3: 3,000/Reel
Lead Finish
Blank: Matte-Tin
G: NiPdAu
ORDERING INFORMATION
Orderable Part Number – CAT1026xx
CAT1026LI-45-G
CAT1026ZI-45-GT3
CAT1026LI-42-G
CAT1026ZI-42-GT3
CAT1026LI-30-G
CAT1026ZI-30-GT3
CAT1026LI-28-G
CAT1026ZI-28-GT3
CAT1026LI-25-G
CAT1026ZI-25-GT3
CAT1026WI-45-GT3
CAT1026ZD4I-45T3*
CAT1026WI-42-GT3
CAT1026ZD4I-42T3*
CAT1026WI-30-GT3
CAT1026ZD4I-30T3*
CAT1026WI-28-GT3
CAT1026ZD4I-28T3*
CAT1026WI-25-GT3
CAT1026ZD4I-25T3*
CAT1026YI-45-GT3
CAT1026YI-42-GT3
CAT1026YI-30-GT3
CAT1026YI-28-GT3
CAT1026YI-25-GT3
Orderable Part Number – CAT1027xx
CAT1027LI-45-G
CAT1027ZI-45-GT3
CAT1027LI-42-G
CAT1027ZI-42-GT3
CAT1027LI-30-G
CAT1027ZI-30-GT3
CAT1027LI-28-G
CAT1027ZI-28-GT3
CAT1027LI-25-G
CAT1027ZI-25-GT3
CAT1027WI-45-GT3
CAT1027ZD4I-45T3*
CAT1027WI-42-GT3
CAT1027ZD4I-42T3*
CAT1027WI-30-GT3
CAT1027ZD4I-30T3*
CAT1027WI-28-GT3
CAT1027ZD4I-28T3*
CAT1027WI-25-GT3
CAT1027ZD4I-25T3*
CAT1027YI-45-GT3
CAT1027YI-42-GT3
CAT1027YI-30-GT3
CAT1027YI-28-GT3
CAT1027YI-25-GT3
* Part number is not exactly the same as the “Example of Ordering Information” shown above. For part numbers marked with
one hyphen in the orderable part number, which is placed before the “Reset Threshold Voltage”.
* there is only
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT1026WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15 V, NiPdAu, Tape & Reel,
3,000/Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
(5) TDFN not available in NiPdAu (–G) version.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
19
Doc. No. MD-3010 Rev. P
CAT1026, CAT1027
REVISION HISTORY
Date
Rev.
Reason
Added Green Package logo. Updated DC Operating Characteristic notes. Updated
Reliability Characteristics notes
9/25/2003
F
11/07/2003
G
Eliminated Automotive temperature range. Updated Ordering Information with “Green”
package marking codes
4/12/2004
H
Eliminated data sheet designation. Updated Reel Ordering Information
11/01/2004
I
Changed SOIC package designators. Eliminated 8-pad TDFN (3 x 4.9 mm) package.
Added package outlines
11/04/2004
J
Update Pin Configuration
11/11/2004
K
Update Feature
Update Description
Update DC Operating Characteristic
Update AC Characteristics
02/02/2007
L
Update Example of Ordering Information
11/28/2007
M
Update Package Outline Drawings
Update Example of Ordering Information
Add “MD-“ to document number
7-Nov-08
N
Change logo and fine print to ON Semiconductor
05-Mar-09
O
Update Ordering Information (Remove 2,000/Reel)
14-Jul-09
P
Update Ordering Information table
ON Semiconductor and
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any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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Email: [email protected]
Doc. No. MD-3010, Rev. P
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Europe, Middle East and Africa Technical Support:
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20
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For additional information, please contact your local
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Characteristics subject to change without notice
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