CAT1320 D

CAT1320, CAT1321
Supervisory Circuits with
I2C Serial 32K CMOS
EEPROM
Description
The CAT1320 and CAT1321 are complete memory and supervisory
solutions for microcontroller−based systems. A 32 kbit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I2C bus.
The CAT1320 provides a precision VCC sense circuit and drives an
open drain output, RESET low whenever VCC falls below the reset
threshold voltage.
The CAT1321 provides a precision VCC sense circuit that drives an
open drain output, RESET high whenever VCC falls below the reset
threshold voltage.
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset options, interface to microcontrollers
and other ICs is simple. In addition, the RESET (CAT1320) pin can be
used as an input for push−button manual reset capability.
The CAT1320/21 memory features a 64−byte page. In addition,
hardware data protection is provided by a VCC sense circuit that
prevents writes to memory whenever VCC falls below the reset
threshold or until VCC reaches the reset threshold during power up.
Available packages include an 8−pin DIP, SOIC, TSSOP and
4.9 x 3 mm TDFN.
Features
• Precision Power Supply Voltage Monitor
•
•
•
•
•
•
•
•
5 V, 3.3 V and 3 V Systems
S +5.0 V (±5%, ±10%)
S +3.3 V (±5%, ±10%)
S +3.0 V (±10%)
Active Low Reset, CAT1320
Active High Reset, CAT1321
Valid Reset Guaranteed at VCC = 1 V
400 kHz I2C Bus
♦
•
•
•
•
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 5
1
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PDIP−8
CASE 646AA
TSSOP−8
CASE 948S
SOIC−8
CASE 751BD
TDFN−8
CASE 511AM
ORDERING INFORMATION
For Ordering Information details, see page 13.
3.0 V to 5.5 V Operation
Low Power CMOS Technology
64−Byte Page Write Buffer
1,000,000 Program/Erase Cycles
100 Year Data Retention
8−pin DIP, SOIC, TSSOP and TDFN Packages
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Publication Order Number:
CAT1320/D
CAT1320, CAT1321
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45
4.50
4.75
−42
4.25
4.50
−30
3.00
3.15
−28
2.85
3.00
−25
2.55
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
DOUT
ACK
VCC
VSS
SDA
WORDADDRESS
BU F F E R S
COLUMN
DECODERS
STA RT/ STOP
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SCL
SLAVE
ADDRESS
COMPARATORS
A0
RESET (CAT1320)
RESET (CAT1321)
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2
A1
A2
CAT1320, CAT1321
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TDFN Package 4.9 mm x 3 mm
(ZD2)
TSSOP (Y)
8 VCC
A0
1
7 RESET
A1
2
6 SCL
A2
3
5 SDA
VSS
VCC
8 VCC
A0 1
7 RESET
A1 2
6 SCL
A2 3
VSS 4
5 SDA
VSS 4
A0 1
8 VCC
A0 1
8
A1 2
7
RESET
A1 2
6
SCL
A2 3
A0 1
A1 2
CAT1320
A2 3
A2 3
VSS 4
CAT1321
5
SDA
CAT1320
CAT1321
VSS 4
8
VCC
7
RESET
6
SCL
4
5
SDA
A0
1
8
VCC
7
RESET
A1
2
7
RESET
6
SCL
A2
3
6
SCL
VSS 4
5
SDA
5
SDA
CAT1320
CAT1321
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTS
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL: SERIAL CLOCK
Serial clock input.
A0, A1, A2: DEVICE ADDRESS INPUTs
When hardwired, up to eight CAT1320/21 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
Table 2. PIN FUNCTION
Pin Name
RESET
Function
Active Low Reset Input/Output
(CAT1320)
VSS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
VCC
Active High Reset Output
(CAT1321)
Power Supply
Table 3. OPERATING TEMPERATURE RANGE
Industrial
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3
−40°C to 85°C
CAT1320, CAT1321
SPECIFICATIONS
Table 4. ABSOLUTE MAXIMUM RATINGS
Ratings
Units
Temperature Under Bias
Parameters
–40 to +85
°C
Storage Temperature
–65 to +105
°C
−0.5 to VCC + 2.0
V
−0.5 to +7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 seconds)
300
°C
Output Short Circuit Current (Note 1)
100
mA
Voltage on any Pin with Respect to Ground (Note 1)
VCC with Respect to Ground
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 5. D.C. OPERATING CHARACTERISTICS
VCC = +3.0 V to +5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ILI
Input Leakage Current
VIN = GND to VCC
−2
10
mA
ILO
Output Leakage Current
VIN = GND to VCC
−10
10
mA
ICC1
Power Supply Current (Write)
fSCL = 400 kHz
VCC = 5.5 V
3
mA
ICC2
Power Supply Current (Read)
fSCL = 400 kHz
VCC = 5.5 V
1
mA
ISB
Standby Current
VCC = 5.5 V
VIN = GND or VCC
40
mA
VIL (Note 3)
Input Low Voltage
−0.5
0.3 x VCC
V
VIH (Note 3)
Input High Voltage
0.7 x VCC
VCC + 0.5
V
VOL
Output Low Voltage
(SDA, RESET)
IOL = 3 mA
VCC = 3.0 V
0.4
V
VOH
Output High Voltage
(RESET)
IOH = −0.4 mA
VCC = 3.0 V
VCC − 0.75
VTH
Reset Threshold
CAT132x−45
(VCC = 5.0 V)
4.50
4.75
CAT132x−42
(VCC = 5.0 V)
4.25
4.50
CAT132x−30
(VCC = 3.3 V)
3.00
3.15
CAT132x−28
(VCC = 3.3 V)
2.85
3.00
CAT132x−25
(VCC = 3.0 V)
2.55
2.70
VRVALID (Note 2)
VRT (Note 2)
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
4
V
1.00
V
15
mV
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
3. VIL min and VIH max are reference values only and are not tested.
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V
CAT1320, CAT1321
Table 6. CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5 V
Test
Symbol
COUT (Note 1)
CIN (Note 1)
Test Conditions
Max
Units
Output Capacitance
VOUT = 0 V
8
pF
Input Capacitance
VIN = 0 V
6
pF
Max
Units
Table 7. AC CHARACTERISTICS
VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 2)
Parameter
Symbol
Min
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
tHIGH
Clock High Period
0.6
ms
ms
tR (Note 1)
SDA and SCL Rise Time
300
ns
tF (Note 1)
SDA and SCL Fall Time
300
ns
tHD; STA
Start Condition Hold Time
0.6
ms
tSU; STA
Start Condition Setup Time (for a Repeated Start)
0.6
ms
tHD; DAT
Data Input Hold Time
0
ns
ns
tSU; DAT
Data Input Setup Time
100
tSU; STO
Stop Condition Setup Time
0.6
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
50
ns
tBUF (Note 1)
Time the Bus must be Free Before a New Transmission Can Start
1.3
ms
tWC (Note 3)
Write Cycle Time (Byte or Page)
ms
900
5
ns
ms
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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CAT1320, CAT1321
Table 8. RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
Test Conditions
Min
Typ
Max
Units
Reset Timeout
Parameter
Note 2
130
200
270
ms
VTH to RESET output Delay
Note 3
5
ms
tGLITCH
VCC Glitch Reject Pulse Width
Notes 4 and 5
30
ns
MR Glitch
Manual Reset Glitch Immunity
Note 5
100
ns
MR Pulse Width
Note 5
5
Test Conditions
Min
tMRW
ms
Table 9. POWER−UP TIMING (Notes 5 and 6)
Symbol
Parameter
Typ
Max
Units
tPUR
Power−Up to Read Operation
270
ms
tPUW
Power−Up to Write Operation
270
ms
Table 10. AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Test Conditions
0.2 VCC to 0.8 VCC
Input Rise and Fall Times
10 ns
Input Reference Voltages
0.3 VCC , 0.7 VCC
Output Reference Voltages
0.5 VCC
Output Load
Current Source: IOL = 3 mA; CL = 100 pF
Table 11. RELIABILITY CHARACTERISTICS
Symbol
Reference Test Method
Min
Endurance
MIL−STD−883, Test Method 1033
1,000,000
Cycles/Byte
TDR (Note 5)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 5)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
Volts
JEDEC Standard 17
100
mA
NEND (Note 5)
ILTH (Notes 5 & 7)
1.
2.
3.
4.
5.
6.
7.
Parameter
Latch−Up
Max
Units
Test Conditions according to “AC Test Conditions” table.
Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
VCC Glitch Reference Voltage = VTHmin; Based on characterization data
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V.
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CAT1320, CAT1321
DEVICE OPERATON
Reset Controller Description
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
The CAT1320/21 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with opendrain
RESET/RESET outputs.
During power−up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200 ms (tPURST) after
reaching VTH. After the tPURST timeout interval, the device
will cease to drive the reset output. At this point the reset
output will be pulled up or down by their respective pull
up/down resistors.
During power−down, the RESET/RESET outputs will be
active when VCC falls below VTH. The RESET/RESET
output will be valid so long as VCC is > 1.0 V (VRVALID). The
device is designed to ignore the fast negative going VCC
transient pulses (glitches).
Reset output timing is shown in Figure 1.
Hardware Data Protection
The CAT1320/21 family has been designed to solve many
of the data corruption issues that have long been associated
with serial EEPROMs. Data corruption occurs when
incorrect data is stored in a memory location which is
assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output is active, in
progress communications to the EEPROM are aborted and
no new communications are allowed. In this condition an
internal write cycle to the memory can not be started, but an
in progress internal non−volatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5 ms) before VCC reaches the minimum value
of 2 V.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
tGLITCH
VTH
VRVALID
VCC
t PURST
t RPD
t PURST
RESET
RESET
Figure 1. RESET/RESET Output Timing
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t RPD
CAT1320, CAT1321
tMRW
RESET
(Input)
tPURST
RESET
(Output)
Figure 2. RESET as Manual Reset Input Operation and Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
SDA OUT
Figure 3. Bus Timing
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tBUF
CAT1320, CAT1321
EMBEDDED EEPROM OPERATON
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
The CAT1320 and CAT1321 feature a 32 kbit embedded
serial EEPROM that supports the I2C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1320/21 monitors the SDA
and SCL lines and will not respond until this condition is
met.
I2C Bus Protocol
Stop Condition
The features of the I2C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
After the Master sends a START condition and the slave
address byte, the CAT1320/21 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1320/21 then perform a Read or Write operation
depending on the R/W bit.
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Write Cycle Timing
ACKNOWLEDGE
When the CAT1320/21 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1320/21 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1320/21 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
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CAT1320, CAT1321
WRITE OPERATIONS
Byte Write
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1320/21
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
SDA
SCL
START BIT
STOP BIT
Figure 5. Start/Stop Timing
SCL FROM
MASTER
8
1
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Acknowledge Timing
Default Configuration
1
0
1
0
A2
A1
A0
R/W
Figure 7. Slave Address Bits
Page Write
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1320/21 in a single write cycle.
The CAT1320/21 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1320/21 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
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CAT1320, CAT1321
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
A
C
K
* = Don’t Care Bit
** * *
S
T
O
P
DATA
P
A
C
K
A
C
K
A
C
K
Figure 8. Byte Write Timing
S
BUS
T
ACTIVITY: A
MASTER R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
SDA LINE S
* = Don’t Care Bit
A
C
K
****
DATA
DATA n
S
T
O
P
DATA n+63
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 9. Page Write Timing
Acknowledge Polling
Read Operations
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1320/21 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
The READ operation for the CAT1320/21 is initiated in
the same manner as the write operation with one exception,
that R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
P
S
A
C
K
DATA
N
O
A
C
K
SCL
8
9
SDA8TH BIT
DATA OUT
NO ACK
Figure 10. Immediate Address Read Timing
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STOP
CAT1320, CAT1321
Immediate/Current Address Read
again, this time with the R/W bit set to one. The CAT1320
and CAT1321 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
The CAT1320 and CAT1321 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1320 and CAT1321 receives its
slave address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1320 and CAT1321 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1320 and
CAT1321 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1320 and
CAT1321 address bits so that the entire memory array can
be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1320 and CAT1321 acknowledges, the Master
device sends the START condition and the slave address
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
A
R
T
BYTE ADDRESS
A15–A8
A7–A0
SLAVE
ADDRESS
S
A
C
K
* = Don’t Care Bit
****
SLAVE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
N
O
A
C
K
A
C
K
A
C
K
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
Figure 12. Sequential Read Timing
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A
C
K
N
O
A
C
K
CAT1320, CAT1321
ORDERING INFORMATION
Orderable Part Numbers − CAT1320 Series
(See Notes 1 − 5)
Device
Reset Threshold
CAT1320LI−45−G
4.50 V − 4.75 V
CAT1320LI−42−G
4.25 V − 4.50 V
CAT1320LI−30−G
3.00 V − 3.15 V
CAT1320LI−28−G
2.85 V − 3.00 V
CAT1320LI−25−G
2.55 V − 2.70 V
CAT1320WI−45−GT3
4.50 V − 4.75 V
CAT1320WI−42−GT3
4.25 V − 4.50 V
CAT1320WI−30−GT3
3.00 V − 3.15 V
CAT1320WI−28−GT3
2.85 V − 3.00 V
CAT1320WI−25−GT3
2.55 V − 2.70 V
CAT1320YI−45−GT3
4.50 V − 4.75 V
CAT1320YI−42−GT3
4.25 V − 4.50 V
CAT1320YI−30−GT3
3.00 V − 3.15 V
CAT1320YI−28−GT3
2.85 V − 3.00 V
CAT1320YI−25−GT3
2.55 V − 2.70 V
CAT1320ZD2I45GT3
4.50 V − 4.75 V
CAT1320ZD2I42GT3
4.25 V − 4.50 V
CAT1320ZD2I30GT3
3.00 V − 3.15 V
CAT1320ZD2I28GT3
2.85 V − 3.00 V
CAT1320ZD2I25GT3
2.55 V − 2.70 V
Package
Shipping
PDIP
SOIC
3000 Tape & Reel
TSSOP
TDFN
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
13
CAT1320, CAT1321
Orderable Part Numbers − CAT1321 Series
(See Notes 1 − 5)
Device
Reset Threshold
CAT1321LI−45−G
4.50 V − 4.75 V
CAT1321LI−42−G
4.25 V − 4.50 V
CAT1321LI−30−G
3.00 V − 3.15 V
CAT1321LI−28−G
2.85 V − 3.00 V
CAT1321LI−25−G
2.55 V − 2.70 V
CAT1321WI−45−GT3
4.50 V − 4.75 V
CAT1321WI−42−GT3
4.25 V − 4.50 V
CAT1321WI−30−GT3
3.00 V − 3.15 V
CAT1321WI−28−GT3
2.85 V − 3.00 V
CAT1321WI−25−GT3
2.55 V − 2.70 V
CAT1321YI−45−GT3
4.50 V − 4.75 V
CAT1321YI−42−GT3
4.25 V − 4.50 V
CAT1321YI−30−GT3
3.00 V − 3.15 V
CAT1321YI−28−GT3
2.85 V − 3.00 V
CAT1321YI−25−GT3
2.55 V − 2.70 V
CAT1321ZD2I45GT3
4.50 V − 4.75 V
CAT1321ZD2I42GT3
4.25 V − 4.50 V
CAT1321ZD2I30GT3
3.00 V − 3.15 V
CAT1321ZD2I28GT3
2.85 V − 3.00 V
CAT1321ZD2I25GT3
2.55 V − 2.70 V
Package
Shipping
PDIP
SOIC
3000 Tape & Reel
TSSOP
TDFN
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
14
CAT1320, CAT1321
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
15
CAT1320, CAT1321
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
16
CAT1320, CAT1321
TDFN8, 3x4.9
CASE 511AM−01
ISSUE A
D
A
DETAIL A
DAP SIZE
2.6 x 3.3mm
E
E2
PIN #1
IDENTIFICATION
A1
PIN #1 IDENTIFICATION
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A
A1
b
0.25
0.30
0.35
2.90
3.00
3.10
D2
0.90
1.00
1.10
E
4.80
4.90
5.00
E2
0.90
1.00
1.10
e
b
L
0.65 TYP
0.50
0.60
A3
FRONT VIEW
0.20 REF
D
L
BOTTOM VIEW
e
0.70
DETAIL A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
http://onsemi.com
17
CAT1320, CAT1321
TSSOP−8
CASE 948S−01
ISSUE C
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
0.20 (0.008) T U
T U
B
−U−
1
J J1
4
V
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
K1
K
A
−V−
S
S
5
L
PIN 1
IDENT
M
DETAIL E
G
0.25 (0.010)
N
M
N
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
F
DETAIL E
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CAT1320/D