CAT15004 D

CAT15002, CAT15004
Voltage Supervisor with 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
FEATURES
DESCRIPTION
„ Precision Power Supply Voltage Monitor
The CAT15002/04 (see table below) are memory and
supervisory solutions for microcontroller based
systems. A CMOS serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together. Memory interface is via SPI
bus serial interface.
ƒ 5V, 3.3V, 3V & 2.5V systems
ƒ 7 threshold voltage options
„ Active High or Low Reset
ƒ Valid reset guaranteed at VCC = 1V
„ 10MHz SPI compatible
The CAT15002/04 provides a precision VCC sense
circuit with two reset output options: CMOS active low
output or CMOS active high. The RESET output is
active whenever VCC is below the reset threshold or
falls below the reset threshold voltage.
„ 16-byte page write buffer
„ Low power CMOS technology
„ 1,000,000 Program/Erase cycles
„ 100 year data retention
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
„ Industrial temperature range
„ RoHS-compliant 8-pin SOIC package
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC (W)
¯¯
CS
1
8 VCC
SO
2
7 RST/¯¯¯¯
RST
¯¯¯
WP
3
6 SCK
VSS
4
5 SI
MEMORY SIZE SELECTOR
Product
15002
15004
PIN FUNCTION
Memory density
2-Kbit
4-Kbit
THRESHOLD SUFFIX SELECTOR
Pin Name
Function
¯¯
CS
Chip Select
SO
Nominal Threshold
Voltage
Threshold Suffix
Designation
Serial Data Output
4.63V
L
¯¯¯
WP
Write Protect
4.38V
M
VSS
Ground
4.00V
J
SI
Serial Data Input
3.08V
T
SCK
Serial Clock Input
2.93V
S
¯¯¯¯
RST/RST
Reset Output
2.63V
R
VCC
Power Supply
2.32V
Z
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
BLOCK DIAGRAM
VCC
SO
SCK
SI
VOLTAGE
DETECTOR
EEPROM
CS
RST or RST
WP
VSS
(1)
ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
Ratings
Units
-65 to +150
°C
-0.5 to +6.5
V
RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Min
Units
(4)
Endurance
1,000,000
Program/ Erase Cycles
100
Years
NEND
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V unless otherwise specified.
Symbol Parameter
Min.
Limits
Typ.
Max.
Test Condition
Units
ICC
Supply Current
2
Read or Write at 10MHz, SO open
mA
ISB
Standby Current
12
25
10
20
¯¯ = VCC
VCC < 5.5V; VIN = VSS or VCC, CS
¯¯ = VCC
VCC < 3.6V; VIN = VSS or VCC, CS
μA
IL
I/O Pin Leakage
2
Pin at GND or VCC
μA
VIL
Input Low Voltage
-0.5
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.4
VCC - 0.8
VCC ≥ 2.5V, IOL = 3.0mA
V
VCC ≥ 2.5V, IOH = -1.6mA
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. MD-1126 Rev. B
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
A.C. CHARACTERISTICS (MEMORY)(1)
VCC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Min.
Max.
Units
fSCK
Clock Frequency
DC
10
MHz
tSU
Data Setup Time
20
ns
tH
Data Hold Time
20
ns
tWH
SCK High Time
40
ns
tWL
SCK Low Time
40
ns
tLZ
¯¯¯¯¯ to Output Low Z
HOLD
25
ns
tRI(2)
tFI(2)
Input Rise Time
2
µs
Input Fall Time
2
µs
tHD
¯¯¯¯¯
HOLD Setup Time
0
tCD
¯¯¯¯¯
HOLD Hold Time
10
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
20
ns
tHZ
¯¯¯¯¯ to Output High Z
HOLD
25
ns
tCS
¯¯ High Time
CS
15
ns
tCSS
¯¯ Setup Time
CS
15
ns
tCSH
¯¯ Hold Time
CS
15
ns
tWPS
¯¯¯
WP Setup Time
10
ns
tWPH
¯¯¯
WP Hold Time
10
ns
tWC(4)
tPU(2) (3)
ns
ns
40
0
ns
ns
Write Cycle Time
5
ms
Power-up to Ready Mode
1
ms
Notes:
(1)
Test conditions according to “A.C. Test Conditions” table.
(2)
Tested initially and after a design or process change that affects this parameter.
(3)
tPU is the delay between the time VCC is stable and the device is ready to accept commands.
¯¯ after a valid write sequence to the end of the internal write cycle.
tWC is the time from the rising edge of CS
(4)
A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 10ns
Input Levels
0.3 VCC to 0.7 VCC
Timing Reference Levels
0.5 VCC
Output Load
Current Source: IOL max/ IOH max; CL = 50pF
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = -40°C to +85°C unless otherwise noted. Typical values at TA = +25°C and VCC = 5V for
L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version.
Symbol
VTH
Parameter
Reset Threshold Voltage
Threshold
L
M
J
T
S
R
Z
Symbol Parameter
Conditions
Min
Typ
Max
TA = +25°C
TA = -40°C to +85°C
4.56
4.50
4.63
4.70
4.75
TA = +25°C
4.31
4.38
4.45
TA = -40°C to +85°C
4.25
TA = +25°C
3.93
TA = -40°C to +85°C
3.89
TA = +25°C
3.04
TA = -40°C to +85°C
3.00
TA = +25°C
2.89
TA = -40°C to +85°C
2.85
TA = +25°C
2.59
TA = -40°C to +85°C
2.55
TA = +25°C
2.28
TA = -40°C to +85°C
2.25
Conditions
Min
Reset Threshold Tempco
tRPD
tPURST
VOL
VOH
VCC to Reset Delay
(2)
Reset Active Timeout Period
¯¯¯¯¯¯ Output Voltage Low
RESET
(Push-pull, active LOW,
CAT150xx9)
¯¯¯¯¯¯ Output Voltage High
RESET
(Push-pull, active LOW,
CAT150xx9)
RESET Output Voltage Low
VOL
(Push-pull, active HIGH,
CAT150xx1)
RESET Output Voltage High
VOH
(Push-pull, active HIGH,
CAT150xx1)
VCC = VTH to (VTH -100mV)
TA = -40°C to +85°C
140
4.50
4.00
4.06
4.10
3.08
3.11
3.15
2.93
3.00
2.63
2.66
2.70
2.32
2.35
2.38
Typ(1)
Max
ppm/°C
20
µs
240
460
VCC = VTH min, ISINK = 3.2mA
J/L/M
0.4
VCC > 1.0V, ISINK = 50µA
0.3
VCC = VTH max, ISOURCE = -800µA
J/L/M
VCC - 1.5
ms
V
V
VCC > VTH max, ISINK = 1.2mA
R/S/T/Z
0.3
VCC > VTH max, ISINK = 3.2mA
J/L/M
0.4
1.8V < VCC ≤ VTH min,
ISOURCE = -150µA
Units
30
0.3
0.8VCC
V
2.96
VCC = VTH min, ISINK = 1.2mA
R/S/T/Z
VCC = VTH max, ISOURCE = -500µA
R/S/T/Z
Units
V
0.8VCC
V
Notes:
(1)
(2)
Production testing done at TA = +25ºC; limits over temperature guaranteed by design only.
RESET output for the CAT150xx9; RESET output for the CAT150xx1.
Doc. No. MD-1126 Rev. B
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
PIN DESCRIPTION
DEVICE OPERATION
¯¯¯¯¯¯: Reset output is available in two
RESET/RESET
versions: CMOS Active Low (CAT150xx9) and CMOS
Active High (CAT150xx1). Both versions are push-pull
outputs for high efficiency.
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
The CAT15002/04 products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9
and HIGH for the CAT150xx1 when the power supply
voltage falls below the threshold trip voltage and
remains asserted for at least 140ms (tPURST) after the
power supply voltage has risen above the threshold.
Reset output timing is shown in Figure 1.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT15002/04.
The CAT15002/04 devices protect µPs against brown-out
failure. Short duration VCC transients of 4µsec or less and
100mV amplitude typically do not generate a Reset pulse.
¯¯ : The chip select input pin is used to enable/disable
CS
¯¯ is high, the SO output is
the CAT15002/04. When CS
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT15002/04 must be preceded by a high to low
transition and concluded with a low to high transition of
¯¯ input.
the CS
¯¯¯:
WP The write protect input pin will allow all write
operations to the device when held high. When ¯¯¯
WP
pin is tied low all write operations are inhibited.
VTH
VCC
VRVALID
t PURST
t RPD
t PURST
t RPD
RESE T
CAT150xx9
RESE T
CAT150xx1
Figure 1. RESET Output Timing
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
TRANSIENT DURATION [µs]
Figure 2 shows the maximum pulse duration of
negative-going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH - VCC), the
maximum pulse duration decreases. In this test, the
VCC starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (VTH - VCC).
EMBEDDED EEPROM DESCRIPTION
The CAT15002/04 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT15002/04 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT15002/04, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
TAMB = 25ºC
¯¯ input pin, the
After a high to low transition on the CS
CAT15002/04 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication
protocol follows the timing from Figure 3.
CAT150xxZ
CAT150xxM
Table 1: Instruction Set
Instruction
RESET OVERDRIVE V TH - VCC [mV]
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 x011
Read Data from Memory
WRITE
0000 x010
Write Data to Memory
Note:
x = 0 for CAT15002,
x = A8 for CAT15004
Figure 3. Synchronous Data Timing
tCS
V IH
CS
VIL
SCK
tCSH
tCSS
VIH
tWL
tWH
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
SO
VOH
HI-Z
tHO
tDIS
HI-Z
VOL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The ¯¯¯¯
RDY (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
Table 2. Status Register
7
6
1
5
1
1
4
3
1
BP1
2
BP0
1
0
WEL
¯¯¯¯
RDY
Table 3. Block Protection Bits
Status Register Bits
BP1
BP0
0
0
0
1
1
0
1
1
Array Address Protected
Protection
None
No Protection
15002: C0-FF
Quarter Array Protection
15004: 180-1FF
15002: 80-FF
Half Array Protection
15004: 100-1FF
15002: 00-FF
Full Array Protection
15004: 000-1FF
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
WRITE OPERATIONS
¯¯ input high after the WREN instruction, as
take the CS
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 4. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The CAT15002/04 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1
bits from the status register.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15002/04. Care must be taken to
Figure 4. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. WRDI Timing
CS
SCK
SI
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, an 8-bit
address and data as shown in Figure 6 (for the
CAT15004, bit 3 of the Write instruciton opcode
contains address bit A8). Internal programming will
¯¯ transition. During an
start after the low to high CS
internal write cycle, all commands, except for RDSR
(Read Status Register) will be ignored. The ¯¯¯¯
RDY bit
will indicate if the internal write cycle is in progress
¯¯¯¯ high), or the the device is ready to accept
(RDY
¯¯¯¯ low).
commands (RDY
Page Write
After sending the first data byte to the CAT15002/04,
the host may continue sending data, up to a total of 32
bytes, according to timing shown in Figure 7. After
each data byte, the lower order address bits are
automatically incremented, while the higher order
address bits (page address) remain unchanged. If
during this process the end of page is exceeded, then
loading will “roll over” to the first byte in the page, thus
possibly overwriting previoualy loaded data. Following
completion of the write cycle, the CAT15002/04 is
automatically returned to the write disable state.
Figure 6. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
21
22
23
SCK
BYTE ADDRESS
OPCODE
SI
0
0
0
0
0X*
0
1
DATA IN
A0 D7 D6 D5 D4 D3 D2 D1 D0
A7
0
HIGH IMPEDANCE
SO
Notes:
* X = 0 for CAT15002; X = A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
Figure 7. Page WRITE Timing
CS
0
1
2
3
4
5
6
7
8
13
14
15 16-23 24-31
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
SCK
SI
0
0
0
0
0
X*
DATA IN
BYTE ADDRESS
OPCODE
0
SO
1
0
A7
A0
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
Notes:
* X = 0 for CAT15002; X = A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 8.
Only bits 2 and 3 can be written using the WRSR
command.
Write Protection
¯¯¯) pin can be used to disable all
The Write Protect (WP
write operations when held low. ¯¯¯
WP going low while
¯¯ is still low will interrupt a write to the
CS
CAT15002/04. If the internal write cycle has already
been initiated, ¯¯¯
WP going low will have no effect on any
write operation. The ¯¯¯
WP input timing is shown in
Figure 9.
Figure 8. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
DATA IN
0
0
3
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 9. ¯¯¯
WP Timing
t WPS
t WPH
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1126 Rev. B
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
READ OPERATIONS
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address, and
the read cycle can be continued indefinitely. The read
¯¯ high.
operation is terminated by taking CS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by an 8-bit address (for the
CAT15008, bit 3 of the Read instruction opcode
contains address bit A8).
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT15002/04 will shift out the contents
of the status register on the SO pin (Figure 11). The
status register may be read at any time, including
during an internal write cycle.
After receiving the last address bit, the CAT15002/04
will respond by shifting out data on the SO pin (as
shown in Figure 10). Sequentially stored data can be
read out by simply continuing to run the clock. The
internal address pointer is automatically incremented
to the next higher address as data is shifted out. After
Figure 10. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SCK
BYTE ADDRESS
OPCODE
0
SI
0
0
0
X*
0
0
1
1
A7 A6 A5
A4
A3
A2
A1 A0
DATA OUT
HIGH IMPEDANCE
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Notes:
* Please check the instruction set table for address
X = 0 for CAT15002; X=A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
Figure 11. RDSR Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
6
5
11
12
13
14
2
1
SCK
OPCODE
SI
0
0
0
0
0
DATA OUT
SO
HIGH IMPEDANCE
7
4
3
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
PACKAGE OUTLINE DRAWING
SOIC 8-Lead 150 mil (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
A1
A
b
C
D
E
E1
e
h
L
q1
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
1.27 BSC
0.25
0.40
0°
0.50
1.27
8°
Notes:
(1)
All dimensions are in millimeters.
(2)
Complies with JEDEC specification MS-012 dimensions.
Doc. No. MD-1126 Rev. B
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
PACKAGE MARKING
8-LEAD SOIC
150XXZWI
○
CSI
XX
Z
I
YY
WW
A
4
4YYWWA
=
=
=
=
=
=
=
=
Catalyst Semiconductor, Inc.
Device Code (see Marking Code table below)
Supervisory Output Code (see Marking Code table below)
Temperature Range
Production Year
Production Week
Product Revision
Lead Finish NiPdAu
Device Marking Codes
XX
15002
02
15004
04
Supervisory Marking Codes
Z
output active low
9
output active high
1
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-1126 Rev. B
CAT15002, CAT15004
EXAMPLE OF ORDERING INFORMATION
Prefix
CAT
Device # Suffix
15002
9
S
W
I
-
G
T3
Lead Finish
G: NiPdAu
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Product Type with
Memory Density
15002: 2-Kb EEPROM
15004: 4-Kb EEPROM
Tape & Reel
T: Tape & Reel
3: 3000 units / Reel
Package
W: SOIC
Reset Threshold Voltage
L: 4.50V – 4.75V
M: 4.25V – 4.50V
J: 3.89V – 4.10V
T: 3.00V – 3.15V
S: 2.85V – 3.00V
R: 2.55V – 2.70V
Z: 2.25V – 2.38V
Supervisor Output Type
9: CMOS Active Low
1: CMOS Active High
Notes:
(1)
All packages are RoHS-compliant (Lead-free, Halogen-free).
(2)
The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3)
The device used in the above example is a CAT150029SWI-GT3 (2-Kb EEPROM, with Active Low CMOS Reset output, with a reset threshold
between 2.85V - 3.00V, in SOIC package, Industrial Temperature, NiPdAu, Tape and Reel.
(4)
For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
Doc. No. MD-1126 Rev. B
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT15002, CAT15004
REVISION HISTORY
Date
Rev.
Description
16-Jan-07
A
Initial Issue
10-Nov-08
B
Change logo and fine print to ON Semiconductor
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Characteristics subject to change without notice
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Doc. No. MD-1126 Rev. B
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