CAT15008 D

CAT15008, CAT15016
Voltage Supervisor with
8-Kb and 16-Kb SPI Serial
CMOS EEPROM
Description
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The CAT15008/16 (see table below) are memory and supervisory
solutions for microcontroller based systems. A CMOS serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together. Memory interface is via SPI bus
serial interface.
The CAT15008/16 provides a precision VCC sense circuit with two
reset output options: CMOS active low output or CMOS active high.
The RESET output is active whenever VCC is below the reset
threshold or falls below the reset threshold voltage.
The power supply monitor and reset circuit protect system
controllers during power up/down and against brownout conditions.
Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
240 ms after the supply voltage exceeds the reset threshold level.
SOIC−8
CASE 751BD
PIN CONFIGURATION
SOIC (W)
CS
1
8
VCC
SO
2
7
RST/RST
WP
3
6
SCK
VSS
4
5
SI
Features
• Precision Power Supply Voltage Monitor
PIN FUNCTION
5 V, 3.3 V, 3 V and 2.5 V Systems
♦ 7 Threshold Voltage Options
Active High or Low Reset
♦ Valid Reset Guaranteed at VCC = 1 V
10 MHz SPI Compatible
32−Byte Page Write Buffer
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
RoHS−Compliant 8−Pin SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
♦
•
•
•
•
•
•
•
•
•
Pin Name
Threshold Suffix
Designation
4.63 V
L
4.38 V
M
4.00 V
J
3.08 V
T
2.93 V
S
2.63 V
R
2.32 V
Z
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 3
CS
Chip Select
SO
Serial Data Output
WP
Write Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
RST/RST
Reset Output
VCC
Power Supply
MEMORY SIZE SELECTOR
Product
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage
Function
Memory Density
15008
8−Kbit
15016
16−Kbit
ORDERING INFORMATION
For Ordering Information details, see page 12.
1
Publication Order Number:
CAT15008/D
CAT15008, CAT15016
BLOCK DIAGRAM
VCC
SO
SCK
SI
VOLTAGE
DETECTOR
EEPROM
CS
RST or RST
WP
VSS
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
NEND (Note 3)
TDR
Parameter
Endurance
Data Retention
Min
Units
1,000,000
Program/ Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
VCC = +2.5 V to +5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Supply Current
Read or Write at 10 MHz, SO open
ISB
Standby Current
VCC < 5.5 V; VIN = VSS or VCC, CS = VCC
VCC < 3.6 V; VIN = VSS or VCC, CS = VCC
IL
I/O Pin Leakage
VIL
Input Low Voltage
Min
Pin at GND or VCC
VIH
Input High Voltage
VOL
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
VOH
Output High Voltage
VCC ≥ 2.5 V, IOH = −1.6 mA
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2
Typ
Max
Units
2
mA
12
25
mA
10
20
2
mA
−0.5
0.3 VCC
V
0.7 VCC
VCC + 0.5
V
0.4
V
VCC − 0.8
V
CAT15008, CAT15016
Table 4. A.C. CHARACTERISTICS (MEMORY) (Note 1)
VCC = 2.5 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.
Parameter
Symbol
Max
Units
10
MHz
fSCK
Clock Frequency
DC
tSU
Data Setup Time
20
ns
tH
Data Hold Time
20
ns
tWH
SCK High Time
40
ns
tWL
SCK Low Time
40
tLZ
HOLD to Output Low Z
25
ns
tRI (Note 2)
Input Rise Time
2
ms
tFI (Note 2)
Input Fall Time
2
ms
ns
tHD
HOLD Setup Time
0
ns
tCD
HOLD Hold Time
10
ns
tV
1.
2.
3.
4.
Min
Output Valid from Clock Low
40
0
ns
tHO
Output Hold Time
ns
tDIS
Output Disable Time
20
ns
tHZ
HOLD to Output High Z
25
ns
tCS
CS High Time
15
ns
tCSS
CS Setup Time
15
ns
tCSH
CS Hold Time
15
ns
tWPS
WP Setup Time
10
ns
tWPH
WP Hold Time
10
ns
tWC (Note 4)
Write Cycle Time
5
ms
tPU
(Notes 2 & 3)
Power−up to Ready Mode
1
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
tPU is the delay between the time VCC is stable and the device is ready to accept commands.
tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 5. A.C. TEST CONDITIONS
Parameter
Test Conditions
Input Rise and Fall Times
Input Levels
≤10 ns
0.3 VCC to 0.7 VCC
Timing Reference Levels
Output Load
0.5 VCC
Current Source: IOL max/ IOH max; CL = 50 pF
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3
CAT15008, CAT15016
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = −40°C to +85°C unless otherwise noted. Typical values at TA = +25°C and VCC = 5 V for L/M/J versions,
VCC = 3.3 V for T/S versions, VCC = 3 V for R version and VCC = 2.5 V for Z version.
Symbol
Parameter
Threshold
VTH
Reset Threshold
Voltage
L
M
J
T
S
R
Z
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TA = +25°C
4.56
4.63
4.70
V
TA = −40°C to +85°C
4.50
TA = +25°C
4.31
TA = −40°C to +85°C
4.25
TA = +25°C
3.93
TA = −40°C to +85°C
3.89
TA = +25°C
3.04
TA = −40°C to +85°C
3.00
TA = +25°C
2.89
TA = −40°C to +85°C
2.85
TA = +25°C
2.59
TA = −40°C to +85°C
2.55
TA = +25°C
2.28
TA = −40°C to +85°C
2.25
Conditions
Min
Reset Threshold Tempco
tRPD
VCC to Reset Delay (Note 2)
VCC = VTH to (VTH −100 mV)
tPURST
Reset Active Timeout Period
TA = −40°C to +85°C
VOL
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT150xx9)
VOH
VOL
VOH
140
4.75
4.38
4.45
4.50
4.00
4.06
4.10
3.08
3.11
3.15
2.93
2.96
3.00
2.63
2.66
2.70
2.32
2.35
2.38
Typ
(Note 1)
Max
Units
30
ppm/°C
20
ms
240
460
ms
VCC = VTH min, ISINK = 1.2 mA
R/S/T/Z
0.3
V
VCC = VTH min, ISINK = 3.2 mA
J/L/M
0.4
VCC > 1.0 V, ISINK = 50 mA
0.3
RESET Output Voltage High
(Push−pull, Active LOW,
CAT150xx9)
VCC = VTH max, ISOURCE = −500 mA
R/S/T/Z
0.8 VCC
VCC = VTH max, ISOURCE = −800 mA
J/L/M
VCC − 1.5
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT150xx1)
VCC > VTH max, ISINK = 1.2 mA
R/S/T/Z
0.3
VCC > VTH max, ISINK = 3.2 mA
J/L/M
0.4
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT150xx1)
1.8 V < VCC ≤ VTH min,
ISOURCE = −150 mA
1. Production testing done at TA = +25°C; limits over temperature guaranteed by design only.
2. RESET output for the CAT150xx9; RESET output for the CAT150xx1.
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4
0.8 VCC
V
V
V
CAT15008, CAT15016
PIN DESCRIPTION
CS: The chip select input pin is used to enable/disable the
CAT15008/16. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAT15008/16
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
RESET/RESET: Reset output is available in two versions:
CMOS Active Low (CAT150xx9) and CMOS Active High
(CAT150xx1). Both versions are push−pull outputs for high
efficiency.
SI: The serial data input pin accepts op−codes, addresses and
data. In SPI modes (0,0) and (1,1) input data is latched on the
rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT15008/16.
DEVICE OPERATION
The CAT15008/16 products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
RESET CONTROLLER DESCRIPTION
TRANSIENT DURATION [μs]
The reset signal is asserted LOW for the CAT150xx9 and
HIGH for the CAT150xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (tPURST) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT15008/16 devices protect mPs against brown−out
failure. Short duration VCC transients of 4 msec or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH − VCC), the maximum
pulse duration decreases. In this test, the VCC starts from an
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (VTH − VCC).
TAMB = 25ºC
CAT150xxZ
CAT150xxM
RESET OVERDRIVE VTH - VCC [mV]
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
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CAT15008, CAT15016
VTH
VCC
VRVALID
t PURST
t RPD
t RPD
t PURST
RESET
CAT150xx9
RESET
CAT150xx1
Figure 2. RESET Output Timing
EMBEDDED EEPROM DESCRIPTION
8−bit combinations. The communication protocol follows
the timing from Figure 3.
The CAT15008/16 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
Reading data stored in the CAT15008/16 is accomplished
by simply providing the READ command and an address.
Writing to the CAT15008/16, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT15008/16 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
Table 7. INSTRUCTION SET
Instruction
Opcode
WREN
0000 0110
Enable Write Operations
Operation
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
tCS
V IH
CS
VIL
SCK
tCSH
tCSS
VIH
tWL
tWH
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
SO
VOH
HI-Z
tHO
tDIS
HI-Z
VOL
Note: Dashed Line = mode (1, 1)−−−−−
Figure 3. Synchronous Data Timing
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CAT15008, CAT15016
STATUS REGISTER
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1
during an internal write cycle, and reset to 0 when the device
is ready to accept commands. For the host, this bit is read
only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
Table 8. STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
0
0
0
BP1
BP0
WEL
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
None
0
1
15008: 0300−03FF
Array Address Protected
Protection
No Protection
Quarter Array Protection
15016: 0600−07FF
1
0
Half Array Protection
15008: 0200−03FF
15016: 0400−07FF
1
1
Full Array Protection
15008: 0000−03FF
15016: 0000−07FF
Table 10. WRITE PROTECT ENABLE OPERATION
WPEN
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
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CAT15008, CAT15016
WRITE OPERATIONS
The CAT15008/16 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
instruction to the CAT15008/16. Care must be taken to take
the CS input high after the WREN instruction, as otherwise
the Write Enable Latch will not be properly set. WREN
timing is illustrated in Figure 4. The WREN instruction must
be sent prior any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
CS
SCK
0
SI
0
0
0
1
0
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)−−−−−
Figure 4. WREN Timing
CS
SCK
SI
0
0
0
0
1
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)−−−−−
0
Figure 5. WRDI Timing
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 6. Only 10 significant address
bits are used by the CAT15008 and 11 by the CAT15016. The
rest are don’t care bits, as shown in Table 11. Internal
programming will start after the low to high CS transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress
(RDY high), or the device is ready to accept commands
(RDY low).
After sending the first data byte to the CAT15008/16, the
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 7. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT15008/16
is automatically returned to the write disable state.
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CAT15008, CAT15016
Table 11. BYTE ADDRESS
Device
Address Significant Bits
Address Don’t Care Bits
# Address Clock Pulse
CAT15008
A9 − A0
A15 − A10
16
CAT15016
A10 − A0
A15 − A11
16
CS
0
1
2
3
4
5
6
7
8
21
22 23
24
25
26 27
28
29
30
31
SCK
BYTE ADDRESS*
OPCODE
SI
0
0
0
0
0
0
1
0
DATA IN
AN A0 D7D6D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
SO
Notes: * Please check the Byte Address Table (Table 11)
Dashed Line = mode (1, 1)−−−−−
Figure 6. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SCK
SI
0
0
0
0
0
DATA IN
BYTE ADDRESS*
OPCODE
0
1
0
AN A0
Data
Byte 1
HIGH IMPEDANCE
SO
Notes: * Please check the Byte Address Table (Table 11)
Dashed Line = mode (1, 1)−−−−−
Figure 7. Page WRITE Timing
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Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
CAT15008, CAT15016
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 8. Only bits
2, 3 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 9.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
DATA IN
0
0
1
7
6
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)−−−−−
Figure 8. WRSR Timing
t WPS
t WPH
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1)−−−−−
Figure 9. WP Timing
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5
4
3
CAT15008, CAT15016
READ OPERATIONS
Read from Memory Array
lowest memory address, and the read cycle can be continued
indefinitely. The read operation is terminated by taking CS
high.
To read from memory, the host sends a READ instruction
followed by an 16−bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the CAT15008/16 will
respond by shifting out data on the SO pin (as shown in
Figure 10). Sequentially stored data can be read out by
simply continuing to run the clock. The internal address
pointer is automatically incremented to the next higher
address as data is shifted out. After reaching the highest
memory address, the address counter “rolls over” to the
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT15008/16 will shift out the contents of the status register
on the SO pin (Figure 11). The status register may be read
at any time, including during an internal write cycle.
CS
0
1
2
3
4
5
6
7
8
1
AN
9
10
20
21
22
23
24
25
26
27
28
29
30
SCK
OPCODE
SI
0
0
0
0
0
BYTE ADDRESS*
0
1
A0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Notes: * Please check the Byte Address Table (Table 11)
Dashed Line = mode (1, 1)−−−−−
Figure 10. READ Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
6
5
11
12
13
14
2
1
SCK
OPCODE
SI
SO
0
0
0
0
0
DATA OUT
HIGH IMPEDANCE
7
MSB
Note: Dashed Line = mode (1, 1)−−−−−
Figure 11. RDSR Timing
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4
3
0
CAT15008, CAT15016
ORDERING INFORMATION
Orderable Part Numbers − CAT150xx Series
(See Notes 1 − 4)
Device
Reset Threshold
Voltage
Package−Pins
Shipping
CAT150089SWI−GT3
2.85 to 3.00 V
3000 Tape & Reel
CAT150089SWI−G
2.85 to 3.00 V
100 Tube
CAT150161MWI−GT3
4.25 to 4.50 V
CAT150169MWI−GT3
4.25 to 4.50 V
CAT150169SWI−GT3
2.85 to 3.00 V
SOIC−8
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu pre−plated (PPF) lead frames.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
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CAT15008, CAT15016
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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