CAT24C128 D

CAT24C128
128 kb I2C CMOS Serial
EEPROM
Description
The CAT24C128 is a 128 kb Serial CMOS EEPROM, internally
organized as 16,384 words of 8 bits each.
It features a 64−byte page write buffer and supports both the
Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C
protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
•
•
•
•
•
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
64−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
8−lead PDIP, SOIC, TSSOP, MSOP and UDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant**
VCC
PDIP−8
L SUFFIX
CASE 646AA
UDFN−8
HU4 SUFFIX
CASE 517AZ
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
W SUFFIX
CASE 751BD
MSOP−8
Z SUFFIX
CASE 846AD
UDFN−8***
HU3 SUFFIX
CASE 517AX
PIN CONFIGURATION
A0
1
VCC
A1
WP
A2
SCL
VSS
SDA
PDIP (L), SOIC (W), TSSOP (Y), MSOP
(Z), UDFN (HU3***), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
*** Not recommended for new design.
SCL
CAT24C128
A2, A1, A0
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PIN FUNCTION
SDA
Pin
Name†
A0, A1, A2
WP
VSS
Figure 1. Functional Symbol
*Available for New Product (Rev. C)
** For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Function
Device Address Inputs
SDA
Serial Data Input/Output
SCL
Serial Clock Input
WP
Write Protect Input
VCC
Power Supply
VSS
Ground
†The exposed pad for the TDFN/UDFN packages can
be left floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 15
1
Publication Order Number:
CAT24C128/D
CAT24C128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Notes 3, 4)
TDR
Endurance
Min
Units
1,000,000
Program / Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C
4. The new product revision (C) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS − Mature Product (Rev B)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
1
mA
ICCW
Write Current
Write, fSCL = 400 kHz
3
mA
TA = −40°C to +85°C
1
mA
TA = −40°C to +125°C
2
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
ISB
IL
Standby Current
All I/O Pins at GND or VCC
I/O Pin Leakage
Pin at GND or VCC
mA
VIL
Input Low Voltage
−0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Table 4. PIN IMPEDANCE CHARACTERISTICS − Mature Product (Rev B)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Conditions
Max
Units
CIN (Note 5)
SDA I/O Pin Capacitance
Parameter
VIN = 0 V
8
pF
CIN (Note 5)
Input Capacitance (other pins)
VIN = 0 V
6
pF
IWP (Note 6)
WP Input Current
VIN < VIH
200
mA
VIN > VIH
1
mA
Symbol
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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CAT24C128
Table 5. D.C. OPERATING CHARACTERISTICS − New Product (Rev C) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
ICCR
Read Current
ICCW
Write Current
ISB
IL
Standby Current
I/O Pin Leakage
Test Conditions
Min
Max
Units
1
mA
3
mA
TA = −40°C to +85°C
2
mA
TA = −40°C to +125°C
5
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
Read, fSCL = 400 kHz/1 MHz
All I/O Pins at GND or VCC
Pin at GND or VCC
mA
VIL1
Input Low Voltage
2.5 V ≤ VCC ≤ 5.5 V
−0.5
0.3 VCC
V
VIL2
Input Low Voltage
1.8 V ≤ VCC < 2.5 V
−0.5
0.25 VCC
V
VIH1
Input High Voltage
2.5 V ≤ VCC ≤ 5.5 V
0.7 VCC
VCC + 0.5
V
0.75 VCC
VIH2
Input High Voltage
1.8 V ≤ VCC < 2.5 V
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Table 6. PIN IMPEDANCE CHARACTERISTICS − New Product (Rev C) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 8)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 8)
Input Capacitance (other pins)
VIN = 0 V
6
pF
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
75
mA
VIN < VIH, VCC = 3.3 V
50
VIN < VIH, VCC = 1.8 V
25
VIN > VIH
2
IWP, IA (Note 9)
7. The product Rev C is identified by letter “C” or dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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CAT24C128
Table 7. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 10)
Standard
VCC = 1.8 V − 5.5 V
Parameter
Symbol
FSCL
tHD:STA
Min
Max
Clock Frequency
START Condition Hold Time
Fast
VCC = 1.8 V − 5.5 V
Min
100
Max
Fast−Plus (Note 13)
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Min
400
Max
Units
1,000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
tHIGH
High Period of SCL Clock
4
0.6
0.40
ms
4.7
0.6
0.25
ms
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
0
ms
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 11)
SDA and SCL Rise Time
1,000
300
100
ns
tF (Note 11)
SDA and SCL Fall Time
300
300
100
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between
STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti (Note 11)
4
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
100
0.9
100
Noise Pulse Filtered at SCL
and SDA Inputs
100
0.40
50
100
ms
ns
50
ns
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
tPU
(Notes 11, 12)
Write Cycle Time
5
5
Power-up to Ready Mode
1
1
0.1
5
ms
1
ms
10. Test conditions according to “A.C. Test Conditions” table.
11. Tested initially and after a design or process change that affects this parameter.
12. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
13. Fast−Plus (1 MHz) speed class available for new product revision “C”. The die revision “C” is identified by letter “C” or a dedicated marking
code on top of the package.
Table 8. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
v 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24C128
Power−On Reset (POR)
The CAT24C128 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
The CAT24C128 will power up into Standby mode after
VCC exceeds the POR trigger level and will power down into
Reset mode when VCC drops below the POR trigger level.
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
When not driven, these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A2, A1 and A0, select one of 8 possible Slave
devices and must match the state of the external address pins.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed.
Functional Description
The CAT24C128 supports the Inter−Integrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C128 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A0, A1,
and A2.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull−up
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CAT24C128
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
DEVICE ADDRESS
1
0
1
A2
0
A1
A0
R/W
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY (RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
SDA OUT
Figure 5. Bus Timing
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tBUF
CAT24C128
Write Operations
latched and the address count automatically increments to
and then wraps−around at the page boundary. Previously
loaded data can thus be overwritten by new data. What is
eventually written to memory reflects the latest Page Write
Buffer contents. Only data loaded within the most recent
Page Write sequence will be written to memory.
Byte Write
Upon receiving a Slave address with the R/W bit set to ‘0’,
the CAT24C128 will interpret the next two bytes as address
bytes. These bytes are used to initialize the internal address
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to
a location within a 64 byte page. A byte following the
address bytes will be interpreted as data. The data will be
loaded into the Page Write Buffer and will eventually be
written to memory at the address specified by the 14 active
address bits provided earlier. The CAT24C128 will
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a
STOP condition (Figure 6). During the internal Write cycle
(tWR), the SDA output will be tri−stated and additional Read
or Write requests will be ignored (Figure 7).
Acknowledge Polling
The ready/busy status of the CAT24C128 can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C128. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C128 will not acknowledge the data byte
and the Write request will be rejected.
Page Write
By continuing to load data into the Page Write Buffer after
the 1st data byte and before issuing the STOP condition, up
to 64 bytes can be written simultaneously during one
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will
continue from the beginning of page, i.e. the page address is
BUS ACTIVITY:
MASTER
S
T
A
R
T
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are FFh.
ADDRESS
BYTE
a7−a0
ADDRESS
BYTE
a13−a8
SLAVE
ADDRESS
S
S
T
O
P
DATA
BYTE
P
* *
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
ACK
Byte n
tWR
STOP
CONDITION
Figure 7. Write Cycle Timing
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START
CONDITION
ADDRESS
CAT24C128
BUS ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
a13−a8
SLAVE
ADDRESS
S
DATA
BYTE
n
ADDRESS
BYTE
a7−a0
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
P
* *
A
C
K
SLAVE
* = Don’t Care Bit
P v 63
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
9
a7
a0
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
Read Operations
with data, the Master instead follows up with an Immediate
Read sequence, then the CAT24C128 will use the 14 active
address bits to initialize the internal address counter and will
shift out data residing at the corresponding location. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 11), the
CAT24C128 returns to Standby mode.
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C128 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C128 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C128
returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1st
data byte, then the CAT24C128 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
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CAT24C128
BUS ACTIVITY:
MASTER
S
T
A
R
T
N
O
A
C
K
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
SCL
DATA
BYTE
8
SDA
S
T
O
P
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
a13−a8
SLAVE
ADDRESS
S
S
T
A
R
T
ADDRESS
BYTE
a7−a0
S
* *
A
C
K
SLAVE
N
O
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
O
P
P
A
C
K
A
C
K
DATA
BYTE
* = Don’t Care Bit
Figure 11. Selective Read Sequence
N
O
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
S
T
O
P
P
SLAVE
A
C
K
DATA
BYTE
n
A
C
K
DATA
BYTE
n+1
A
C
K
DATA
BYTE
n+2
Figure 12. Sequential Read Sequence
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A
C
K
DATA
BYTE
n+x
CAT24C128
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT24C128
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT24C128
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
1.20
A
E1
E
MAX
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.20
0.65 BSC
e
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT24C128
PACKAGE DIMENSIONS
UDFN8, 2x3
CASE 517AX−01
ISSUE O
D
A
DETAIL A
DAP SIZE 1.3 x 1.8
E
PIN #1
IDENTIFICATION
E2
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SYMBOL
MIN
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
b
L
0.127 REF
K
b
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.50
1.60
1.70
E
2.90
3.00
3.10
E2
0.10
0.20
0.30
e
0.50 TYP
K
0.10 REF
L
BOTTOM VIEW
SIDE VIEW
0.30
0.35
e
DETAIL A
A3
A
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
A1
FRONT VIEW
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13
CAT24C128
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.10
A
E
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
0.38
0.23
c
0.13
D
2.90
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
E1
0.65 BSC
e
L
0.60
0.40
L1
0.25 BSC
L2
θ
0.80
0.95 REF
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
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14
CAT24C128
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
D
b
A
e
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SYMBOL
MIN
SIDE VIEW
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
0.127 REF
b
0.20
0.25
0.30
D
1.95
2.00
2.05
D2
1.35
1.40
1.45
E
2.95
3.00
3.05
E2
1.25
1.30
1.35
e
L
BOTTOM VIEW
DETAIL A
0.065 REF
A3 A
FRONT VIEW
0.50 REF
0.25
0.30
0.35
A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
0.0 - 0.05
DETAIL A
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15
0.065 REF
Copper Exposed
CAT24C128
ORDERING INFORMATION (Notes 14 thru 19)
Device Order Number
Specific
Device
Marking*
Package
Type
Temperature Range
Lead Finish
Shipping
CAT24C128LI−G
24128C
PDIP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
CAT24C128LE−G
24128C
PDIP−8
E = Extended
(−40°C to +125°C)
NiPdAu
Tube, 50 Units / Tube
CAT24C128WI−GT3
24128C
SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128WE−GT3
24128C
SOIC−8,
JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128YI−GT3
C28C
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128YE−GT3
C28C
TSSOP−8
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128HU4IGT3
(Note 19)
C7U
UDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128HU4EGT3
(Note 19)
C7U
UDFN−8
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128HU3IGT3**
BB
UDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128ZI−GT3
C7
MSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT24C128ZE−GT3
C7
MSOP−8
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
14. All packages are RoHS−compliant (Lead−free, Halogen−free).
15. The standard lead finish is NiPdAu.
16. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
17. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
18. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
19. There are NO hyphens in the orderable part numbers.
*Marking for New Product (Rev C).
** Not recommended for new designs.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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16
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT24C128/D
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