CAT24C21 D

CAT24C21
1 kb Dual Mode Serial
EEPROM for VESAt
“Plug-and-Play”
Description
The CAT24C21 is a 1 kb Serial CMOS EEPROM internally
organized as 128 words of 8 bits each. The device complies with the
Video Electronics Standard Association’s (VESA™), Display Data
Channel (DDC™) standards for “Plug−and−Play” monitors. The
“transmit−only” mode (DDC1™) is controlled by the VCLK clock
input and the “bi−directional” mode (DDC2™) is controlled by the
SCL clock input, with both modes sharing a common SDA
input/output (I/O). The transmit−only mode is a read−only mode,
while the bi−directional mode is a read and write mode following the
I2C protocol. In write mode the CAT24C21 features a 16−byte page
write buffer. The device is available in 8−lead DIP, SOIC, TSSOP,
MSOP and TDFN packages.
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SOIC−8
W SUFFIX
CASE 751BD
PDIP−8
L SUFFIX
CASE 646AA
Features
•
•
•
•
•
•
•
•
•
•
•
DDC1t/DDC2t Interface Compliant for Monitor Identification
400 kHz I2C Bus Compatible
2.5 to 5.5 Volt Operation
16−byte Page Write Buffer
Hardware Write Protect
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−lead DIP, SOIC, TSSOP, MSOP or TDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
NC
SDA
VCLK
TSSOP−8
Y SUFFIX
CASE 948AL
1
VCC
NC
VCLK
NC
SCL
VSS
SDA
PDIP (L), SOIC (W), TSSOP (Y),
TDFN (ZD4), MSOP (Z)
PIN FUNCTION
NC
SCL
MSOP−8
Z SUFFIX
CASE 846AD
PIN CONFIGURATION
Pin Name
VCC
CAT24C21
TDFN−8
ZD4 SUFFIX
CASE 511AL
Function
No Connect
SDA
Serial Data / Address
SCL
Serial Clock (bi−directional mode)
VCLK
Serial Clock (transmit−only mode)
VCC
Power Supply
VSS
Ground
VSS
ORDERING INFORMATION
Figure 1. Functional Symbol
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 16
1
Publication Order Number:
CAT24C21/D
CAT24C21
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
–55 to +125
°C
Storage Temperature
–65 to +150
°C
–2.0 to +VCC +2.0
V
Voltage on Any Pin with Respect to Ground (Note 1)
VCC with Respect to Ground
–2.0 to +7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 secs)
300
°C
Output Short Circuit Current (Note 2)
100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Units
Endurance
MIL−STD−883, Test Method 1033
1,000,000
Program/Erase Cycles
TDR (Note 3)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 3)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
Volts
JEDEC Standard 17
100
mA
NEND (Notes 3 and 4)
ILTH (Notes 3 and 5)
Latch−up
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Page Mode, VCC = 5 V, 25°C
5. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.)
Max
Units
fSCL = 400 kHz
2
mA
Standby Current
VIN = GND or VCC
1
mA
ILI
Input Leakage Current
VIN = GND to VCC
10
mA
ILO
Output Leakage Current
VOUT = GND to VCC
10
mA
Symbol
ICC
ISB (Note 6)
Parameter
Test Conditions
Power Supply Current
Min
VIL
Input Low Voltage
−1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
VCC = 3.0 V, IOL = 3 mA
0.4
V
VCC ≥ 2.7 V
0.8
V
VIL
Input Low Voltage (VCLK)
VIH
Input High Voltage (VCLK)
2.0
V
6. Maximum standby current (ISB) = 10 mA for the Extended Automotive temperature range.
Table 4. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V)
Symbol
Parameter
Conditions
Min
Max
Units
CI/O (Note 7)
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
CIN (Note 7)
Input Capacitance (VCLK, SCL)
VIN = 0 V
6
pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
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2
CAT24C21
Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.)
Parameter
Symbol
Min
Max
Units
0.5
ms
TRANSMIT−ONLY MODE
TVAA
Output valid from VCLK
TVHIGH
VCLK high
0.6
TVLOW
VCLK low
1.3
TVHZ
Mode transition
TVPU
Transmit−only power−up
ms
ms
0.5
0
ms
ns
READ & WRITE CYCLE LIMITS
FSCL
TI (Note 8)
tAA
tBUF (Note 8)
Clock Frequency
400
kHz
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
1
ms
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
1.2
ms
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time
0.6
ms
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
50
ns
tHD:STA
tR (Note 8)
SDA and SCL Rise Time
0.3
ms
tF (Note 8)
SDA and SCL Fall Time
300
ns
tSU:STO
tDH
Stop Condition Setup Time
0.6
ms
Data Out Hold Time
100
ns
POWER−UP TIMING (Note 8 and 9)
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
5
ms
WRITE CYCLE LIMITS
tWR
Write Cycle Time
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Functional Description
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are
disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
The CAT24C21 has two modes of operation: the
transmit−only mode and the bi−directional mode. There is a
separate 2−wire protocol to support each mode, each having
a separate clock input (VCLK and SCL respectively) and
both modes sharing a common bi−directional data line
(SDA). The CAT24C21 enters the transmit−only mode upon
power up and begins outputting data on the SDA pin with
each clock signal on the VCLK pin. The device will remain
in the transmit−only mode until there is a valid HIGH to
LOW transition on the SCL pin, when it will switch to the
bi−directional mode (Figure 2). Once in the bi−directional
mode, the only way to return to the transmit−only mode is
by powering down the device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit−only mode. When held low,
in bi−directional mode, it will inhibit write operations.
Pin Description
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the bi−directional
mode.
The SDA bi−directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire−ORed with other open
drain or open collector outputs.
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CAT24C21
Transmit−Only Mode: (DDC1)
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th ‘don’t care’ bit which will be in
the high impedance state (Figure 4). The CAT24C21 will
continuously sequence through the entire memory array as
long as VCLK is present and no falling edges on SCL are
detected. When the maximum address (7FH) is reached,
addressing will wrap around to the zero location (00H) and
transmitting will continue. The bi−directional mode clock
(SCL) pin must be held high for the device to remain in the
transmit−only mode.
Upon power−up, the CAT24C21 will output valid data
only after it has been initialized. During initialization, data
will not be available until after the first nine clocks are sent
to the device (Figure 3). The starting address for the
transmit−only mode can be determined during initialization.
If the SDA pin is high during the first eight clocks, the
starting address will be 7FH. If the SDA pin is low during the
first eight clocks, the starting address will be 00H. During
the ninth clock, SDA will be in the high impedance state.
Transmit−Only Mode
Bi−Directional Mode
SCL
TVHZ
SDA
VCLK
Figure 2. Mode Transition
SCL
SDA at high impedance for 9 clock cycles
Bit8
SDA
Bit7
Bit6
Bit5
Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
TVPU
11
12
13
14
15
TVAA
Figure 3. Device Initialization for Transmit−only Mode
SCL must remain high for transmit−only mode
SCL
SDA
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
(MSB)
VCLK
TVHIGH
TVLOW
Figure 4. Transmit−Only Mode
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4
Bit1
Bit8
Don’t
(LSB) Care
Bit7
CAT24C21
Bi−Directional Mode (DDC2)
Acknowledge
The following defines the features of the I2C bus protocol
in bi−directional mode (Figure 5):
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
When in the bi−directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
After a successful data transfer, each receiving device is
required to generate an acknowledge (ACK). The
acknowledging device pulls down the SDA line during the
ninth clock cycle, signaling that it has received the 8 bits of
data (Figure 8).
The CAT24C21 responds with an ACK after receiving a
START condition and its slave address. If the device has
been selected along with a write operation, it responds with
an ACK after receiving each 8−bit byte.
When the CAT24C21 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an ACK. Once it receives this ACK, the CAT24C21 will
continue to transmit data. If no ACK is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
START Condition
The START condition (Figure 7) precedes all commands
to the device, and is defined as a HIGH to LOW transition
of SDA when SCL is HIGH. The CAT24C21 monitors the
SDA and SCL lines and will not respond until this condition
is met.
Write Operations
VCLK must be held high in order to program the device.
This applies to byte write and page write operation. Once the
device is in its self−timed program cycle, VCLK can go low
and not affect programming.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Byte Write
In the Byte Write mode (Figure 10), the Master device
sends the START condition and the slave address
information (with the R/W bit set to zero) to the Slave
device. After the Slave generates an ACK, the Master sends
the byte address that is to be written into the address pointer
of the CAT24C21. After receiving another ACK from the
Slave, the Master device transmits the data byte to be written
into the addressed memory location. The CAT24C21
acknowledges once more and the Master generates the
STOP condition, at which time the device begins its internal
programming cycle to nonvolatile memory (Figure 6).
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 1010
for the CAT24C21 (see Figure 9). The next three significant
bits are “don’t care”. The last bit of the slave address
specifies whether a Read or Write operation is to be
performed. When this bit is set to 1, a Read operation is
selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24C21 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT24C21 then
performs a Read or Write operation depending on the state
of the R/W bit.
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tDH
tAA
SDA OUT
Figure 5. Bus Timing
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tBUF
CAT24C21
SCL
8th Bit
SDA
ACK
Byte n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 6. Write Cycle Timing
Page Write
programming cycle begins. At this point all received data is
written to the CAT24C21 in a single write cycle.
The CAT24C21 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page Write
operation (Figure 11) is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the initial word is transmitted, the Master is allowed to send
up to fifteen additional bytes. After each byte has been
transmitted the CAT24C21 will respond with an ACK, and
internally increment the low order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than sixteen bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT24C21 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the CAT24C21 is still busy with the write
operation, no ACK will be returned. If the CAT24C21 has
completed the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
SDA
SCL
START Bit
STOP Bit
Figure 7. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 8. Acknowledge Timing
1
0
1
0
X
X
X
Figure 9. Slave Address Bits
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R/W
CAT24C21
Write Protection
(Figure 13). The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to read.
After the CAT24C21 acknowledges the word address, the
Master device resends the START condition and the slave
address, this time with the R/W bit set to one. The
CAT24C21 then responds with its ACK and sends the 8−bit
byte requested. The master device does not send an ACK but
will generate a STOP condition.
When the VCLK pin is connected to GND and the
CAT24C21 is in the bi−directional mode, the entire memory
is protected and becomes “read only”.
Read Operations
The READ operation for the CAT24C21 is initiated in the
same manner as the write operation with the one exception
that the R/W bit is set to a one. Three different READ
operations are possible: Immediate Address READ,
Selective READ and Sequential READ.
Sequential Read
The Sequential READ operation (Figure 14) can be
initiated by either the Immediate Address READ or the
Selective READ operation. After the CAT24C21 sends the
first 8−bit byte, the Master responds with an ACK, which
tells the Slave that more data is being requested. The
CAT24C21 will continue to output an 8−bit byte for each
ACK sent by the Master. The entire memory content can thus
be read out sequentially. If the end of memory is reached in
the process, then addressing will ‘wrap−around’ to the
beginning of memory. Data output will stop when the Master
fails to acknowledge and sends a STOP condition.
Immediate Address Read
The CAT24C21’s address counter contains the address of
the last byte accessed, incremented by one. In other words,
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N + 1 (Figure 12). If N = 127, then the counter will
‘wrap around’ to address 0 and continue to clock out data.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ operation
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
* * *
SDA LINE
S
T
O
P
DATA
P
*
A
C
K
nMAX = 7FH
P = 15 for CAT24WC21
* = Don−t care
BUS ACTIVITY:
MASTER
BYTE
ADDRESS
A
C
K
A
C
K
Figure 10. Byte Write Timing
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
O
P
DATA n+P
P
*
* * *
A
C
K
A
C
K
A
C
K
Figure 11. Page Write Timing
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A
C
K
A
C
K
CAT24C21
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
S
S
T
O
P
SLAVE
ADDRESS
P
* * *
A
C
K
SCL
8
DATA
N
O
A
C
K
9
8th Bit
SDA
DATA OUT
NO ACK
STOP
Figure 12. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
A
R
T
BYTE
ADDRESS (n)
* * *
*
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
P
A
C
K
A
C
K
DATA n
Figure 13. Selective Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
N
O
A
C
K
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
Figure 14. Sequential Read Timing
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A
C
K
N
O
A
C
K
CAT24C21
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT24C21
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT24C21
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
e
0.20
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT24C21
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.10
A
E
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
0.38
0.23
c
0.13
D
2.90
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
E1
0.65 BSC
e
L
0.60
0.40
L1
0.25 BSC
L2
θ
0.80
0.95 REF
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
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CAT24C21
PACKAGE DIMENSIONS
TDFN8, 3x3
CASE 511AL−01
ISSUE A
D
A
e
b
L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
SIDE VIEW
TOP VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
BOTTOM VIEW
0.20 REF
b
0.23
0.30
0.37
D
2.90
3.00
3.10
D2
2.20
−−−
2.50
E
2.90
3.00
3.10
E2
1.40
−−−
1.80
e
L
D2
A
A3
A1
0.65 TYP
0.20
0.30
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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FRONT VIEW
CAT24C21
Example of Ordering Information
Prefix
Device #
CAT
24C21
Suffix
Y
I
−G
T3
Temperature Range
Lead Finish
Tape & Reel (Note 15)
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C) (Note 14)
G: NiPdAu
Blank: Matte−Tin
Company ID
Product Number
24C21
T: Tape & Reel
3: 3,000 / Reel
Package
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
Z: MSOP (Note 12)
ZD4: TDFN (3 x 3 mm)
10. All packages are RoHS-compliant (Lead-free, Halogen-free).
11. The device used in the above example is a CAT24C21YI−GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel).
12. For availability, please contact your nearest ON Semiconductor Sales office.
13. For additional package options, please contact your nearest ON Semiconductor Sales office.
14. Extended Temperature available upon request.
15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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14
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CAT24C21/D
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