CAT64LC40 D

CAT64LC40
4 kb SPI Serial EEPROM
Description
The CAT64LC40 is a 4 kb Serial EEPROM which is configured as
256 registers by 16 bits. Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT64LC40 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. It is designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is available in 8−pin
DIP, SOIC and TSSOP packages.
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Features
•
•
•
•
•
•
•
•
•
•
•
•
SPI Bus Compatible
Low Power CMOS Technology
2.5 V to 6.0 V Operation
Self−Timed Write Cycle with Auto−Clear
Hardware Reset Pin
Hardware and Software Write Protection
Commercial, Industrial and Automotive Temperature Ranges
Power−up Inadvertent Write Protection
RDY/BSY Pin for End−of−Write Indication
1,000,000 Program/Erase Cycles
100 Year Data Retention
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
VCC
PDIP−8
P, L SUFFIX
CASE 646AA
SOIC−8
J, W, S, V SUFFIX
CASE 751BD
TSSOP−8
U, Y SUFFIX
CASE 948AL
GND
PIN FUNCTION
Pin Name
MEMORY ARRAY
256 x 16
ADDRESS
DECODER
DATA
REGISTER
OUTPUT
BUFFER
DI
RESET
CS
SK
CLOCK
GENERATOR
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
+2.5 V to +6.0 V Power Supply
GND
Ground
RESET
MODE DECODE
LOGIC
RDY/BUSY
DO
Function
Reset
Ready/BUSY Status
ORDERING INFORMATION
RDY/BUSY
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Figure 1. Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 4
1
Publication Order Number:
CAT64LC40/D
CAT64LC40
PIN CONNECTIONS
CS
SK
DI
DO
1
8
2
3
7
6
RDY/BUSY
RESET
4
5
GND
VCC
RDY/BUSY
1
8
RESET
VCC
2
3
7
6
GND
DO
4
5
DI
CS
SK
PDIP−8 (P, L)
CS
SK
DI
DO
1
8
DI
2
3
7
6
VCC
RDY/BUSY
RESET
DO
4
5
GND
8
7
6
5
VCC
RDY/BUSY
RESET
GND
TSSOP−8 (U, Y)
SOIC−8 (J, W)
CS
SK
1
2
3
4
SOIC−8 (S, V)
Table 1. ABSOLUTE MAXIMUM RATINGS
Ratings
Unit
Temperature Under Bias
Parameters
−55 to +125
°C
Storage Temperature
−65 to +150
°C
−2.0 to +VCC +2.0
V
−2.0 to +7.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 secs)
300
°C
Output Short Circuit Current (Note 2)
100
mA
Voltage on any Pin with Respect to Ground (Note 1)
VCC with Respect to Ground
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
NEND (Note 3)
Parameter
Min
Endurance
Max
Units
1,000,000
Cycles/Byte
TDR (Note 3)
Data Retention
100
Years
VZAP (Note 3)
ESD Susceptibility
2000
V
Latch−Up
100
mA
ILTH (Notes 3 and 4)
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V.
Table 3. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 6.0 V)
Symbol
Test
Conditions
Max
Units
CI/O (Note 5)
Input/Output Capacitance (DO, RDY/BSY)
VI/O = 0 V
8
pF
CIN (Note 5)
Input Capacitance (CS, SK, DI, RESET)
VIN = 0 V
6
pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT64LC40
Table 4. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Limits
Parameter
Symbol
ICC
ICCP
ISB (Note 6)
Test Conditions
Min
Typ
Max
Units
Operating Current
2.5 V
fSK = 250 kHz
0.4
mA
EWEN, EWDS, READ
6.0 V
fSK = 1 MHz
1
mA
Program Current
2.5 V
2
mA
6.0 V
3
mA
3
mA
VIN = GND to VCC
2
mA
VOUT = GND to VCC
10
mA
Standby Current
VIN = GND or VCC
CS = VCC
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Low Level Input Voltage, DI
−0.1
VCC x 0.3
V
VIH
High Level Input Voltage, DI
VCC x 0.7
VCC + 0.5
V
VIL
Low Level Input Voltage, CS, SK, RESET
−0.1
VCC x 0.2
V
VIH
High Level Input Voltage, CS, SK, RESET
VCC x 0.8
VCC + 0.5
V
VOH (Note 6)
VOL (Note 6)
High Level Output Voltage
Low Level Output Voltage
2.5 V
IOH = −10 mA
VCC − 0.3
V
6.0 V
IOH = −10 mA
VCC − 0.3
V
IOH = −400 mA
2.4
V
2.5 V
IOL = 10 mA
0.4
V
6.0 V
IOL = 2.1 mA
0.4
V
Max
Units
6. VOH and VOL spec applies to READY/BUSY pin also.
Table 5. A.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Limits
Min
Parameter
Symbol
Typ
tCSS
CS Setup Time
100
ns
tCSH
CS Hold Time
100
ns
tDIS
DI Setup Time
200
ns
tDIH
DI Hold Time
200
ns
tPD1
Output Delay to 1
300
ns
tPD0
Output Delay to 0
300
ns
Output Delay to High Impedance
500
ns
tHZ (Note 7)
tCSMIN
Minimum CS High Time
tSKHI
Minimum SK High Time
tSKLOW
Minimum SK Low Time
tSV
Output Delay to Status Valid
fSK
Maximum Clock Frequency
tRESS
250
ns
2.5 V
1000
ns
4.5 V − 6.0 V
400
2.5 V
1000
4.5 V − 6.0 V
400
ns
500
2.5 V
250
4.5 V − 6.0 V
1000
Reset to CS Setup Time
ns
kHz
0
ns
tRESMIN
Minimum RESET High Time
250
ns
tRESH
RESET to READY Hold Time
0
ns
100
ns
tRC
Write Recovery
7. This parameter is sampled but not 100% tested.
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CAT64LC40
Table 6. POWER−UP TIMING (Notes 8 and 9)
Parameter
Symbol
Min
Max
Units
tPUR
Power−Up to Read Operation
10
ms
tPUW
Power−Up to Program Operation
1
ms
Max
Units
2.5 V
10
ms
4.5 V − 6.0 V
5
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. WRITE CYCLE LIMITS
Symbol
Parameter
tWR
Min
Program Cycle Time
Table 8. INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 − D0
Write
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 − D0
Write Enable
10100011
XXXXXXXX
Write Disable
10100000
XXXXXXXX
[Write All Locations] (Note 10)
10100001
XXXXXXXX
10. (Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications.
VCC x 0.8
VCC x 0.7
INPUT PULSE LEVELS
REFERENCE POINTS
VCC x 0.3
VCC x 0.2
Figure 2. AC Testing Input/Output Waveform (Notes 11, 12 and 13) (CL = 100 pF)
11. Input Rise and Fall Times (10% to 90%) < 10 ns.
12. Input Pulse Levels = VCC x 0.2 and VCC x 0.8.
13. Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
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4
D15 − D0
CAT64LC40
Device Operation
The CAT64LC40 is a 4 kb nonvolatile memory intended
for use with all standard controllers. The CAT64LC40 is
organized in a 256 x 16 format. All instructions are based on
an 8−bit format. There are four 16−bit instructions: READ,
WRITE, EWEN, and EWDS. The CAT64LC40 operates on
a single power supply ranging from 2.5 V to 6.0 V and it has
an on−chip voltage generator to provide the high voltage
needed during a programming operation. Instructions,
addresses and data to be written are clocked into the DI pin
on the rising edge of the SK clock. The DO pin is normally
in a high impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4−bit start sequence, 1010, a 4−bit op code and an 8−bit
address field or dummy bits. For a WRITE operation, a
16−bit data field is also required following the 8−bit address
field.
RESET
tRESS
tSKLOW
tSKHI
SK
tDIS
tDIH
DI
tCSS
tCSH
tCSMIN
CS
tPD0, tPD1
tSV
tHZ
DO
tRESH
tRC
tSV
RDY/BUSY
Figure 3. Synchronous Data Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO
RDY/BUSY
D15 D14
HIGH
Figure 4. Read Instruction Timing
*Please check the instruction set table for address
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5
D1 D0
CAT64LC40
Write
The CAT64LC40 requires an active LOW CS in order to
be selected. Each instruction must be preceded by a
HIGH−to−LOW transition of CS before the input of the
4−bit start sequence. Prior to the 4−bit start sequence (1010),
the device will ignore inputs of all other logical sequence.
After receiving a WRITE op code, address and data, the
device goes into the AUTO−Clear cycle and then the
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one tSV after the rising edge of the 32nd clock
(the last data bit) and will stay LOW until the write cycle is
complete. Then it will output a logical “1” until the next
WRITE cycle. The RDY/BSY output is not affected by the
input of CS.
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one tPD after the
falling edge of the 16th clock (the last bit of the address
field). The READ operation is not affected by the RESET
input.
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
RDY/BUSY
Figure 5. Write Instruction Timing
*Please check instruction set table for address.
RESET
LOW
SK
CS
WRITE INSTRUCTION
NEXT INSTRUCTION
DI
DO
RDY/BUSY
HIGH
Figure 6. Ready/BUSY Status Instruction Timing
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CAT64LC40
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
NOTE: Data may be corrupted if a RESET occurs while the
device is BUSY. If the reset occurs before the BUSY period,
no writing will be initiated. However, if RESET occurs after
the BUSY period, new data will have been written over the
old data.
An alternative to get RDY/BSY status is from the DO pin.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed a
WRITE cycle, the DO pin will output a logical “1” when the
device is deselected. The rising edge of the first “1” input on
the DI pin will reset DO back to the high impedance state
again.
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
tWR
RDY/BUSY
*Please check instruction set table for address.
Figure 7. RESET During BUSY Instruction Timing
RESET
SK
CS
DI
DO
RDY/BUSY
1
0
1
0
0
0
1
1
HIGH−Z
HIGH
Figure 8. EWEN Instruction Timing
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CAT64LC40
Reset
Erase/Write Enable and Disable
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High−Z
condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and will
display READY status on the RDY/BSY pin and on the DO
pin if CS is low.
The RESET input affects only the WRITE and
WRITEALL operations. It does not reset any other
operations such as READ, EWEN and EWDS.
The CAT64LC40 powers up in the erase/write disabled
state. After power−up or while the device is in an erase/write
disabled state, any write operation must be preceded by an
execution of the EWEN instruction. Once enabled, the
device will stay enabled until an EWDS has been executed
or a power−down has occurred. The EWDS is used to
prevent any inadvertent over−writing of the data. The
EWEN and EWDS instructions have no affect on the READ
operation and are not affected by the RESET input.
RESET
SK
CS
DI
DO
RDY/BUSY
1
0
1
0
0
0
0
0
HIGH−Z
HIGH
Figure 9. EWDS Instruction Timing
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CAT64LC40
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT64LC40
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT64LC40
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
e
0.20
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT64LC40
Example of Ordering Information
Prefix
Device #
Suffix
CAT
64LC40
V
Company ID
Product Number
64LC40
−G
I
T3
Temperature Range
Tape & Reel (Note 18)
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C)*
T3: 3,000 / Tape & Reel
Package
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Lead Finish
G: NiPdAu
Blank: Matte−Tin
*−40°C to +125°C is available upon request.
ORDERING INFORMATION
Orderable Part Number
(for Pb−Free Devices)
CAT64LC40LI−GT3
CAT64LC40VI−GT3
CAT64LC40WI−GT3
CAT64LC40YI−GT3
14. All packages are RoHS−compliant (Lead−free, Halogen−free).
15. The standard lead finish is NiPdAu.
16. The device used in the above example is a 64LC40VI−GT3 (SOIC, Industrial Temperature, Tape & Reel).
17. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
18. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
CAT64LC40/D
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