CAT93C46R D

CAT93C46R
1 kb Microwire Serial
EEPROM
Description
The CAT93C46R is a 1 kb CMOS Serial EEPROM device which is
organized as either 64 registers of 16 bits or 128 registers of 8 bits, as
determined by the state of the ORG pin. The CAT93C46R features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
In contrast to the CAT93C46, the CAT93C46R features an internal
instruction clock counter which provides improved noise immunity
for Write/Erase commands.
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 4 MHz @ 5 V, 2 MHz @ 1.8 V
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
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PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8**
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
CS
SK
DI
DO
VCC
NC
ORG
GND
1
PDIP (L), SOIC (V),
TSSOP (Y), TDFN (VP2)**
(Top View)
** Not recommended for new designs
VCC
PIN FUNCTION
Pin Name
ORG
CS
SK
CAT93C46R
DO
DI
GND
Figure 1. Functional Symbol
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
Power Supply
GND
Ground
ORG
Memory Organization
NC
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Function
CS
No Connection
Note: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 9
1
Publication Order Number:
CAT93C46R/D
CAT93C46R
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Units
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Note 3)
TDR
Endurance
Min
Units
1,000,000
Program / Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, TA = 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply Current (Write)
fSK = 1 MHz
VCC = 5.0 V
1
mA
ICC2
Power Supply Current (Read)
fSK = 1 MHz
VCC = 5.0 V
500
mA
ISB1
Power Supply Current (Standby) (x8 Mode)
CS = 0 V
ORG = GND
10
mA
ISB2
Power Supply Current (Standby) (x16 Mode)
CS = 0 V
ORG = Float or VCC
10
mA
VIN = 0 V to VCC
2
mA
VOUT = 0 V to VCC,
CS = 0 V
2
mA
ILI
Input Leakage Current
ILO
Output Leakage Current (Including ORG pin)
VIL1
Input Low Voltage
4.5 V v VCC < 5.5 V
−0.1
0.8
V
VIH1
Input High Voltage
4.5 V v VCC < 5.5 V
2
VCC + 1
V
VIL2
Input Low Voltage
1.8 V v VCC < 4.5 V
0
VCC x 0.2
V
VCC x 0.7
VCC + 1
V
0.4
V
VIH2
Input High Voltage
1.8 V v VCC < 4.5 V
VOL1
Output Low Voltage
4.5 V v VCC < 5.5 V
IOL = 2.1 mA
VOH1
Output High Voltage
4.5 V v VCC < 5.5 V
IOH = −400 mA
VOL2
Output Low Voltage
1.8 V v VCC < 4.5 V
IOL = 1 mA
VOH2
Output High Voltage
1.8 V v VCC < 4.5 V
IOH = −100 mA
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2
2.4
V
0.2
VCC − 0.2
V
V
CAT93C46R
Table 4. PIN CAPACITANCE
Symbol
COUT (Note 4)
CIN (Note 4)
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Min
Typ
Max
Units
VOUT = 0 V
5
pF
VIN = 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (Note 5)
Parameter
Symbol
VCC = 1.8 V − 5.5 V
VCC = 4.5 V − 5.5 V
Min
Min
Max
Max
Units
tCSS
CS Setup Time
50
50
ns
tCSH
CS Hold Time
0
0
ns
tDIS
DI Setup Time
100
50
ns
tDIH
DI Hold Time
100
50
ns
tPD1
Output Delay to 1
0.25
tPD0
Output Delay to 0
0.25
0.1
ms
Output Delay to High−Z
100
100
ns
5
5
ms
tHZ (Note 6)
tEW
Program/Erase Pulse Width
0.1
ms
tCSMIN
Minimum CS Low Time
0.25
0.1
ms
tSKHI
Minimum SK High Time
0.25
0.1
ms
tSKLOW
Minimum SK Low Time
0.25
0.1
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
0.25
DC
2
DC
0.1
ms
4
MHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. POWER−UP TIMING (Notes 4 and 7)
Symbol
Max
Units
tPUR
Power−up to Read Operation
Parameter
1
ms
tPUW
Power−up to Write Operation
1
ms
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
v 50 ns
Input Pulse Voltages
Timing Reference Voltages
0.4 V to 2.4 V
4.5 V v VCC v 5.5 V
0.8 V, 2.0 V
4.5 V v VCC v 5.5 V
0.2 VCC to 0.7 VCC
1.8 V v VCC v 4.5 V
Timing Reference Voltages
0.5 VCC
1.8 V v VCC v 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL = 100 pF
Input Pulse Voltages
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CAT93C46R
Table 8. INSTRUCTION SET
Address
Data
Instruction
Start Bit
Opcode
x8
x16
x8
READ
1
10
A6−A0
A5−A0
Read Address AN–A0
ERASE
1
11
A6−A0
A5−A0
Clear Address AN–A0
WRITE
1
01
A6−A0
A5−A0
EWEN
1
00
11XXXXX
11XXXX
Write Enable
EWDS
1
00
00XXXXX
00XXXX
Write Disable
ERAL
1
00
10XXXXX
10XXXX
Clear All Addresses
WRAL
1
00
01XXXXX
01XXXX
Device Operation
The CAT93C46R is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46R can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46R operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
D7−D0
D7−D0
x16
D15−D0
D15−D0
Comments
Write Address AN–A0
Write All Addresses
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
Sequential Read
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS is
continuously asserted and SK continues to toggle, the device
will keep incrementing to the next address automatically
until it reaches the end of the address space, then loops back
to address 0. In the sequential Read mode, only the initial
data word is preceeded by a dummy zero bit; all subsequent
data words will follow without a dummy zero bit.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status.
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CAT93C46R
tSKHI
tSKLOW
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tDIS
tPD0, tPD1
DO
tCSMIN
DATA VALID
Figure 2. Synchronous Data Timing
SK
tCSMIN
CS
AN
DI
1
1
AN−1
STANDBY
A0
0
DO
tHZ
tPD0
HIGH−Z
HIGH−Z
0
DN
DN−1
D1
D0
Figure 3. Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
AN
DI
DO
1
1
AN−1
Don’t Care
A0
0
HIGH−Z
Dummy 0
D15...D0
or
D7...D0
Address + 1
D15...D0
or
D7...D0
Figure 4. Sequential Read Instruction Timing
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Address + 2
D15...D0
or
D7...D0
Address + n
D15...
or
D7...
CAT93C46R
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 5. EWEN/EWDS Instruction Timing
Write
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of tCSMIN (See Design Note for details). The falling edge of
CS will start the self clocking clear and data store cycle of
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN after the proper number of clock pulses (See Design
Note). The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before the
next rising edge of the clock (SK) in order to start the
self−timed high voltage cycle. This is important because if
the CS is brought low before or after this specific frame
window, the addressed location will not be programmed or
erased.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The falling
SK
tCS MIN
CS
STATUS
VERIFY
AN
DI
1
0
AN−1
A0
DN
D0
1
tSV
DO
STANDBY
tHZ
BUSY
HIGH−Z
READY
tEW
Figure 6. Write Instruction Timing
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6
HIGH−Z
CAT93C46R
SK
CS
STANDBY
STATUS VERIFY
AN−1
AN
1
DI
1
tCS MIN
A0
1
tSV
tHZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
tEW
Figure 7. Erase Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS MIN
DI
1
0
0
1
0
tSV
tHZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
tEW
Figure 8. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS MIN
DI
1
0
0
0
DN
1
D0
tSV
tHZ
BUSY
DO
tEW
Figure 9. WRAL Instruction Timing
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READY
HIGH−Z
CAT93C46R
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT93C46R
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT93C46R
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
e
0.20
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT93C46R
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SYMBOL
MIN
SIDE VIEW
NOM
A
0.70
0.75
0.80
0.00
0.02
0.05
A2
0.45
0.55
0.65
A2
0.20 REF
A3
b
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
e
L
BOTTOM VIEW
MAX
A1
A3
FRONT VIEW
0.50 TYP
0.20
0.30
L
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT93C46R
Ordering Information
Specific
Device
Marking
Pkg Type
Temperature Range
CAT93C46RLI−G
93C46RL
PDIP−8
CAT93C46RVI−G
93C46RV
CAT93C46RVI−GT3
Lead
Finish
Shipping
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
93C46RV
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
EL
TDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C46RYI−G
46R
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C46RYI−GT3
46R
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
OPN
CAT93C46RVP2IGT3
(Note 8)
8. Not recommended for new designs.
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10. The standard lead finish is NiPdAu.
11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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CAT93C46R/D
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