CAV93C76 D

CAV93C76
8-Kb Microwire Serial
EEPROM
Description
The CAV93C76 is an 8−Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at VCC or Not
Connected) or 8 bits (ORG pin at GND). Each register can be written
(or read) serially by using the DI (or DO) pin. The CAV93C76 is
manufactured using ON Semiconductor’s advanced CMOS EEPROM
floating gate technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100 years. The device
is available in 8−pin SOIC and TSSOP packages.
Features
•
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Automotive Temperature Grade 1 (−40°C to +125°C)
High Speed Operation: 2 MHz
2.5 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Self−timed Write Cycle with Auto−clear
Software Write Protection
Power−up Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Sequential Read
8−pin SOIC and TSSOP Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant†
VCC
ORG
CS
CAV93C76
DI
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SOIC−8
V SUFFIX
CASE 751BD
PIN CONFIGURATION
CS
SK
DI
DO
1
VCC
NC
ORG
GND
SOIC (V), TSSOP (Y)
(Top View)
PIN FUNCTION
Pin Name
Function
CS
Chip Select
SK
Serial Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
Power Supply
GND
Ground
ORG
Memory Organization
NC
DO
TSSOP−8
Y SUFFIX
CASE 948AL
No Connection
NOTE: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected to
ground, the x8 organization is selected. If the ORG pin
is left unconnected, then an internal pull−up device will
select the x16 organization.
SK
GND
Figure 1. Functional Symbol
ORDERING INFORMATION
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 0
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
CAV93C76/D
CAV93C76
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
NEND (Note 3)
TDR
Endurance
Min
Units
1,000,000
Program / Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = +2.5 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
ICC1
Supply Current (Write)
Write, VCC = 5.0 V
ICC2
Supply Current (Read)
Read, DO open, fSK = 2 MHz, VCC = 5.0 V
ISB1
Standby Current
(x8 Mode)
VIN = GND or VCC
CS = GND, ORG = GND
ISB2
Standby Current
(x16 Mode)
Min
Max
Units
2
mA
500
mA
5
mA
VIN = GND or VCC
CS = GND,
ORG = Float or VCC
3
mA
ILI
Input Leakage Current
VIN = GND to VCC
2
mA
ILO
Output Leakage
Current
VOUT = GND to VCC
CS = GND
2
mA
VIL1
Input Low Voltage
4.5 V ≤ VCC < 5.5 V
−0.1
0.8
V
VIH1
Input High Voltage
4.5 V ≤ VCC < 5.5 V
2
VCC + 1
V
VIL2
Input Low Voltage
2.5 V ≤ VCC < 4.5 V
0
VCC x 0.2
V
VIH2
Input High Voltage
2.5 V ≤ VCC < 4.5 V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
4.5 V ≤ VCC < 5.5 V, IOL = 3 mA
0.4
V
VOH1
Output High Voltage
4.5 V ≤ VCC < 5.5 V, IOH = −400 mA
VOL2
Output Low Voltage
2.5 V ≤ VCC < 4.5 V, IOL = 1 mA
VOH2
Output High Voltage
2.5 V ≤ VCC < 4.5 V, IOH = −100 mA
2.4
V
0.2
VCC − 0.2
V
V
Table 4. PIN CAPACITANCE (Note 4)
Symbol
COUT
CIN
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Min
Max
Units
VOUT = 0 V
5
pF
VIN = 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter.
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Typ
CAV93C76
Table 5. POWER−UP TIMING (Notes 6, 5)
Parameter
Symbol
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
5. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V v VCC v 5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V v VCC v 5.5 V
Input Pulse Voltages
0.2 VCC to 0.7 VCC
2.5 V v VCC v 4.5 V
Timing Reference Voltages
0.5 VCC
2.5 V v VCC v 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL = 100 pF
Table 7. A.C. CHARACTERISTICS
(VCC = +2.5 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Parameter
Symbol
Min
Max
Units
tCSS
CS Setup Time
50
ns
tCSH
CS Hold Time
0
ns
tDIS
DI Setup Time
100
ns
tDIH
DI Hold Time
100
ns
tPD1
Output Delay to 1
0.25
tPD0
Output Delay to 0
0.25
ms
Output Delay to High−Z
100
ns
5
ms
tHZ (Note 6)
tEW
Program/Erase Pulse Width
ms
tCSMIN
Minimum CS Low Time
0.25
ms
tSKHI
Minimum SK High Time
0.25
ms
tSKLOW
Minimum SK Low Time
0.25
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
DC
0.25
ms
2000
kHz
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. INSTRUCTION SET (Note 7)
Address
Data
Instruction
Start
Bit
Opcode
x8
x16
READ
1
10
A10−A0
A9−A0
Read Address AN– A0
ERASE
1
11
A10−A0
A9−A0
Clear Address AN– A0
WRITE
1
01
A10−A0
A9−A0
EWEN
1
00
11XXXXXXXXX
11XXXXXXXX
Write Enable
EWDS
1
00
00XXXXXXXXX
00XXXXXXXX
Write Disable
ERAL
1
00
10XXXXXXXXX
10XXXXXXXX
WRAL
1
00
01XXXXXXXXX
01XXXXXXXX
x8
D7−D0
x16
D15−D0
Comments
Write Address AN– A0
Clear All Addresses
D7−D0
D15−D0
Write All Addresses
7. Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE
and ERASE commands.
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CAV93C76
Device Operation
The CAV93C76 is a 8192−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAV93C76 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the read, write and erase operations of
the device. When organized as X8, seven 14−bit instructions
control the read, write and erase operations of the device.
The CAV93C76 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The most significant bit of the address is “don’t care” but it
must be present.
tSKHI
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAV93C76 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAV93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C76 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
tSKLOW
tCSH
SK
tDIH
tDIS
VALID
VALID
DI
tCSS
CS
tDIS
tPD0, tPD1
DO
DATA VALID
Figure 2. Synchronous Data Timing
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tCSMN
CAV93C76
SK
CS
AN
DI
1
1
AN−1
Don’t Care
A0
0
HIGH−Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. READ Instruction Timing
SK
tCSMIN
CS
STATUS
VERIFY
AN
DI
1
0
AN−1
A0
DN
D0
1
tSV
DO
STANDBY
BUSY
HIGH−Z
READY
tEW
Figure 4. WRITE Instruction Timing
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tHZ
HIGH−Z
CAV93C76
Erase
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAV93C76
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAV93C76 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Note 1: After the last data bit has been sampled, Chip Select
(CS) must be brought Low before the next rising edge of the
clock (SK) in order to start the self−timed high voltage cycle.
This is important because if CS is brought low before or after
this specific frame window, the addressed location will not
be programmed or erased.
Erase/Write Enable and Disable
The CAV93C76 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAV93C76 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Power−On Reset (POR)
Erase All
The CAV93C76 incorporates Power−On Reset (POR)
circuitry which protects the device against malfunctioning
while VCC is lower than the recommended operating
voltage.
The device will power up into a read−only state and will
power−down into a reset state when VCC crosses the POR
level of ~1.3 V.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The falling
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C76 can be
SK
CS
STATUS VERIFY
AN
DI
1
1
AN−1
tCS
A0
1
tSV
DO
STANDBY
HIGH−Z
tHZ
BUSY
tEW
Figure 5. ERASE Instruction Timing
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6
READY
HIGH−Z
CAV93C76
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 6. EWEN/EWDS Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
1
0
0
tSV
tHZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
tEW
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
1
DN
D0
tSV
tHZ
BUSY
DO
tEW
Figure 8. WRAL Instruction Timing
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READY
HIGH−Z
CAV93C76
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAV93C76
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
1.20
A
E1
E
MAX
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.20
0.65 BSC
e
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAV93C76
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
Package Type
Temperature Range
Lead
Finish
CAV93C76VE−GT3
93C76D
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAV93C76YE−GT3
M76D
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
Shipping
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
11. For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
12. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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CAV93C76/D
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