INTERSIL ISL54052IRUZ-T

ISL54051, ISL54052
®
Data Sheet
September 25, 2007
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Single SPST Analog
Switches
The Intersil ISL54051 and ISL54052 devices are low
ON-resistance, low voltage, bidirectional, single pole/single
throw (SPST) analog switches designed to operate from a
single +1.8V to +5.5V supply. Targeted applications include
battery powered equipment, which benefit from low rON
resistance (0.8Ω), excellent rON flatness, and fast switching
speeds (tON = 24ns, tOFF = 10ns). The digital logic input is
1.8V logic compatible when using a single +3.0V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to switch
in additional functionality while reducing ASIC design risk. The
ISL54051 and the ISL54052 are offered in a 6 Ld
1.2mmx1.0mmx0.5mm µTDFN package, alleviating board
space limitations.
The ISL54051 has one normally open (NO) switch and
ISL54052 has one normally closed (NC) switch.
TABLE 1. FEATURES AT A GLANCE
ISL54051
ISL54052
Number of Switches
1
1
SW
NO
NC
1.8V rON
2.3Ω
2.3Ω
1.8V tON/tOFF
68ns/45ns
68ns/45ns
3V rON
1.1Ω
1.1Ω
3V tON/tOFF
29ns/12ns
29ns/12ns
5V rON
0.8Ω
0.8Ω
5V tON/tOFF
24ns/10ns
24ns/10ns
FN6459.2
Features
• ON-resistance (rON)
- VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8Ω
- VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1Ω
- VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3Ω
• rON flatness (+4.5V supply) . . . . . . . . . . . . . . . . . . . . . 0.25Ω
• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V, CMOS logic compatible (+3V supply)
• Available in 6 Ld µTDFN Package
• Pb-free (RoHS compliant)
Applications
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
6 Ld μTDFN
Packages
Ordering Information
PART NUMBER (Note)
PART MARKING TEMP. RANGE (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
ISL54051IRUZ-T*
A
-40 to +85
6 Ld (0.40mm pitch) 1.2x1.0x0.5 μTDFN Tape and Reel L6.1.2x1.0A
ISL54052IRUZ-T*
B
-40 to +85
6 Ld (0.40mm pitch) 1.2x1.0x0.5 μTDFN Tape and Reel L6.1.2x1.0A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54051, ISL54052
Pinouts
(Note 1)
ISL54052
(6 LD µTDFN)
TOP VIEW
ISL54051
(6 LD µTDFN)
TOP VIEW
NO
1
6
IN
N.C.
1
6
IN
GND
2
5
V+
GND
2
5
V+
N.C.
3
4
COM
NC
3
4
COM
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
NOTE:
Pin Descriptions
LOGIC
ISL54051
ISL54052
PIN
0
Off
On
V+
1
On
Off
GND
Ground Connection
IN
Digital Control Input
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 2V to 5V supply.
COM
2
FUNCTION
System Power Supply Input (+1.8V to +5.5V)
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
N.C.
No Connect
FN6459.2
September 25, 2007
ISL54051, ISL54052
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . ± 600mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
6 Ld μTDFN Package . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
VIN (Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless
Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
Full
0
-
V+
V
25
-
0.86
-
Ω
Full
-
1
-
Ω
25
-
0.25
-
Ω
TYP
MAX
(Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
rON Flatness, rFLAT(ON)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
Full
-
0.27
-
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V
25
-10
5
10
nA
Full
-150
-
150
nA
COM ON Leakage Current,
ICOM(ON)
V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V,
or floating
25
-20
9
20
nA
Full
-300
-
300
nA
25
-
24
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Charge Injection, Q
VG = 0V, RG = 0Ω, CL = 1.0nF (See Figure 2)
OFF Isolation
Full
-
30
-
ns
25
-
10
-
ns
Full
-
15
-
ns
25
-
26
-
pC
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
80
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 600Ω
25
-
0.012
-
%
-3dB Bandwidth
RL = 50Ω
25
-
190
-
MHz
NO or NC OFF Capacitance, COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
16
-
pF
COM ON Capacitance, CCOM(ON)
25
-
48
-
pF
V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
3
FN6459.2
September 25, 2007
ISL54051, ISL54052
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless
Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
Full
1.8
-
5.5
V
25
-
0.075
0.1
μA
Full
-
-
2.5
μA
TYP
MAX
(Notes 5, 6) UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.8
V
Input Voltage High, VINH
Full
2.4
-
-
V
Full
-0.1
-
0.1
μA
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless
Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
Full
0
-
25
-
Full
-
MAX
(Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 3V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
ON-Resistance, rON
rON Flatness, rFLAT(ON)
V+ = 3V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
V+
V
1.1
1.2
Ω
-
1.5
Ω
25
-
0.33
0.35
Ω
Full
-
-
0.4
Ω
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Turn-ON Time, tON
25
-
29
-
ns
Full
-
35
-
ns
25
-
12
-
ns
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Full
-
17
-
ns
Charge Injection, Q
VG = 0V, RG = 0Ω,CL = 1.0nF (See Figure 2)
25
-
32
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
80
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5)
25
-
16
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 5)
25
-
48
-
pF
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.1
-
0.1
μA
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
MAX
(Notes 5, 6) UNITS
Full
0
-
V+
V
25
-
2.33
-
Ω
Full
-
2.54
-
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 4)
4
FN6459.2
September 25, 2007
ISL54051, ISL54052
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
25
-
68
-
ns
Full
-
93
-
ns
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
25
-
45
-
ns
Full
-
71
-
ns
VG = V+/2, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
18
-
pC
PARAMETER
MAX
(Notes 5, 6) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
Charge Injection, Q
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1
-
-
V
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
8. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
VINH
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
C
VINL
tOFF
SWITCH
INPUT
SWITCH
V
INPUT NX
VOUT
COM
IN
90%
SWITCH
OUTPUT
VOUT
NO OR NC
90%
0V
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
--------------------------V OUT = V
(NO or NC) R + r
L
( ON )
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
ΔVOUT
VINH
LOGIC
INPUT
ON
ON
VG
NO OR NC
GND
C
VOUT
COM
IN
CL
OFF
VINL
LOGIC
INPUT
Q = ΔVOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
5
FN6459.2
September 25, 2007
ISL54051, ISL54052
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
100mA
IN
0V OR V+
IN
V1
COM
ANALYZER
VINL OR VINH
COM
GND
GND
RL
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. rON TEST CIRCUIT
V+
C
NO OR NC
IN
VINL OR VINH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
Supply Sequencing and Overvoltage Protection
The ISL54051 and ISL54052 are bidirectional, single
pole/single throw (SPST) analog switches. They offer
precise switching capability from a single 1.8V to 5.5V
supply with low ON-resistance and high speed operation.
With a single supply of 5V the typical ON-resistance is only
0.8Ω, with a typical turn-on and turn-off time of: tON = 24ns,
tOFF = 10ns. The devices are especially well suited for
portable battery powered equipment due to their low
operating supply voltage (1.8V), low power consumption
(5.5μW), low leakage currents (300nA max) and tiny μTDFN
package.
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 6). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
The ISL54051 is a single normally open (NO) SPST analog
switch. The ISL54052 is a single normally closed (NC) SPST
analog switch.
6
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 6). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
FN6459.2
September 25, 2007
ISL54051, ISL54052
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting schottky
diodes to the signal pins (as shown in Figure 6) will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 6. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The constuction of the ISL54051 and the ISL54052 is typical
of most single supply CMOS analog switches in that they
have two supply pins: V+ and GND. V+ and GND drive the
internal CMOS switches and set their analog voltage limits.
Unlike switches with a 4.5V maximum supply voltage, the
ISL54051 and the ISL54052’s 5.5V maximum supply voltage
provides plenty of room for the 10% tolerance of 4.3V
supplies, as well as room for overshoot and noise spikes.
The minimum recommended supply voltage is 1.8V but the
part will operate with a supply below 1.8V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables starting on page 3 and
“Typical Performance Curves” starting on page 8 for details.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, the ISL54051 and the ISL54052 have a
-3dB bandwidth of 190MHz (see Figure 14). The frequency
response is very consistent over a wide V+ range, and for
varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough. Figure 15 details the high
off isolation rejection provided by this family. At 100kHz, off
isolation is about 80dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease off isolation and crosstalk
rejection due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
V+ and GND also power the internal logic and level shiftier.
The level shiftier converts the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2V to 5V (see Figure 13). At 5V the
VIH level is about 1.2V. This is still below the 1.8V CMOS
guaranteed high output minimum level of 1.4V, but noise
margin is reduced.
7
FN6459.2
September 25, 2007
ISL54051, ISL54052
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
2.5
1.0
ICOM = 100mA
0.9
V+ = 1.8V
2.0
0.8
0.7
rON (Ω)
rON (Ω)
1.5
V+ = 2.7V
1.0
+85°C
0.6
+25°C
0.5
V+ = 3V
V+ = 4.5V
0.4
V+ = 5V
-40°C
0.5
V+ = 5V
ICOM = 100mA
0.3
0.2
0
0
1
2
3
0
5
4
1
2
3
5
4
VCOM (V)
VCOM (V)
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE
3.0
1.5
V+ = 1.8V
ICOM = 10mA
1.4
2.5
1.3
1.2
2.0
rON (Ω)
rON (Ω)
1.1
+85°C
1.0
0.9
+85°C
1.5
+25°C
+25°C
0.8
-40°C
1.0
0.7
-40°C
0.6
V+ = 3.0V
ICOM = 100mA
0.5
0
0.5
1.0
1.5
2.0
2.5
0.5
0
3.0
0.5
1.0
1.5
1.8
VCOM (V)
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
80
100
90
-40°C
80
60
-40°C
60
tOFF (ns)
tON (ns)
70
50
40
+85°C
+25°C
30
40
+25°C
20 +85°C
20
-40°C
10
0
1.8
2.8
3.8
4.8
V+ (V)
FIGURE 11. TURN-ON TIME vs SUPPLY VOLTAGE
8
0
1.8
-40°C
2.8
3.8
4.8
V+ (V)
FIGURE 12. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6459.2
September 25, 2007
ISL54051, ISL54052
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
1.6
1.4
VINH AND VINL (V)
1.2
VINH
1.0
VINL
0
GAIN
-1
-2
-3
0.8
0.6
V+ = 5.0V
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
0.4
0.2
2.0
2.5
3.0
3.5
4.0
V+ (V)
4.5
5.0
0.01k
5.5
ISOLATION
-60
-60
-80
-80
-100
-100
10
0
Q (pC)
-40
20
OFF ISOLATION (dB)
CROSSTALK (dB)
-40
1G
V+ = 3.0V
30
-20
100M
40
0
V+ = 1.8V to 5.5V
-20
1M
10M
FREQUENCY (Hz)
FIGURE 14. FREQUENCY RESPONSE
FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
0
0.1k
-10
V+ = 1.8V
-20
V+ = 5V
V+ = 3.0V
-30
-40
-120
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 15. OFF ISOLATION
-120
100M 500M
-50
-60
0
1
2
3
4
5
VCOM (V)
FIGURE 16. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
57
PROCESS:
Submicron CMOS
9
FN6459.2
September 25, 2007
ISL54051, ISL54052
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
L6.1.2x1.0A
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
2X
0.10 C
2X
D
0.10 C
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A
0.08 C
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
0.40 BSC
e
A1 A3
SIDE VIEW
C
SEATING
PLANE
4X
e
DETAIL B
1
5X
L
3
-
b
DETAIL A
0.10 C
7X
0.127 REF
A3
TOP VIEW
-
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3
θ
0
-
12
4
L1
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6
4
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
0.1x45°
CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
A3
A1
DETAIL A
DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.30
0.45
0.35
0.20
0.40
LAND PATTERN
10
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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10
FN6459.2
September 25, 2007