CM1224 D

CM1224
2 and 4-Channel
Low Capacitance
ESD Protection Arrays
Product Description
The CM1224 family of diode arrays has been designed to provide
ESD protection for electronic components or subsystems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
the positive (VP) or negative (VN) supply rail. A Zener diode is
embedded between VP and VN, offering two advantages. First, it
protects the VCC rail against ESD strikes, and second, it eliminates the
need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1224 will protect
against ESD pulses up to ±8 kV per the IEC 61000−4−2 standard.
These devices are particularly well−suited for protecting systems
using high−speed ports such as USB 2.0, IEEE1394 (Firewire®,
iLinkt), Serial ATA, DVI, HDMI and corresponding ports in
removable storage, digital camcorders, DVD−RW drives and other
applications where extremely low loading capacitance with ESD
protection are required.
The CM1224 family of devices has lead−free finishing in a small
package footprint.
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SOT23−6
SO SUFFIX
CASE 527AJ
SOT−143
SR SUFFIX
CASE 318A
MSOP 10
MR SUFFIX
CASE 846AE
BLOCK DIAGRAM
VP
CH1
CH4
VP
CH3
CH1
VN
CH2
CH2
VN
CM1224−02SR
CM1224−04SO
CM1224−04MR
MARKING DIAGRAM
Features
• Two or Four Channels of ESD Protection
• Provides ESD Protection to IEC61000−4−2 Level 4
•
•
•
•
•
•
•
•
•
L242 MG
G
±8 kV Contact Discharge
Low Channel Input Capacitance of 0.7 pF Typical
Minimal Capacitance Change with Temperature and Voltage
Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for
Differential Dignals
Zener Diode Protects Supply Rail and Eliminates the Need for
External By−pass Capacitors
Low Clamping Voltage (VCLAMP) at 10 V
Low Dynamic Resistance (RDYN) at 1.08 W
Each I/O Pin Can Withstand Over 1000 ESD Strikes
Available in SOT and MSOP Lead−free Packages
These Devices are Pb−Free and are RoHS Compliant
Applications
• USB2.0 Ports at 480 Mbps in desktop PCs, Notebooks and Peripherals
• IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 5
L243 MG
G
L244 MG
G
1
SOT143−4
SOT23−6
MSOP−10
L24x
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
CM1224−02SR
SOT143−4
(Pb−Free)
3000/Tape & Reel
Shipping
CM1224−04SO
SOT23−6
(Pb−Free)
3000/Tape & Reel
CM1224−04MR
MSOP−10
(Pb−Free)
4000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• General Purpose High−speed Data Line ESD Protection
1
Publication Order Number:
CM1224/D
CM1224
PACKAGE / PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
Top View
2−Channel, 4−Lead SOT143−4 Package
Name
Type
Description
1
VN
GND
2
CH1
I/O
ESD Channel
3
CH2
I/O
ESD Channel
4
VP
PWR
VN
1
CH1
2
4
VP
3
CH2
L242
Pin
Negative voltage supply rail
4−Lead SOT143−4
Positive voltage supply rail
4−Channel, 6−Lead SOT23−6 Packages
Name
Type
1
CH1
I/O
2
VN
GND
3
CH2
I/O
ESD Channel
4
CH3
I/O
ESD Channel
5
VP
PWR
6
CH4
I/O
Top View
Description
ESD Channel
Negative voltage supply rail
CH1
1
VN
2
CH2
3
L244
Pin
6
CH4
5
VP
4
CH3
6−Lead SOT23−6
Positive voltage supply rail
ESD Channel
4−Channel, 10−Lead MSOP−10 Packages
Pin
Name
Type
1
CH1
I/O
2
NC
Description
Top View
ESD Channel
No Connect
VP
PWR
4
CH2
I/O
5
NC
6
CH3
7
NC
8
VN
GND
9
CH4
I/O
10
NC
Positive voltage supply rail
ESD Channel
No Connect
I/O
1
2
3
4
5
L243
3
CH1
NC
VP
CH2
NC
10
9
8
7
6
NC
CH4
VN
NC
CH3
10−Lead MSOP−10
ESD Channel
No Connect
Negative voltage supply rail
ESD Channel
No Connect
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Operating Supply Voltage (VP − VN)
Units
6.0
V
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
(VN − 0.5) to (VP + 0.5)
V
DC Voltage at any Channel Input
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
CM1224
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
SOT23−3, SOT143−4, SOT23−5 and SOT23−6 Packages
MSOP−10 Package
Rating
Units
–40 to +85
°C
mW
225
400
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)
Symbol
Parameter
Conditions
VP
Operating Supply Voltage (VP−VN)
IP
Operating Supply Current
(VP−VN) = 3.3 V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8 mA; TA = 25°C
Channel Leakage Current
TA = 25°C; VP = 5 V, VN = 0 V
Channel Input Capacitance
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
DCIN
Channel Input Capacitance Matching
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
VESD
ESD Protection − Peak Discharge
Voltage at any channel input, in system
Contact discharge per
IEC 61000−4−2 standard
ILEAK
CIN
Min
0.6
0.6
0.6
Typ
Max
Units
3.3
5.5
V
8.0
mA
V
0.8
0.8
0.95
0.95
±0.1
±1.0
mA
0.7
0.8
pF
0.02
pF
kV
TA = 25°C (Notes 2 and 3)
VCL
Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A,
tP = 8/20 mS; (Note 3)
RDYN
Dynamic Resistance
Positive Transients
Negative Transients
IPP = 1A, tP = 8/20 mS
Any I/O pin to Ground;
(Note 3)
1. All parameters specified at TA = –40°C to +85°C unless otherwise noted.
2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
3. These measurements performed with no external capacitor on VP (VP floating).
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3
±8
+10
–1.8
1.08
0.66
V
W
CM1224
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
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4
CM1224
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)
Figure 1. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP = 3.3 V)
Figure 2. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP = 3.3 V)
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5
CM1224
APPLICATION INFORMATION
Design Considerations
To realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series
inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector)
and the ESD protection device. Figure 3 illustrates an example of a positive ESD pulse striking an input channel. The parasitic
series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from 0 to 30 Amps in 1ns. Here d(IESD)/dt can be
approximated by ΔIESD/Δt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1224 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned earlier should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note “Design Considerations for ESD Protection”.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
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6
CM1224
MECHANICAL DETAILS
The CM1224 is available in SOT143−4, SOT23−6 and MSOP−10 packages with lead−free finishing. The various package
drawings are presented below.
SOT143−4, SOT23−6 and MSOP−10 Mechanical Specifications
The CM1224−02SR devices are supplied in 4−pin SOT143 packages, the CM1224−04SO devices are packaged in 6−pin
SOT23 and the CM1224−04MR in 10−lead MSOP packages. Dimensions are presented below.
Table 5. TAPE AND REEL SPECIFICATIONS
Part Number
Chip Size (mm)
Pocket Size (mm)
B0 X A0 X K0
Tape Width
W
Reel
Diameter
Qty per
Reel
P0
P1
CM1224−02SR
2.92 X 2.37 X 1.01
2.60 X 3.15 X1.20
8 mm
178 mm (7″)
3000
4 mm
4 mm
CM1224−04SO
2.90 X 2.80 X 1.45
3.20 X 3.20 X1.40
8 mm
178 mm (7″)
3000
4 mm
4 mm
CM1224−04MR
3.00 X 3.00 X 0.85
3.30 X 5.30 X1.30
12 mm
330 mm (13″)
4000
4 mm
8 mm
Po
Top
Cover
Tape
Ao
+
Ko
For Tape Feeder Reference
Only Including Draft,
Concerning around B.
10 Pitches Cumulative
Tolerance On Tape
±0.2 mm
Embossment
Bo
+
P1
User Direction of Feed
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7
+
Center Lines
of Cavity
W
CM1224
PACKAGE DIMENSIONS
SOT−143
CASE 318A−06
ISSUE U
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE.
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
e
D
A
GAUGE
PLANE
E
DETAIL A
b1
e1
B
3X
b
0.20
TOP VIEW
SIDE VIEW
C A-B D
M
H
c
A1
L
L2
E1
A
SEATING
PLANE
c
0.10 C
C
DETAIL A
SEATING
PLANE
END VIEW
DIM
A
A1
b
b1
c
D
E
E1
e
e1
L
L2
MILLIMETERS
MAX
MIN
0.80
1.12
0.01
0.15
0.30
0.51
0.76
0.94
0.08
0.20
2.80
3.05
2.10
2.64
1.20
1.40
1.92 BSC
0.20 BSC
0.35
0.70
0.25 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
1.92
4X
0.75
2.70
0.20
3X
0.96
0.54
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
CM1224
PACKAGE DIMENSIONS
D
SOT−23, 6 Lead
CASE 527AJ
ISSUE B
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
B
6
5
4
1
2
3
E
E1
GAGE
PLANE
6X
e
TOP VIEW
L2
b
0.20
SEATING
PLANE
L
M
C A
S
B
S
DETAIL A
A2
c
A
6X
0.10 C
A1
SIDE VIEW
C
SEATING
PLANE
DETAIL A
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
3.30
6X
0.85
6X
0.56
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
DIM
A
A1
A2
b
c
D
E
E1
e
L
L2
MILLIMETERS
MIN
MAX
--1.45
0.00
0.15
0.90
1.30
0.20
0.50
0.08
0.26
2.70
3.00
2.50
3.10
1.30
1.80
0.95 BSC
0.20
0.60
0.25 BSC
CM1224
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL
MIN
NOM
1.10
A
E
E1
MAX
A1
0.00
0.05
0.15
A2
0.75
0.85
0.95
b
0.17
0.27
0.23
c
0.13
D
2.90
3.00
3.10
E
4.75
4.90
5.05
E1
2.90
3.00
3.10
0.50 BSC
e
L
0.40
L1
0.80
0.25 BSC
L2
θ
0.60
0.95 REF
0º
8º
DETAIL A
TOP VIEW
D
A
A2
c
A1
e
b
END VIEW
SIDE VIEW
q
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L2
L
L1
DETAIL A
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10
CM1224
iLink is a trademark of S.J.Electro Systems, Inc.
FireWire is a registered trademark of Apple Computer, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CM1224/D
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