CM1293A D

CM1293A
2 and 4-Channel
Low Capacitance
ESD Protection Arrays
Product Description
The CM1293A family of diode arrays has been designed to provide
ESD protection for electronic components or subsystems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series that steer the positive or negative ESD current pulse to either the
positive (VP) or negative (VN) supply rail. A Zener diode is embedded
between VP and VN which helps protect the VCC rail against ESD
strikes. The CM1293A protects against ESD pulses up to ±8 kV
contact discharge) per the IEC 61000−4−2 Level 4 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (FireWire®, i.LINKt),
Serial ATA, DVI, HDMI, and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
• Two and Four Channels of ESD Protection
• Provides ESD Protection to IEC61000−4−2
•
•
•
•
•
•
±8 kV Contact Discharge
Low Loading Capacitance of 2.0 pF Max
Low Clamping Voltage
Channel I/O to I/O Capacitance 1.5 pF Typical
Zener Diode Protects Supply Rail and Eliminates the Need for
External By−Pass Capacitors
Each I/O Pin Can Withstand over 1000 ESD Strikes*
These Devices are Pb−Free and are RoHS Compliant
♦
Applications
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
•
•
•
LCD Displays
Serial ATA Ports in Desktop PCs and Hard Disk Drives
PCI Express Ports
General Purpose High−Speed Data Line ESD Protection
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin
subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at
1 second intervals and all 1000 strikes are completed in one continuous test run.
The part is then subjected to standard production test to verify that all of the
tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 8
1
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MSOP−10
MR SUFFIX
CASE 846AE
SC−74
SO SUFFIX
CASE 318F
SOT−143
SR SUFFIX
CASE 318A
BLOCK DIAGRAM
VP
CH4
CH1
VP
CH3
CH2
VN
CM1293A−02SR
CM1293A−02SO
CH1 VN CH2
CM1293A−04MR
MARKING DIAGRAM
XXX MG
G
XXX
M
G
XXX MG
G
= Specific Device Code
= Date Code
= Pb−Free Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
CM1293A−02SR
SOT143−4
(Pb−Free)
3,000 /
Tape & Reel
CM1293A−02SO
SC−74
(Pb−Free)
3,000 /
Tape & Reel
CM1293A−04MR
MSOP−10
(Pb−Free)
4,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
CM1293A/D
CM1293A
PACKAGE/PINOUT DIAGRAM
Table 1. PIN DESCRIPTIONS
2−Channel, 4−Lead SOT143−4 Package (CM1293A−02SR)
Pin
Name
Type
Description
1
VN
GND
2
CH1
I/O
ESD Channel
3
CH2
I/O
ESD Channel
4
VP
PWR
Top View
Negative Voltage Supply Rail
VN (1)
VP (4)
D636
CH1 (2)
Positive Voltage Supply Rail
CH2 (3)
4−Lead SOT143−4
2−Channel, SC−74 Package (CM1293A−02SO)
Pin
Name
Type
1
NC
−
2
VN
GND
Description
No Connect
Top View
Negative Voltage Supply Rail
CH1
I/O
ESD Channel
4
CH2
I/O
ESD Channel
VN (2)
5
NC
−
6
VP
PWR
No Connect
VP (6)
633
3
NC (1)
CH1 (3)
Positive Voltage Supply Rail
NC (5)
CH2 (4)
2−Channel SC−74
4−Channel, 10−Lead MSOP−10 Package (CM1293A−04MR)
Name
Type
1
CH1
I/O
2
NC
−
3
VP
PWR
4
CH2
I/O
5
NC
−
6
CH3
I/O
7
NC
−
8
VN
GND
9
CH4
I/O
10
NC
−
Description
ESD Channel
Top View
No Connect
CH1
NC
VP
CH2
NC
Positive Voltage Supply Rail
ESD Channel
No Connect
D641
Pin
NC
CH4
VN
NC
CH3
10−Lead MSOP−10
ESD Channel
No Connect
Negative Voltage Supply Rail
ESD Channel
No Connect
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2
CM1293A
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
6.0
V
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
(VN − 0.5) to (VP + 0.5)
V
Operating Supply Voltage (VP − VN)
DC Voltage at any Channel Input
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
SOT143−4 Package (CM1293A−02SR)
SC−74 Package (CM1293A−02SO)
MSOP−10 Package (CM1293A−04MR)
Rating
Units
–40 to +85
°C
mW
225
225
400
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Conditions
VP
Operating Supply Voltage (VP−VN)
IP
Operating Supply Current
(VP−VN) = 3.3 V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8 mA, TA = 25°C
Channel Leakage Current
TA = 25°C, VP = 5 V, VN = 0 V
Channel Input Capacitance
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
ILEAK
CIN
1.
2.
3.
4.
Parameter
DCIO
Channel I/O to I/O Capacitance
VESD
ESD Protection − Peak Discharge
Voltage at any Channel Input, in System
Contact Discharge per
IEC 61000−4−2 Standard
Human Body Model, MIL−STD−883,
Method 3015
Min
0.60
0.60
Typ
Max
Units
3.3
5.5
V
8.0
mA
V
0.80
0.80
0.95
0.95
±0.1
±1.0
mA
2.0
pF
1.5
pF
kV
TA = 25°C (Notes 2 and 4)
±8
TA = 25°C (Notes 3 and 4)
±15
VCL
Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20 mS
(Note 4)
RDYN
Dynamic Resistance
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20 mS
(Note 4)
+9.9
–1.6
0.96
0.5
All parameters specified at TA = –40°C to +85°C unless otherwise noted.
Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
Human Body Model per MIL−STD−883, Method 3015, CDischarge = 100 pF, RDischarge = 1.5 kW, VP = 3.3 V, VN grounded.
These measurements performed with no external capacitor on VP.
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3
V
W
CM1293A
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)
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4
CM1293A
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP = 3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP = 3.3 V)
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5
CM1293A
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a
connector) and the ESD protection device. Refer to Figure 5, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the
line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 μF ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
L2
VP
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
D1
0.22 mF
D2
ONE
CHANNEL
POSITIVE SUPPLY RAIL
VCC
PATH OF ESD CURRENT PULSE IESO
LINE BEING
PROTECTED
L1
CHANNEL
INPUT
25 A
0A
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
VCL
GROUND RAIL
VN
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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6
CM1293A
PACKAGE DIMENSIONS
SOT−143
CASE 318A−06
ISSUE U
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM­
UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO­
TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,
AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE.
5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
e
D
A
GAUGE
PLANE
E
DETAIL A
b1
e1
B
3X
b
0.20
TOP VIEW
SIDE VIEW
C A-B D
M
H
c
A1
L
L2
E1
A
SEATING
PLANE
c
0.10 C
C
DETAIL A
SEATING
PLANE
END VIEW
DIM
A
A1
b
b1
c
D
E
E1
e
e1
L
L2
MILLIMETERS
MAX
MIN
0.80
1.12
0.01
0.15
0.30
0.51
0.76
0.94
0.08
0.20
2.80
3.05
2.10
2.64
1.20
1.40
1.92 BSC
0.20 BSC
0.35
0.70
0.25 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
1.92
4X
0.75
2.70
0.20
3X
0.96
0.54
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
CM1293A
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE N
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F−01, −02, −03, −04 OBSOLETE. NEW
STANDARD 318F−05.
D
6
HE
1
5
4
2
3
E
DIM
A
A1
b
c
D
E
e
L
HE
b
e
0.05 (0.002)
C
A
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.37
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.074
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.015
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
CM1293A
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL
MIN
NOM
1.10
A
E
E1
MAX
A1
0.00
0.05
0.15
A2
0.75
0.85
0.95
b
0.17
0.27
c
0.13
0.23
D
2.90
3.00
3.10
E
4.75
4.90
5.05
E1
2.90
3.00
3.10
0.50 BSC
e
L
0.40
L1
0.80
0.25 BSC
L2
θ
0.60
0.95 REF
0º
8º
DETAIL A
TOP VIEW
D
A
END VIEW
A2
A1
c
e
b
q
SIDE VIEW
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
FireWire is a registered trademark of Apple Computer, Inc.
i.LINK is a trademark of Sony Corporation.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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For additional information, please contact your local
Sales Representative
CM1293A/D
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