ESD5004 D

ESD5004
ESD Protection Diode
Low Capacitance ESD Protection Diode
The ESD5004 is designed for applications requiring ESD
protection. It is intended to be used in sensitive equipment such as
smartphone, wireless headsets, digital cameras, computers, printers,
communication systems, and other applications. The integrated design
provides very effective and reliable protection for four separate lines
using only one package. This device is ideal for situations where board
space is at a premium.
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MARKING
DIAGRAM
X3DFN4
CASE 714AA
Features
• Low Capacitance (5 pF Max, I/O to GND)
• Four Separate Bi−directional Configurations for Protection
• Protection for the Following IEC Standards:
•
•
4
M
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
= Specific Device Code
= Date Code
PIN CONFIGURATION
AND SCHEMATIC
2
• Smartphone and Portable Electronics
• Notebooks, Desktops, Servers
• Microprocessor Based Equipment
3
5
1
4
(Bottom View)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±10
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
4M
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
2
3
4
5
ORDERING INFORMATION
Device
ESD5004MXTBG
Package
Shipping†
X3DFN4
(Pb−Free)
8000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 2
1
Publication Order Number:
ESD5004/D
ESD5004
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
VRWM
Breakdown Voltage
VBR
Conditions
Min
Typ
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
Max
Unit
3.3
V
3.9
V
Reverse Leakage Current
IR
VRWM = 3.3 V, I/O Pin to GND
Clamping Voltage
VC
8 x 20 ms, Ipp = 1 A
5.0
Clamping Voltage
TLP (Note 1)
See Figures 4 and 5
VC
IPP = 16 A
IPP = −16 A
10
4.5
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
3.5
1.0
mA
9.1
V
V
5.0
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 1. IEC61000−4−2 Spec
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2
ESD5004
45
5
40
0
35
−5
30
−10
VOLTAGE (V)
25
20
15
−15
−20
−25
10
−30
5
−35
0
−40
−5
−20
0
20
40
60
80
100
120
−45
−20
140
0
20
40
Figure 2. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
20
100
120
140
Figure 3. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
−20
10
10
−18
18
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
8
16
8
−14
14
6
12
−12
6
−10
10
4
8
6
2
4
−8
4
−6
−4
2
−2
2
2
4
6
8
10 12
14
VC, VOLTAGE (V)
16
18
0
0
20
0
2
Figure 4. Positive TLP I−V Curve
4
6
8
10 12
14
VC, VOLTAGE (V)
3.5
3.0
I/O−GND
2.5
2.0
1.5
1.0
0.5
0
0
0.5
16
Figure 5. Negative TLP I−V Curve
4.0
C (pF)
TLP CURRENT (A)
80
TIME (ns)
TIME (ns)
0
0
60
1.0
1.5
2.0
2.5
VR, VOLTAGE (V)
Figure 6. CV Characteristics
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3
3.0
3.5
18
0
20
EQUIVALENT VIEC (kV)
VOLTAGE (V)
TYPICAL CHARACTERISTICS
ESD5004
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD5004
PACKAGE DIMENSIONS
X3DFN4 0.525x0.925, 0.3P
CASE 714AA
ISSUE B
PIN ONE
REFERENCE
2X
0.05 C
2X
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
D
ÉÉ
ÉÉ
MILLIMETERS
DIM MIN
MAX
A
0.24
0.32
A1 0.00
0.05
b
0.12
0.18
D
0.525 BSC
E
0.925 BSC
e
0.30 BSC
L 0.173 0.233
L2 0.42
0.48
E
TOP VIEW
A
0.05 C
RECOMMENDED
SOLDER FOOTPRINT*
0.05 C
A1
SIDE VIEW
NOTE 3
SEATING
PLANE
C
0.66
5X
5X
L2
b
0.07
1
4X
0.38
0.18
M
2
C A B
NOTE 3
4X
1.08
1
L
0.30
PITCH
4
3
DIMENSIONS: MILLIMETERS
e
e/2
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
Sales Representative
ESD5004/D
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