ESD5B5.0ST1 D

ESD5B5.0S, SZESD5B5.0S
Transient Voltage Suppressor
Micro−Packaged Diode for ESD Protection
The ESD5B Series is designed to protect voltage sensitive
components from ESD. Excellent clamping capability, low leakage,
and fast response time provide best in class protection on designs that
are exposed to ESD. Because of its small size and bi−directional
design, it is ideal for use in cellular phones, MP3 players, and portable
applications that require audio line protection.
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Specification Features
•
Low Capacitance 32 pF
Low Clamping Voltage
Small Body Outline Dimensions: nom 0.063″ x 0.032″ (1.6x0.8 mm)
Low Body Height: nom 0.024″ (0.6 mm)
Reverse Working (Stand−off) Voltage: 5.0 V
Peak Power up to 50 W @ 8 x 20 ms Pulse
Low Leakage
Response Time is Typically < 1 ns
ESD Rating of Class 3 (> 16 kV) per Human Body Model
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
This is a Pb−Free Device
2
1
SOD−523
CASE 502
MARKING DIAGRAM
1
B5
M
G
Mechanical Characteristics
CASE: Void-free, transfer-molded, thermosetting plastic
B5
G
M
•
•
•
•
•
•
•
•
•
•
•
G
2
= Specific Device Code
Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
*Date Code orientation and/or position may
vary depending upon manufacturing location.
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
ORDERING INFORMATION
Package
Shipping†
ESD5B5.0ST1G
SOD−523
(Pb−Free)
3000 / Tape &
Reel
ESD5B5.0ST5G
SOD−523
(Pb−Free)
8000 / Tape &
Reel
SZESD5B5.0ST1G
SOD−523
(Pb−Free)
3000 / Tape &
Reel
MAXIMUM RATINGS
Device
Rating
Value
Unit
Contact
Air
±30
±30
kV
Per Human Body Model
Per Machine Model
16
400
kV
V
IEC 61000−4−2 (ESD)
ESD Voltage
Symbol
Peak Power (Figure 1) Per 8 x 20 ms Waveform
Peak Power (Figure 2)Per 10 x 1000 ms Waveform
PPK
50
10
W
Total Power Dissipation on FR−5 Board (Note 1)
@ TA = 25°C
°PD°
200
mW
TJ, Tstg
−55 to
+150
°C
TL
260
°C
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 5
1
Publication Order Number:
ESD5B5.0ST1/D
ESD5B5.0S, SZESD5B5.0S
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
IPP
Parameter
IPP
Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
IT
VC VBR VRWM IR
IR VRWM VBR VC
IT
Working Peak Reverse Voltage
V
Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
IPP
Test Current
Bi−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 0.9 V Max. @ IF = 10 mA for all types)
VRWM
(V)
IR (mA)
@ VRWM
VBR (V) @ IT
(Note 2)
Device*
Max
Max
Min
ESD5B5.0ST1G/T5G,
SZESD5B5.0ST1G
5.0
1.0
5.8
IT
C (pF) @ VR = 0 V,
f = 1 MHz
VC
Max
mA
Typ
Per IEC61000−4−2 (Note 3)
7.8
1.0
32
Figures 1 and 2
See Below
*Other voltages available upon request.
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC 61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC 61000−4−2
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2
ESD5B5.0S, SZESD5B5.0S
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD5B5.0S, SZESD5B5.0S
PACKAGE DIMENSIONS
SOD−523
CASE 502
ISSUE E
−X−
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
−Y−
E
2X
b
0.08
1
M
2
X Y
DIM
A
b
c
D
E
HE
L
L2
TOP VIEW
A
c
MILLIMETERS
MIN
NOM
MAX
0.50
0.60
0.70
0.25
0.30
0.35
0.07
0.14
0.20
1.10
1.20
1.30
0.70
0.80
0.90
1.50
1.60
1.70
0.30 REF
0.15
0.20
0.25
RECOMMENDED
SOLDERING FOOTPRINT*
HE
SIDE VIEW
2X
1.80
0.48
2X
0.40
PACKAGE
OUTLINE
2X
L2
BOTTOM VIEW
2X
L
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
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PUBLICATION ORDERING INFORMATION
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4
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ESD5B5.0ST1/D
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