ESD7124 D

ESD7124
4-Channel Low Capacitance
Dual-Voltage ESD and Surge
Protection Array
Features
• 3 Channels of Low Voltage ESD Protection
• 1 Channel of High Voltage ESD Protection
• Provides ESD Protection to IEC61000−4−2 Level 4:
•
•
•
•
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±25 kV Contact Discharge
IEC 61000−4−5 (lighting)
Low Channel Input Capacitance
High Voltage Zener Diode Protects Supply Rail up to 100 A (8/20 ms)
These Devices are Pb−Free and are RoHS Compliant
UDFN−6
D4 SUFFIX
CASE 517CS
BLOCK DIAGRAM
APPLICATION DIAGRAM
IO1
IO2
IO3
Vcc
Vcc (1)
GND (6)
CH1 (2)
DAP**
High−Speed
Data Lines
CH2 (3)
GND (5)
CH3 (4)
MARKING DIAGRAM
**Die Attach Pad on
back of package
(connect to ground)
1
AD M
G
AD = Specific Device Code
M = Date Code
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
ESD7124MUTBG
UDFN−6
(Pb−Free)
3000/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 0
1
Publication Order Number:
ESD7124/D
ESD7124
PACKAGE / PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
4−Channel, 6−Lead, UDFN−8 Package
Top View
(Pins Down View)
Pin
Name
Type
Description
1
VCC
HV VDD
2
CH1
I/O
LV Low−capacitance ESD Channel
3
CH2
I/O
LV Low−capacitance ESD Channel
4
CH3
I/O
LV Low−capacitance ESD Channel
5
GND
Ground
6
GND
Ground
Bottom View
(Pins Up View)
1 2 3 4
6 5
HV ESD Channel
XX M
Pin 1
Marking
6
1 2 3 4
5
6−Lead UDFN
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Units
Operating Temperature Range
Parameter
–55 to +125
°C
Storage Temperature Range
–65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. ELECTRICAL CHARACTERISTICS
Reverse Working
Voltage
Breakdown
Voltage Vbr (V)
Reverse Current
Leakage Ir (mA)
Rdyn
Junction Capactance
Cj(pF)
Vrwm (V)
at 1 mA
at Vrwm
W
Vr = 0 V, f = 1 MHz
Device Name
Max
Min
Typ
Max
Typ
Typ
Max
Pin2-4 (LV)
3.3
5.5
6.5
1
1
0.35
0.5
Pin1 (HV)
12
13.3
14
1
Clamping Voltage Vc (V)
tp = 8 x 20 ms
Max Ratings
tp = 8 x 20 ms
Ipp = 1 A
Ipp = 16 A
Ipp (A)
Vc @ Max Ipp (V)
Device Name
Typ
Typ
Max
Max
Pin1 (HV)
15
16
100
27
Pin2-4 (LV)
9.5
Parameter
Symbol
Clamping Voltage
TLP (Note 1)
All Devices Pin2-4(LV)
See Figures 3 − 6
VC
Conditions
Min
Typ
IPP = ±8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
16.8
IPP = ±16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
24.9
1. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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2
Max
Unit
V
ESD7124
TYPICAL CHARACTERISTICS
Figure 1. Capacitance Over Frequency
Figure 2. Insertion Loss
Interface
Data Rate
(Mb/s)
Fundamental Frequency
(MHz)
3rd Harmonic Frequency
(MHz)
USB 2.0
480
240 (m1)
720 (m2)
45
0
40
−5
35
−10
m1 = 0.031
m2 = 0.047
−15
Vpk (V)
Vpk (V)
30
ESD7124 Insertion Loss (dB)
25
20
−20
−25
15
−30
10
−35
5
0
0
5
10
15
20
25
30
−40
−35
35
−30
−25
−20
−15
−10
−5
Ipk (A)
Ipk (A)
Figure 3. Positive TLP I−V Curve
Figure 4. Negative TLP I−V Curve
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3
0
ESD7124
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 5. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 6 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 5. Simplified Schematic of a Typical TLP
System
Figure 6. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7124
PACKAGE DIMENSIONS
UDFN6, 1.8x2, 0.4P
CASE 517CS
ISSUE O
D
PIN ONE
REFERENCE
ÇÇ
ÇÇ
ÉÉ
A B
ÍÍÍ
ÍÍÍ
ÍÍÍ
EXPOSED Cu
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINALS
AND IS MEASURED BETWEEN 0.15 AND 0.30mm
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
E
0.10 C
2X
0.10 C
2X
L
L
TOP VIEW
DIM
A
A1
A3
b
D
D2
E
E2
e
e1
e2
L
L1
L1
DETAIL B
A3
0.05 C
DETAIL A
ALTERNATE
CONSTRUCTIONS
A
6X
0.05 C
NOTE 4
A1
C
SIDE VIEW
SEATING
PLANE
0.10 C
DETAIL A
2X
e/2
RECOMMENDED
MOUNTING FOOTPRINT*
e
D2
1
6X
4
1
2X
4
E2
b
0.07 C A B
0.05 C
0.95
NOTE 3
2X
6X
L
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.125 REF
0.15
0.25
1.80 BSC
0.35
0.55
2.00 BSC
0.74
0.94
0.40 BSC
0.80 BSC
0.95 BSC
0.20
0.40
0.15
---
0.40
PITCH
0.55
6X
0.48
0.10 C
6
5
e1/2
6
PACKAGE
OUTLINE
5
2X
0.94 2.20
e2
e1
BOTTOM VIEW
SUPPLEMENTAL
BOTTOM VIEW
6X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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ESD7124/D
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