ESD7461 D

ESD7461, SZESD7461
Ultra-Low Capacitance ESD
Protection
Micro−Packaged Diodes for ESD Protection
The ESD7461 is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. It has industry leading capacitance linearity over voltage
making it ideal for RF applications. This capacitance linearity
combined with the extremely small package and low insertion loss
makes this part well suited for use in antenna line applications for
wireless handsets and terminals.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
Industry Leading Capacitance Linearity Over Voltage
Ultra−Low Capacitance: 0.3 pF Typ
Insertion Loss: 0.05 dB at 1 GHz; 0.21 dB at 3 GHz
Low Leakage: < 1 nA
Protection for the following IEC Standards:
♦ IEC61000−4−2 (ESD): Level 4 ±18 kV Contact
♦ IEC61000−4−4 (EFT): 40 A −5/50 ns
♦ IEC61000−4−5 (Lightning): 1 A (8/20 ms)
ISO 10605 (ESD) 330 pF/2 kW ±23 kV Contact
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
XX
M
XX M
G
= Specific Device Code
= Date Code
ORDERING INFORMATION
Package
Shipping†
ESD7461N2T5G
XDFN2
(Pb−Free)
8000 / Tape &
Reel
SZESD7461N2T5G
XDFN2
(Pb−Free)
8000 / Tape &
Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
•
•
•
•
XDFN2
CASE 711AM
RF Signal ESD Protection
RF Switching, PA, and Antenna ESD Protection
Near Field Communications
USB 2.0, USB 3.0
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
±18
kV
°PD°
RqJA
300
400
mW
°C/W
TJ, Tstg
−55 to
+150
°C
TL
260
°C
IEC 61000−4−2 (ESD) (Note 1)
Total Power Dissipation (Note 2) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform.
2. Mounted with recommended minimum pad size, DC board FR−4
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 0
1
Publication Order Number:
ESD7461/D
ESD7461, SZESD7461
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
IPP
I
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IT
VC VBR VRWM IR
IR
V
IR VRWM VBR VC
IT
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
IT
IPP
Test Current
Bi−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Parameter
Symbol
Reverse Working Voltage
Condition
Min
Typ
VRWM
Breakdown Voltage
VBR
IT = 1 mA (Note 3)
Max
Unit
16
V
16.5
V
Reverse Leakage Current
IR
VRWM = 5 V
<1
Clamping Voltage TLP
VC
IPP = 8 A (Note 4)
35
V
Clamping Voltage TLP
VC
IPP = 16 A (Note 4)
39
V
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
VR = 0 V, f = 1 GHz
0.3
0.3
Dynamic Resistance
RDYN
TLP Pulse
1.05
W
f = 1 GHz
f = 3 GHz
0.05
0.21
dB
Insertion Loss
100
0.55
0.55
nA
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
1.3−03
1
1.E−04
0.8
CAPACITANCE (pF)
1.E−05
CURRENT (A)
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
0.6
0.4
0.2
1.E−11
1.E−12
−30
0
−20
−10
0
10
20
30
−18 −15 −12 −9 −6
−3
0
3
6
9
12 15 18
VOLTAGE (V)
VOLTAGE (V)
Figure 1. Typical IV Characteristics
Figure 2. Typical CV Characteristics
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2
ESD7461, SZESD7461
TYPICAL CHARACTERISTICS
1
1
0.5
0.9
0.8
CAPACITANCE (pF)
S21 (dB)
0
−0.5
−1
−1.5
−2
0.6
0.5
0.4
0.3
0.2
−2.5
−3
1.E+07
0.7
0.1
1.E+08
1.E+09
1.E+10
0
1.E+07
2.E+09
4.E+09
6.E+09
8.E+09
1.E+10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3. Typical Insertion Loss
ESD7461N2T5G (SOD882)
Figure 4. Typical Capacitance over Frequency
ESD7461N2T5G (SOD882)
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3
ESD7461, SZESD7461
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
25
−25
20
−20
TLP CURRENT (A)
TLP CURRENT (A)
ESD7461, SZESD7461
15
10
−15
−10
−5
5
0
0
0
NOTE:
5
10
15
20
25
30
35
40
45
0
−5
−10
−15
−20 −25
−30 −35
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
−40
−45
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD7461, SZESD7461
PACKAGE DIMENSIONS
XDFN2 1.0x0.6, 0.65P (SOD−882)
CASE 711AM
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
0.10 C
ÉÉ
ÉÉ
A B
D
PIN 1
INDICATOR
E
DIM
A
A1
b
D
E
e
L
0.05 C
TOP VIEW
A
NOTE 3
0.10 C
0.10 C
A1
C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.34
0.44
−−−
0.05
0.43
0.53
1.00 BSC
0.60 BSC
0.65 BSC
0.20
0.30
RECOMMENDED
SOLDER FOOTPRINT*
SEATING
PLANE
1.20
2X
e
2X
0.47
0.60
b
e/2
0.05
M
PIN 1
C A B
1
DIMENSIONS: MILLIMETERS
2X
L
0.05
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
C A B
BOTTOM VIEW
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ESD7461/D
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