ESD8006 D

ESD8006
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8006 is specifically designed to protect USB 3.0 and
Thunderbolt interfaces from ESD. Ultra−low capacitance and low
ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
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MARKING
DIAGRAM
UDFN8
CASE 517CB
Features
1
• Low Capacitance (0.25 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
•
6TMG
G
6T = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATION
GND
GND
10
9
Typical Applications
• USB 3.0/3.1
• Thunderbolt
• Display Port
1
I/O
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
2
3
4
I/O GND I/O
5
6
7
I/O GND I/O
8
I/O
ORDERING INFORMATION
Rating
Symbol
Value
Unit
Device
Package
Shipping
Operating Junction Temperature Range
TJ
−55 to +125
°C
ESD8006MUTAG
Storage Temperature Range
Tstg
−55 to +150
°C
UDFN8
(Pb−Free)
3000 / Tape &
Reel
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
SZESD8006MUTAG
UDFN8
3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 4
1
Publication Order Number:
ESD8006/D
ESD8006
I/O I/O
I/O
I/O I/O
I/O
Pin 1 Pin 2 Pin 4 Pin 5 Pin 7 Pin 8
Pins 3, 6, 9, 10
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
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2
ESD8006
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IPP
Parameter
Working Peak Voltage
RDYN
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
V
VC VRWMVHOLD
Test Current
IR
IT
VHOLD
Holding Reverse Voltage
IHOLD
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IT
VC
RDYN
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
−IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
Max
Unit
3.3
V
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
5.5
7.0
V
Reverse Leakage Current
IR
VRWM = 3.3 V, I/O Pin to GND
1.0
Holding Reverse Voltage
VHOLD
I/O Pin to GND
1.19
V
Holding Reverse Current
IHOLD
I/O Pin to GND
25
mA
See Figures 2 and 3
V
V
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
VC
IPP = 8 A
IPP = −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
4.9
−5.0
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.4
−9.5
Dynamic Resistance
RDYN
Junction Capacitance
CJ
I/O Pin to GND
GND to I/O Pin
0.44
0.49
VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 2.5 GHz between I/O Pins and GND
VR = 0 V, f = 5.0 GHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
mA
W
0.32
0.25
0.25
0.16
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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3
VOLTAGE (V)
VOLTAGE (V)
ESD8006
TIME (ns)
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
ESD8006
VC = VHOLD + (IPP * RDYN)
NOTE:
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
Figure 7. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD8006
IO−GND
Figure 11. CV Characteristics
C_ESD8006_pF
dB (ESD8006..Sdd21)
Figure 10. IV Characteristics
Figure 12. RF Insertion Loss
Figure 13. Capacitance over Frequency
TABLE 1. RF Insertion Loss: Application Description
Interface
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3rd Harmonic Frequency
(GHz)
ESD8006 Insertion Loss
(dB)
USB 3.0
5.0
2.5 (m1)
7.5 (m3)
Thunderbolt,
USB 3.1
10
5.0 (m2)
15 (m4)
m1 = 0.098
m2 = 0.240
m3 = 0.479
m4 = 3.732
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6
ESD8006
Without ESD8006
With ESD8006
Figure 14. USB 3.0 Eye Diagram with and without ESD8006. 5 Gb/s
With ESD8006
Without ESD8006
Figure 15. Thunderbolt and USB 3.1 Eye Diagram with and without ESD8006. 10 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
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7
ESD8006
USB 3.0 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
ESD8006
D−
GND_DRAIN
D+
StdA_SSRX+
GND
StdA_SSRX−
Figure 16. USB 3.0/3.1 Layout Diagram
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8
ESD8006
Thunderbolt Connector
Top Layer
GND
ML0+
ESD8006
ML0−
GND
ML1+
ML1−
GND
ML2+
ML2−
GND
Thunderbolt Connector
Bottom Layer
ESD9X
Hot Plug Detect
CONFIG1
ESD8006
CONFIG2
GND
ML3+
ML3−
GND
AUX+
AUX−
PWR
Black = Top layer
Red = Bottom layer
ESD9X
Figure 17. Thunderbolt Layout Diagram
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9
ESD8006
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦ In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 18. In this
configuration, no DC current can flow through the
ESD protection device preventing any potential
•
latch-up condition. For more information on latchup
considerations, see below description on Page 11.
Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Figure 18. USB 3.0 Connection Diagram
Figure 19. Thunderbolt Recommended PCB Layout
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10
ESD8006
Latch-Up Considerations
therefore latch-up free. Please note that for USB 3.0
applications, ESD8006 latch-up free considerations are
explained in more detail in the above PCB layout guidelines.
In the non-latch up free load line case, the IV characteristic
of the snapback protection device intersects the load-line in
two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this
case, the potential for latch-up exists if the system settles at
(VOPB, IOPB) after a transient. Because of this, ESD8006
should not be used for HDMI applications – ESD8104 or
ESD8040 have been designed to be acceptable for HDMI
applications without latch-up. Please refer to Application
Note AND9116/D for a more in-depth explanation of
latch-up considerations using ESD8000 series devices.
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analysis of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP, IOP). This is the only
stable operating point of the circuit and the system is
I
I
ISSMAX
IOPB
ISSMAX
IOP
VOP
IOPA
V
VDD
VOPB
ESD8006 Latch−up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0/3.1 SS,
DisplayPort
VOPA VDD
V
ESD8006 Potential Latch−up:
HDMI 2.0/1.4/1.3a TMDS
Figure 20. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 2.0/1.4/1.3a TMDS
3.465
54.78
1.0
ESD8104, ESD8040
USB 2.0 LS/FS
3.301
1.76
1.0
ESD8004
USB 2.0 HS
0.482
N/A
1.0
ESD8004
USB 3.0/3.1 SS
2.800
N/A
1.0
ESD8004, ESD8006
DisplayPort
3.600
25.00
1.0
ESD8004, ESD8006
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11
ESD8006
PACKAGE DIMENSIONS
UDFN8, 3.3x1.0, 0.4P
CASE 517CB
ISSUE O
PIN ONE
REFERENCE
2X
0.10 C
ÉÉ
ÉÉ
0.10 C
2X
0.05 C
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
EXPOSED Cu
A
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
G2
L
L1
L2
ÉÉÉ
ÉÉÉ
ÇÇÇ
TOP VIEW
(A3)
MOLD CMPD
DETAIL B
A1
SIDE VIEW
8X
DETAIL A
1
e/2
e
7X
2X
G2
C
ALTERNATE
CONSTRUCTION
SEATING
PLANE
b
8
L2
E2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
L1
0.05 C
2X
L
L
A B
D
0.10
M
C A B
0.05
M
C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
3.30 BSC
0.25
0.45
1.00 BSC
0.45
0.55
0.40 BSC
1.19 BSC
0.20
0.30
−−−
0.15
0.30
0.40
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 3
1.66
2X
L
0.50
2X
0.65
D2
BOTTOM VIEW
0.10
M
C A B
0.05
M
C
1.20
0.50
8X
0.25
7X
0.40
PITCH 0.40
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
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ESD8006/D
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