ESD8018 D

ESD8018
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8018 transient voltage suppressor is specifically designed
to protect four high speed data points from ESD. Ultra−low
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines. The
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines.
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MARKING
DIAGRAM
Features
AA
M
G
• Low Capacitance (0.32 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
•
•
IEC 61000−4−2 (Level 4)
IEC 61000−4−5 (Lightning) 5A (8/20 ms)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
AAMG
G
UDFN10
CASE 517CY
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
I/O
I/O
I/O
I/O
10
9
8
7
Typical Applications
•
•
•
•
V−by−One HS
LVDS
USB 3.1 Type C
10 GbE
3
4
5
6
I/O
I/O
GND
I/O
Device
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±17
±17
kV
kV
IPP
5.0
A
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C (I/O−GND)
2
GND
ORDERING INFORMATION
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
1
I/O
ESD8018MUTAG
Package
Shipping
UDFN10 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 1
1
Publication Order Number:
ESD8018/D
ESD8018
I/O
Pin 1
I/O
Pin 3
I/O
Pin 4
I/O
Pin 6
I/O
Pin 7
I/O
Pin 8
I/O
Pin 9
I/O
Pin 10
Pin 2
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
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2
ESD8018
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IPP
Parameter
Working Peak Voltage
RDYN
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
V
VC VRWMVHOLD
Test Current
IR
IT
VHOLD
Holding Reverse Voltage
IHOLD
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IT
VC
RDYN
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
−IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
Max
Unit
3.3
V
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
Reverse Leakage Current
IR
Holding Reverse Voltage
VHOLD
I/O Pin to GND
Holding Reverse Current
IHOLD
I/O Pin to GND
5.5
7.0
V
VRWM = 3.3 V, I/O Pin to GND
1.0
mA
1.19
V
25
mA
See Figures 2 and 3
V
IPP = 1 A, Any I/O to GND (8/20 ms pulse)
1.7
V
VC
IPP = 5 A, Any I/O to GND (8/20 ms pulse)
4.8
V
VC
IPP = 8 A
IPP = −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
4.9
−5.0
V
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.4
−9.5
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage
VC
Clamping Voltage
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
Dynamic Resistance
RDYN
Junction Capacitance
CJ
I/O Pin to GND
GND to I/O Pin
W
0.44
0.49
VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 2.5 GHz between I/O Pins and GND
VR = 0 V, f = 5.0 GHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
0.32
0.25
0.25
0.16
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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3
VOLTAGE (V)
VOLTAGE (V)
ESD8018
TIME (ns)
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
NOTE:
TLP CURRENT (A)
EQUIVALENT VIEC (kV)
VC = VHOLD + (IPP * RDYN)
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
ESD8018
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
Figure 7. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
ESD8018
IO−GND
Figure 11. CV Characteristics
C_ESD8018_pF
Figure 10. IV Characteristics
Peak
Value
100
8
tr = rise time to peak value [8 ms]
tf = decay time to half value [20 ms]
7
6
Vpk (V)
Ipp - PEAK PULSE CURRENT - %Ipp
Figure 12. Capacitance over Frequency
Half Value
50
5
I/O−GND
4
3
2
1
0
0 tr
0
tf
0
TIME (ms)
Figure 13. IEC61000−4−5 8/20 ms Pulse
Waveform
1
2
3
4
IPP (A)
5
6
7
8
Figure 14. Clamping Voltage vs. Peak Pulse Current
(tp = 8/20 ms per Figure 13)
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6
dB (ESD8018..Sdd21)
ESD8018
Figure 15. RF Insertion Loss
TABLE 1. RF Insertion Loss: Application Description
Data Rate
(Gb/s)
Fundamental
Frequency (GHz)
3rd Harmonic
Frequency (GHz)
ESD8018 Insertion
Loss (dB)
V−by−One HS
Full HD (1920 x 1080p)
240 Hz, 36bit color depth
3.71
1.854 (m1)
5.562 (m3)
m1 = 0.146
m3 = 0.451
USB 3.1
10
5.0 (m2)
15 (m4)
M2 = 0.240
m4 = 5.000
Interface
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7
ESD8018
Type−C Hybrid Top Mount Connector
Top Layer
GND
TX1+
TX1−
Vbus
CC1
(Config. detect: Vconn or PD comm.)
D+
D−
SBU1
Sideband use: AUX signal
Vbus
RX2−
RX2+
GND
Type−C Hybrid Top Mount Connector
Bottom Layer
ESD9X
GND
RX1+
RX2+
SBU2
Vbus
D−
D+
Vbus
CC2
TX2−
TX2+
GND
ESD9X
Black = Top layer
Red = Bottom layer
Figure 16. USB 3.1 Type−C Layout Diagram
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ESD8018
Rx0p
ESD8018
Rx0n
Rx1p
Rx1n
Rx2p
Rx2n
Rx3p
TCON Board
Connector
V−by−One HS
Driver
Rx3n
Rx4p
ESD8018
To Timing
Controller
Rx4n
Rx5p
Rx5n
Rx6p
Rx6n
Rx7p
Rx7n
Figure 17. V−by−One HS Layout Diagram (for LCD Panel)
• Make sure to use differential design methodology and
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦ In USB 3.1 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes. In this configuration, no DC
current can flow through the ESD protection device
preventing any potential latch-up condition.
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
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9
ESD8018
Latch-Up Considerations
therefore latch-up free. Please note that for USB 3.1
applications, ESD8018 latch−up free considerations are
explained in more detail in the above PCB guidelines. In the
non-latch up free load line case, the IV characteristic of the
snapback protection device intersects the load-line in two
points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this
case, the potential for latch-up exists if the system settles at
(VOPB, IOPB) after a transient. Because of this, ESD8018
should not be used for HDMI applications – ESD8114 or
ESD8040 have been designed to be acceptable for HDMI
applications without latch-up. Please refer to Application
Note AND9116/D for a more in-depth explanation of
latch-up considerations using ESD8000 series devices.
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP, IOP). This is the only
stable operating point of the circuit and the system is
I
I
ISSMAX
IOPB
ISSMAX
IOP
VOP
IOPA
V
VDD
VOPB
ESD8018 Latch−up free:
V−by−One HS, DisplayPort, LVDS, USB 3.1 SS
VOPA VDD
V
ESD8018 Potential Latch−up:
HDMI 1.4/1.3a TMDS
Figure 18. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 1.4/1.3a TMDS
3.465
54.78
1.0
ESD8040
DisplayPort
3.600
25.00
1.0
ESD8016, ESD8018
V−by−One HS
1.980
21.70
1.0
ESD8018
LVDS
1.829
9.20
1.0
ESD8018
USB 3.1 SS
2.800
N/A
1.0
ESD8016, ESD8018
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10
ESD8018
PACKAGE DIMENSIONS
UDFN10 3.2x1.2, 0.5P
CASE 517CY
ISSUE O
A
B
D
PIN ONE
REFERENCE
ÉÉÉÉ
ÉÉÉÉ
2X
0.10 C
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
E
e
e1
L
L1
L2
TOP VIEW
A
(A3)
0.05 C
10X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
L
L1
E
0.10 C
2X
L
0.05 C
A1
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
3.20 BSC
1.20 BSC
0.50 BSC
0.80 BSC
0.15
0.35
−−−
0.10
0.40
0.60
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
2X
e
L2
0.835
10X
1
8X
0.40
0.28
8X
10
10X
e1/2
e1
BOTTOM VIEW
L
PACKAGE
OUTLINE
1.40
b
0.10 C A B
0.05 C
1
2X
NOTE 3
0.4875
PITCH
0.65
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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Sales Representative
ESD8018/D
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