ESD8116 D

ESD8116
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8116 transient voltage suppressor is specifically designed
to protect USB 3.0/3.1 interfaces from ESD. Ultra−low capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
MARKING
DIAGRAM
UDFN8
CASE 517CX
6C
M
G
• Low Capacitance (0.35 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
•
•
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IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
6CMG
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
I/O
I/O
I/O
I/O
8
7
6
5
Typical Applications
• USB 3.0/3.1
• Display Port
1
2
3
4
I/O
GND
GND
I/O
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device
ESD8116MUTAG
Package
Shipping†
UDFN8
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0
1
Publication Order Number:
ESD8116/D
ESD8116
I/O I/O
I/O
I/O I/O
I/O
Pin 1 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8
Pins 2, 3
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
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2
ESD8116
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
IPP
Parameter
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
RDYN
Working Peak Reverse Voltage
IR
VCL VBR VRWM
Maximum Reverse Leakage Current @ VRWM
VBR
V
IR
IT
VCL
Breakdown Voltage @ IT
IT
RDYN
Test Current
RDYN
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
VRWM
Breakdown Voltage
VBR
Conditions
IT = 1 mA, I/O Pin to GND
4.0
IR
VRWM = 3.3 V, I/O Pin to GND
Clamping Voltage
(Note 1)
VC
IEC61000−4−2, ±8 kV Contact
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
VC
IPP = 8 A
IPP = −8 A
IPP = 16 A
IPP = −16 A
RDYN
Junction Capacitance
CJ
Typ
Max
Unit
3.3
V
1.0
mA
I/O Pin to GND
Reverse Leakage Current
Dynamic Resistance
Min
5.0
V
See Figures 2 and 3
V
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
8.5
−4.5
V
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
11.4
−8.0
I/O Pin to GND
GND to I/O Pin
0.36
0.44
VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 1 MHz between I/O Pins
VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND
0.30
0.15
0.37
W
0.35
0.20
0.47
pF
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
90
10
80
0
70
−10
60
−20
VOLTAGE (V)
VOLTAGE (V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
50
40
30
−30
−40
−50
20
−60
10
−70
0
−80
−10
−20
0
20
40
60
80
100
120
−90
−20
140
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
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3
140
ESD8116
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD8116
20
−20
10
8
−14
14
6
12
−12
6
−10
10
4
8
6
2
4
−8
4
−6
−4
2
−2
2
2
4
6
8
10 12
14
VC, VOLTAGE (V)
16
18
0
0
20
0
2
Figure 6. Positive TLP I−V Curve
NOTE:
4
6
8
10 12
14
VC, VOLTAGE (V)
16
0
20
18
Figure 7. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
8
16
0
0
10
−18
18
ESD8116
Without ESD8116
With ESD8116
Figure 10. USB 3.0 Eye Diagram with and without ESD8116. 5 Gb/s
Without ESD8116
With ESD8116
Figure 11. USB 3.1 Eye Diagram with and without ESD8116. 10 Gb/s
dB(ESD8116..S(2,1))
See application note AND9075/D for further description of eye diagram testing methodology.
Figure 12. RF Insertion Loss
TABLE 1. RF Insertion Loss: Application Description
Interface
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3rd Harmonic Frequency
(GHz)
ESD8116 Insertion Loss
(dB)
USB 3.0
5.0
2.5 (m1)
7.5 (m3)
USB 3.1
10
5.0 (m2)
15 (m4)
m1 = 0.128
m2 = 0.155
m3 = 0.352
m4 = 4.194
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6
ESD8116
USB 3.0/3.1 Type A
Connector
StdA_SSTX+
Vbus
StdA_SSTX−
D−
ESD8116
GND_DRAIN
D+
StdA_SSRX+
GND
StdA_SSRX−
Figure 13. USB 3.0/3.1 Type−A Layout Diagram
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7
ESD8116
Type−C Hybrid Top Mount Connector
Top Layer
GND
TX1+
TX1−
Vbus
CC1
(Config. detect: Vconn or PD comm.)
D+
D−
SBU1
Sideband use: AUX signal
Vbus
RX2−
RX2+
GND
Type−C Hybrid Top Mount Connector
Bottom Layer
GND
ESD9X
RX1+
RX2+
SBU2
Vbus
D−
D+
Vbus
TX2−
CC2
TX2+
GND
ESD9X
Black = Top layer
Red = Bottom layer
Figure 14. USB 3.1 Type−C Layout Diagram
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8
ESD8116
• Make sure to use differential design methodology and
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
♦ In USB 3.0/3.1 applications, the ESD protection
device should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes.
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
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ESD8116
ESD Protection Device Technology
ON Semiconductor’s portfolio contains three main
technologies for low capacitance ESD protection device
which are highlighted below and in Figure 15.
• ESD7000 series: Zener diode based technology. This
technology has a higher breakdown voltage (VBR)
limiting it to protecting chipsets with larger geometries.
• ESD8000 series: Silicon controlled rectifier (SCR) type
technology. The key advatange for this technology is a
low holding voltage (VH) which produces a deeper
snapback that results in lower voltage over high
•
currents as shown in the TLP results in Figure 16. This
technology provides optimized protection for chipsets
with small geometries against thermal failures resulting
in chipset damage (also known as “hard failures”).
ESD8100 series: Low voltage punch through (LVPT)
type technology. The key advatange for this technology
is a very low turn-on voltage as shown in Figure 17.
This technology provides optimized protection for
chipsets with small geometries against recoverable
failures due to voltage peaks (also known as “soft
failures”).
Figure 15. ON Semiconductor’s Low-cap ESD Technology Portfolio
10
20
18
TLP Current (A)
14
6
12
10
4
8
SCR
6
LVPT
4
2
Zener
2
0
0
0
2
4
6
8
10
12
14
16
18
20
VC (V)
Figure 16. High Current, TLP, IV Characteristic of Each Technology
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10
Equivalent VIEC (kV)
8
16
ESD8116
1.00E−01
1.00E−02
SCR
1.00E−03
LVPT
1.00E−04
Zener
I (A)
1.00E−05
1.00E−06
1.00E−07
1.00E−08
1.00E−09
1.00E−10
1.00E−11
0
1
2
3
4
5
6
7
V (V)
Figure 17. Low Current, DC, IV Characteristic of Each Technology
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11
8
ESD8116
PACKAGE DIMENSIONS
UDFN8 2.0x1.2, 0.4P
CASE 517CX
ISSUE O
A
B
D
PIN ONE
REFERENCE
ÉÉÉ
ÉÉÉ
L1
E
0.10 C
2X
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
E
e
L
L1
L2
0.10 C TOP VIEW
2X
A
0.05 C
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
L
L
(A3)
0.05 C
A1
NOTE 4
C
SIDE VIEW
e
DETAIL A
2X
e
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
0.40
PITCH
8X
L2
0.25
1
6X
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
2.00 BSC
1.20 BSC
0.40 BSC
0.15
0.35
−−−
0.10
0.40
0.60
L
6X
0.40
PACKAGE
OUTLINE
1.40
8
e
e/2
BOTTOM VIEW
8X b
1
0.10 C A B
0.05 C
2X
0.65
NOTE 3
0.40
PITCH
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
Sales Representative
ESD8116/D
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