ESD8118 D

ESD8118
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8118 transient voltage suppressor is specifically designed
to protect four high speed data pairs from ESD. Ultra−low capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
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MARKING
DIAGRAM
ACMG
G
UDFN10
CASE 517CY
Features
• Low Capacitance (0.35 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
•
•
PIN CONFIGURATION
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• HDMI 1.3/1.4/2.0
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
I/O
I/O
I/O
10
9
8
7
1
2
3
4
5
6
I/O
GND
I/O
I/O
GND
I/O
ORDERING INFORMATION
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
I/O
Device
ESD8118MUTAG
Package
Shipping
UDFN10 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0
1
Publication Order Number:
ESD8118/D
ESD8118
I/O
Pin 1
I/O
Pin 3
I/O
Pin 4
I/O
Pin 6
I/O
Pin 7
I/O
Pin 8
I/O
Pin 9
I/O
Pin 10
Pin 2
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
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2
ESD8118
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IT
IPP
Parameter
Working Peak Voltage
RDYN
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
VCL VBR VRWM
V
IR
IT
Test Current
VHOLD
Holding Reverse Voltage
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
VCL
RDYN
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
IT = 1 mA, I/O Pin to GND
IR
VRWM = 3.3 V, I/O Pin to GND
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
VC
IPP = 8 A
IPP = −8 A
IPP = 16 A
IPP = −16 A
RDYN
Junction Capacitance
CJ
Typ
Max
Unit
3.3
V
I/O Pin to GND
Reverse Leakage Current
Dynamic Resistance
Min
4.0
5.0
V
1.0
mA
See Figures 2 and 3
V
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
8.5
−4.5
V
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
11.4
−8.0
I/O Pin to GND
GND to I/O Pin
0.35
0.44
VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins
and GND
0.30
0.15
0.37
W
0.35
0.20
0.47
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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3
90
10
80
0
70
−10
60
−20
VOLTAGE (V)
VOLTAGE (V)
ESD8118
50
40
30
−30
−40
−50
20
−60
10
−70
0
−80
−10
−20
0
20
40
60
80
100
120
−90
−20
140
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact
Clamping Voltage
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
140
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note AND8307/D
− Characterization of ESD Clamping Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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ESD8118
20
−20
10
8
−14
14
6
12
−12
6
−10
10
4
8
6
2
4
−8
4
−6
−4
2
−2
2
2
4
6
8
10 12
14
VC, VOLTAGE (V)
16
18
0
0
20
0
2
Figure 6. Positive TLP I−V Curve
NOTE:
4
6
8
10 12
14
VC, VOLTAGE (V)
16
0
20
18
Figure 7. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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EQUIVALENT VIEC (kV)
TLP CURRENT (A)
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
8
16
0
0
10
−18
18
ESD8118
1.E−01
1.0
1.E−02
0.9
1.E−03
0.8
1.E−04
0.7
C (pF)
1.E−05
I (A)
1.E−06
1.E−07
0.6
0.5
0.4
1.E−08
0.3
1.E−09
1.E−10
0.2
1.E−11
1.E−12
−2
0.1
0
−1
0
1
2
3
4
5
6
7
8
0
0.5
1.0
V (V)
1.5
2.0
2.5
3.0
3.5
VBias (V)
Figure 11. CV Characteristics
C_ESD8118_pF
dB (ESD8118..S(2,1))
Figure 10. IV Characteristics
Figure 12. RF Insertion Loss
Figure 13. Capacitance over Frequency
TABLE 1. RF Insertion Loss: Application Description
Interface
Data Rate (Gb/s)
Fundamental
Frequency (GHz)
3rd Harmonic
Frequency (GHz)
ESD8118 Insertion
Loss (dB)
HDMI 1.3/1.4
HDMI 2.0
3.9
6.0
1.7 (m1)
3.0 (m2)
5.1 (m3)
9.0 (m4)
m1 = 0.030
m2 = 0.091
m3 = 0.254
m4 = 0.803
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ESD8118
Without ESD8118
With ESD8118
Figure 14. HDMI2.0 Eye Diagram with and without ESD8118. 6 Gb/s
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ESD8118
HDMI Type−A
Connector
D2+
GND
ESD8118
D2−
D1+
GND
D1−
D0+
GND
D0−
CLK+
GND
CLK−
CEC
N/C (or HEC_DAT)
SCL
SDA
GND
5V
HPD (and HEC_DAT)
Top layer
Other layer
NUP4114
Figure 15. HDMI Layout Diagram
♦
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
• Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦
♦
Use curved traces when possible to avoid unwanted
reflections.
Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
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ESD8118
ESD Protection Device Technology
ON Semiconductor’s portfolio contains three main
technologies for low capacitance ESD protection device
which are highlighted below and in Figure 16.
• ESD7000 series: Zener diode based technology. This
technology has a higher breakdown voltage (VBR)
limiting it to protecting chipsets with larger geometries.
• ESD8000 series: Silicon controlled rectifier (SCR) type
technology. The key advatange for this technology is a
low holding voltage (VH) which produces a deeper
snapback that results in lower voltage over high
•
currents as shown in the TLP results in Figure 17. This
technology provides optimized protection for chipsets
with small geometries against thermal failures resulting
in chipset damage (also known as “hard failures”).
ESD8100 series: Low voltage punch through (LVPT)
type technology. The key advatange for this technology
is a very low turn-on voltage. This technology provides
optimized protection for chipsets with small geometries
against recoverable failures due to voltage peaks (also
known as “soft failures”).
Figure 16. ON Semiconductor’s Low-cap ESD Technology Portfolio
10
20
18
TLP Current (A)
14
6
12
10
4
8
SCR
6
LVPT
4
2
Zener
2
0
0
0
2
4
6
8
10
12
14
16
18
20
VC (V)
Figure 17. High Current, TLP, IV Characteristic of Each Technology
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Equivalent VIEC (kV)
8
16
ESD8118
PACKAGE DIMENSIONS
UDFN10 3.2x1.2, 0.5P
CASE 517CY
ISSUE O
A
B
D
PIN ONE
REFERENCE
0.10 C
2X
2X
ÉÉÉ
ÉÉÉ
0.10 C
L1
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
E
e
e1
L
L1
L2
TOP VIEW
A
(A3)
0.05 C
10X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
L
L
0.05 C
A1
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
3.20 BSC
1.20 BSC
0.50 BSC
0.80 BSC
0.15
0.35
−−−
0.10
0.40
0.60
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
2X
e
L2
0.835
10X
8X
0.40
0.28
1
8X
10
10X
e1/2
e1
L
PACKAGE
OUTLINE
1.40
b
0.10 C A B
0.05 C
1
NOTE 3
2X
0.4875
PITCH
BOTTOM VIEW
0.65
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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For additional information, please contact your local
Sales Representative
ESD8118/D
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