ESD8451 D

ESD8451, SZESD8451
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD8451 Series ESD protection diodes are designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
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MARKING
DIAGRAMS
Features
PIN 1
•
•
•
IEC 61000−4−2 (Level 4)
ISO10605 330 pF / 2 kW ±30 kV Contact
Low ESD Clamping Voltage
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
P, A
M
Typical Applications
X3DFN2
CASE 152AF
P
• Low Capacitance (0.30 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
XDFN2
CASE 711AM
AM
G
M
= Specific Device Code
= Date Code
PIN CONFIGURATION
AND SCHEMATIC
• USB 3.0
• MHL 2.0
• eSATA
1
2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
=
Rating
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 8
1
Publication Order Number:
ESD8451/D
ESD8451, SZESD8451
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IPP
Parameter
RDYN
Working Peak Voltage
IHOLD
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
VBR
VCVRWMVHOLD
IT
IR
V
Test Current
IR
IT
VHOLD
Holding Reverse Voltage
IHOLD
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IT
VHOLDVRWMVC
VBR
RDYN
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
−IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
5.5
7.9
VRWM = 3.3 V, I/O Pin to GND
Max
Unit
3.3
V
8.3
V
500
nA
Reverse Leakage Current
IR
Reverse Holding Voltage
VHOLD
I/O Pin to GND
2.05
V
Holding Reverse Current
IHOLD
I/O Pin to GND
17
mA
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
ESD8451MUT5G
Clamping Voltage
VC
IPP = 3.7 A, 8/20 ms pulse
13.7
V
ESD8451N2T5G
Clamping Voltage
VC
IPP = 5.0 A, 8/20 ms pulse
17.0
V
ESD8451MUT5G
Clamping Voltage
TLP (Note 2)
VC
IPP = 8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
11.0
IPP = 16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±8 kV Air)
19.0
IPP = 8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
9.0
IPP = 16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±8 kV Air)
16.0
ESD8451N2T5G
Clamping Voltage
TLP (Note 2)
VC
V
V
V
ESD8451MUT5G
Dynamic Resistance
RDYN
Pin1 to Pin2
Pin2 to Pin1
1.0
1.0
W
ESD8451N2T5G
Dynamic Resistance
RDYN
Pin1 to Pin2
Pin2 to Pin1
0.84
0.84
W
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz
0.20
0.30
pF
Junction Capacitance
CJ
VR = 0 V, f = 2.5 GHz
0.19
0.25
pF
1. For test procedure see Figure 16 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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2
ESD8451, SZESD8451
TYPICAL CHARACTERISTICS
Figure 1. ESD8451N2 ESD Clamping Voltage
Screenshot Negative 8kV Contact per IEC61000−4−2
Figure 2. ESD8451N2 ESD Clamping Voltage
Screenshot Positive 8kV Contact per IEC61000−4−2
Figure 3. ESD8451MU ESD Clamping Voltage
Screenshot Negative 8kV Contact per IEC61000−4−2
Figure 4. ESD8451MU ESD Clamping Voltage
Screenshot Positive 8kV Contact per IEC61000−4−2
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3
ESD8451, SZESD8451
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
C (pF)
C (pF)
TYPICAL CHARACTERISTICS
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0
−3.5
0.1
0
−3.5
−2.5
−1.5
−0.5
0.5
2.5
3.5
−2.5
−1.5
−0.5
0.5
1.5
2.5
3.5
VBIAS (V)
Figure 5. ESD8451MUT5G CV Characteristics
Figure 6. ESD8451N2T5G CV Characteristics
m1
2
m1
m2
0
0
−2
−2
−4
−4
(dB)
(dB)
1.5
VBIAS (V)
2
−6
m2
−6
−8
−8
−10
−10
−12
−12
−14
−14
1E7
1E8
1E7
1E10 3E10
1E9
1E8
1E9
1E10 3E10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. ESD8451MUT5G S21 Insertion Loss
Figure 8. ESD8451N2T5G S21 Insertion Loss
1.0
1.0
0.9
0.9
0.8
0.8
CAPACITANCE (pF)
CAPACITANCE (pF)
0.5
0.4
0.7
0.6
0.5
0.4
0.3
0.7
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0
0.1
0
1
2
3
4
5
6
7
8
9
1
10
2
3
4
5
6
7
8
9
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. ESD8451MUT5G Capacitance over
Frequency
Figure 10. ESD8451N2T5G Capacitance over
Frequency
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4
10
ESD8451, SZESD8451
TYPICAL CHARACTERISTICS
20
20
10
18
16
12
TLP CURRENT (A)
14
6
10
8
4
6
4
2
2
0
0
2
4
6
8
10
12
14
16
18
20
22
8
14
12
6
10
8
4
6
4
2
2
0
0
24
0
0
2
4
6
VC, VOLTAGE (V)
8
10
12
14
16
18
20
VC, VOLTAGE (V)
Figure 11. ESD8451MUT5G Positive TLP I−V
Curve
−20
Figure 12. ESD8451N2T5G Positive TLP I−V
Curve
10
−20
10
−18
−18
6
−10
−8
4
−6
−4
TLP CURRENT (A)
−14
−12
−16
2
−2
0
0
2
4
6
8
10
12
14
16
18
20
22
8
VIEC, EQUIVALENT (kV)
8
VIEC, EQUIVALENT (kV)
−16
TLP CURRENT (A)
VIEC, EQUIVALENT (kV)
8
VIEC, EQUIVALENT (kV)
16
TLP CURRENT (A)
10
18
−14
−12
6
−10
−8
4
−6
−4
2
−2
0
0
24
0
0
VC, VOLTAGE (V)
2
4
6
8
10
12
14
16
18
20
VC, VOLTAGE (V)
Figure 13. ESD8451MUT5G Negative TLP I−V
Curve
Figure 14. ESD8451N2T5G Negative TLP I−V
Curve
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5
ESD8451, SZESD8451
Latch−Up Considerations
stable operating point of the circuit and the system is
therefore latch−up free. In the non−latch up free load line
case, the IV characteristic of the snapback protection device
intersects the load−line in two points (VOPA, IOPA) and
(VOPB, IOPB). Therefore in this case, the potential for
latch−up exists if the system settles at (VOPB, IOPB) after a
transient. Because of this, ESD8451 should not be used for
HDMI applications – ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch−up. Please refer to Application Note AND9116/D for
a more in−depth explanation of latch−up considerations
using ESD8000 series devices.
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap−back, SCR type structure. By using
this technology, the potential for a latch−up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch−up free applications and applications with the
potential for latch−up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch−up free load line case, the IV
characteristic of the snapback protection device intersects
the load−line in one unique point (VOP, IOP). This is the only
ESD8451 Latch*up free:
USB 2.0 LS/FS, USB 2.0 HS,
USB 3.0 SS, DisplayPort
ESD8451 Potential Latch*up:
HDMI 1.4/1.3a TMDS
Figure 15. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 1.4/1.3a TMDS
3.465
54.78
1.0
ESD8104, ESD8040
USB 2.0 LS/FS
3.301
1.76
1.0
ESD8004, ESD8451
USB 2.0 HS
0.482
N/A
1.0
ESD8004, ESD8451
USB 3.0 SS
2.800
N/A
1.0
ESD8004, ESD8006, ESD8451
DisplayPort
3.600
25.00
1.0
ESD8004, ESD8006, ESD8451
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6
ESD8451, SZESD8451
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 16. IEC61000−4−2 Spec
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 17. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 18 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 17. Simplified Schematic of a Typical TLP
System
Figure 18. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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7
ESD8451, SZESD8451
ORDERING INFORMATION
Package
Shipping†
ESD8451N2T5G,
SZESD8451N2T5G*
XDFN2
(Pb−Free)
8000 / Tape & Reel
ESD8451MUT5G
X3DFN2
(Pb−Free)
10000 / Tape & Reel
SZESD8451MUT5G*
X3DFN2
(Pb−Free)
15000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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8
ESD8451, SZESD8451
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
D
PIN 1
INDICATOR
(OPTIONAL)
DIM
A
A1
b
D
E
e
L2
E
TOP VIEW
0.05 C
MILLIMETERS
MIN
MAX
0.25
0.33
−−−
0.05
0.22
0.28
0.58
0.66
0.28
0.36
0.355 BSC
0.17
0.23
A
RECOMMENDED
MOUNTING FOOTPRINT*
0.05 C
2X
A1
SIDE VIEW
C
SEATING
PLANE
0.74
1
e
2X
1
b
2
2X
2X
0.05
M
2X
0.30
0.05
L2
M
0.31
DIMENSIONS: MILLIMETERS
C A B
See Application Note AND8398/D for more mounting details
C A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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9
ESD8451, SZESD8451
PACKAGE DIMENSIONS
XDFN2 1.0x0.6, 0.65P (SOD−882)
CASE 711AM
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
0.10 C
ÉÉ
ÉÉ
A B
D
PIN 1
INDICATOR
E
DIM
A
A1
b
D
E
e
L
0.05 C
TOP VIEW
NOTE 3
0.10 C
A
0.10 C
A1
C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.34
0.44
−−−
0.05
0.43
0.53
1.00 BSC
0.60 BSC
0.65 BSC
0.20
0.30
RECOMMENDED
SOLDER FOOTPRINT*
SEATING
PLANE
1.20
2X
e
2X
0.47
0.60
b
e/2
0.05
M
PIN 1
C A B
1
DIMENSIONS: MILLIMETERS
2X
L
0.05
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
C A B
BOTTOM VIEW
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ESD8451/D
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