LV56851UV D

LV56851UV
Linear Voltage Regulator, Multiple-Output,
System Power Supply IC,
for Automotive Infotainment System
Overview
The LV56851UV is a multiple output linear voltage regulator IC, which allows
reduction of quiescent current. The LV56851UV is specifically designed to
address automotive infotainment systems power supply requirements.
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The LV56851UV integrates 5 linear regulator outputs, 1 high side power switch,
I2C-bus communication, ACC detection, battery voltage detection, over-current
limiter, overvoltage protection and thermal shut down.
Features
• Low consumption current: 60A (typ, VDD output is in operation)
• 5 regulator outputs
VDD for microcontroller: 3.3 V,Iomax: 300 mA
For system: 3.3/5 V, Iomax: 300 mA
For audio: 5/8.5/9/12 V, Iomax: 400 mA
For illumination: 8/9/10.5/12 V, Iomax: 300 mA
For CD: 5/6/7/8 V, Iomax: 1500 mA
• 1 high side switch
AMP: Imax: 500 mA, voltage difference between input and output: 0.75 V
• ACC detection circuit
Detection Voltage 2.7/3.2/3.6/4.2 V
• Battery voltage detection (BDET) : VCC2
Low voltage detection(UVDET): 6.5/7.5(hys=0.5 V or 1.5 V)/8 V
Over voltage detection(OVDET): detection voltage 18 V
• I2C-bus communication interface
Each output except VDD is independently enabled/disabled.
SYS/ILM/CD/AUDIO/ACC/UV voltage setting.
Read back supported: Output voltage setting, Output over-current,
Detections(ACC/UV/OVDET/OVP/TWARN)
• RESET
Detection Voltage 2.8 V(typ, 0.85*VDD), N-MOS Open-Drain output
• Supply input
VCC1: For internal reference voltage, control circuitry, VDD output.
VCC2: For AUDIO/ILM/CD/AMP/SYS
• Over-current protection
• Overvoltage protection(OVP): VCC1,VCC2 Typ 21 V
(All outputs except VDD are turned off)
• Thermal shutdown: Typ 175°C , Thermal Warning: Typ 140°C
• Package : HZIP15
• AEC-Q100 (Grade 3) Qualified and PPAP capable
HZIP15
ORDERING INFORMATION
Ordering Code:
LV56851UV-XH
Package
HZIP15
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
720 / Tube
Typical Applications
• Automotive infotainment
* I2C Bus is a trademark of Philips Corporation.
© Semiconductor Components Industries, LLC, 2016
April 2016- Rev. 0
1
Publication Order Number:
LV56851UV/D
LV56851UV
BLOCK DIAGRAM
VCC1
8
VDD
11
-
VREF
OVP
3.3 V, 0.3 A
+
5.1 V
VREG
VREF
VREF
1.25 V
SYS_EN
SYS
9
3.3 V/5 V, 0.3 A
-
+
TSD/
TWARN
VCC2
7
VREF
OVP
ILM_EN
ILM
3
8/9/10.5/12 V, 0.3 A
-
+
2 GND
VDD
VDD
RSTB
13
RESET
AUDIO
4
VREF
5/8.5/9/12 V, 0.4 A
-
AUDIO_EN
+
FILT
VDD
VDD
SCL
VREF
10
CD_EN
SDA
12
OVP
-
+
I2C-bus
CTL
AMP
1
TSD
UV
OV
ACCIN
VDD
UVDET
BDET
OVDET
6
VCC2-0.75 V, 0.5 A
CTRL
AMP_EN
OVP→All Output OFF
except VDD
TSD→All Output OFF
ACC
CD
5/6/7/8 V, 1.5 A
5
14
OVP
BDET
VDD
ACCDET
15
VREF
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LV56851UV
PIN EQUIVALENT CIRCUITS
Pin #
Pin name
Function
Equivalent circuit
VCC2
7
1
AMP
AMP output
VCC2-0.75 V
1
GND
2
2
GND
GND
VCC2
7
3
ILM
ILM output
20.9~33.4kΩ 180kΩ
3
8 V~12 V
2
1kΩ
GND
VCC2
7
4
180kΩ
AUDIO
5 V~12 V
20.9~60kΩ
4
AUDIO output
1kΩ
GND
2
VCC2
7
5
CD output
180kΩ
CD
5 V~8 V
33.3~60kΩ
5
2
1kΩ
GND
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LV56851UV
Continued from preceding page
Pin #
Pin name
Function
Equivalent circuit
ACCIN
ACC detection input
36~78kΩ
6
90kΩ
6
2
7
VCC2
Supply terminal
8
VCC1
Supply terminal
GND
VCC2
VCC1
7
8
GND
2
VCC2
7
9
230/420kΩ
SYS
3.3 V/5 V
1kΩ
140kΩ
9
SYS output
GND
2
8
VCC1
VDD
11
10
SCL
I2C-bus clock input
1kΩ
10
2
GND
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LV56851UV
Continued from preceding page
Pin #
Pin name
Function
Equivalent circuit
VCC1
8
VDD output
11
230kΩ
VDD
3.3 V
140kΩ
11
GND
2
VDD
11
12
SDA
100Ω
2
I C-bus data input
1kΩ
12
GND
2
VDD
11
RESET
13
100Ω
RSTB
Open-drain output
GND
2
14
BDET
VDD
11
BDET output
1kΩ
13
14
100Ω
15
15
ACCDET
ACCDET output
2
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GND
LV56851UV
MAXIMUM RATINGS / Ta = 25C
Parameter
(Note 1)
Symbol
Conditions
Ratings
Unit
Supply voltage
Vcc max
VCC1,VCC2
36
V
Input voltage
Vio max
SDA,SCL,ACCDET,BDET,RSTB,SYS,VDD
ILM,AUDIO,CD
ACCIN, AMP
7
14
36
V
Allowable power
dissipation
Pd max
Ta ≤ 25°C
-Independent IC
-Al heatsink (50 * 50 * 1.5 mm3) is used
-Size of heatsink: infinite
1.3
5.3
26
W
Peak supply voltage
Vcc peak
VCC1/VCC2/ACCIN
• See the test waveform below
50
V
Topr
-40 to +85
°C
Tstg
Tjmax
-55 to +150
+150
°C
°C
Operating ambient
temperature
Storage temperature
Junction temperature
1. Stresses exceeding those listed in the Absolute Maximum Rating table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur and reliability may be affected.
• Waveform of surge test (VCC1,VCC2,ACCIN)
50V
90%
10%
16V
5msec
100ms
• Allowable power dissipation derating curve
HZIP15
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(a) Independent IC
(b)Aluminum heat-sink (50×50×1.5 mm3)
Heat-sink tightening condition
tightening torque: 39 N•cm ,
with silicone grease
LV56851UV
RECOMMENDED OPERATING RANGES at Ta = 25C (Note 2)
■VCC1
Parameter
Symbol
Operating supply voltage1
Conditions
Ratings
VCCop1 VDD output
Unit
7 to 16
V
■VCC2
Parameter
Symbol
Conditions
Ratings
ILM(10.5 V) output
Unit
12.5 to 16
Operating supply voltage2
VCCop2
Operating supply voltage3
VCCop3 AUDIO(8.5 V) output
Operating supply voltage4
VCCop4
Operating supply voltage5
VCCop5 AMP output
7.5 to 16
V
Operating supply voltage6
VCCop6 SYS output
7.5 to 16
V
ILM(8 V) output
10 to 16
9.5 to 16
CD(8V) output(Io=1.5 A)
10.5 to 16
CD(8V) output(Io≤ 1 A)
10 to 16
V
V
V
2. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
• “Maximum Rating” and “Recommended operating range”
VCC2
VCC1
Out-of-Rating
36 V
disabled(OVP)
21 V
20.5 V
operating1
16 V
14V
10V
9.5V
9V
8V
ILM
CD(Io≤1 A)
(*) Each lower limit value is determined by “Output voltage”-“Dropout voltage”.
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recommended
operation
range
operating2(*)
drop out
region
Vo=7 V
Vo=8 V
Vo=5 V
Vo=8.5 V
Vo=9 V
Vo=8 V
Vo=9 V
Vo=12 V
Vo=12 V
AUDIO
7.5V 7.5V
Vo=5 V
10V
7.5V
Vo=10.5 V
SYS
Vo=5 V
VDD
10V
7.5V
Vo=3.3 V
7V
13V
11V
Vo=6 V
12.5V
AMP
LV56851UV
ELECTRICAL CHARACTERISTICS at Ta  25C(Note 4), VCC1=VCC2=14.4 V unless otherwise noted. (Note 3)
Parameter
Quiescent current
Symbol
Icc
Conditions
Min
VDD w/out load, ACCIN=0V
2
I C register Gr0/Gr1/Gr2=00h
Typ
Max
Unit
60
100
μA
3.3
3.47
V
VDD output (3.3 V)
Output voltage
Vo1
Io1=200 mA
3.13
Output current
Io1
Vo1≥ 3.1 V
300
Line regulation
∆VoLN1
Load regulation
Dropout voltage
Ripple rejection (Note 5)
30
90
mV
∆VoLD1 1 mA<Io1<200 mA
70
150
mV
VDROP1 Io1=200 mA
0.5
1.0
V
RREJ1
7.5 V<VCC1<16 V, Io1=200 mA
mA
f=120 Hz, VCC1=0.5 Vpp
Io1=200 mA
40
50
2.7
2.8
dB
RESET
Reset voltage
Vrst0
VDD falling
2.94
V
Vrst
As a ratio of Vo1, VDD falling
85
%
As a ratio of Vo1
1.6
%
Hysteresis voltage
Vrshs
Detection Delay1
Td1
H to L, VDD=Vrst+0.4 V to Vrst-0.4 V
25
μsec
Detection Delay2
Td2
L to H, VDD=Vrst-0.4 V to Vrst+0.4 V
100
μsec
SYS output (3.3 V/5 V) ; SYS_EN=1
Output voltage 1
Vo21
Io2=200 mA, SYS_V=0
3.13
3.3
3.47
V
Output voltage 2
Vo22
Io2=200 mA, SYS_V=1
4.75
5.0
5.25
V
Io2
Vo21≥3.1 V, Vo22≥4.7 V
300
Output current
mA
Line regulation
∆VoLN2 7.5 V<VCC2<16 V, Io2=200 mA
30
90
mV
Load regulation
∆VoLD2 1 mA<Io2<200 mA
70
150
mV
Dropout voltage
VDROP2 Io2=200 mA
0.4
0.8
V
Ripple rejection (Note 5)
RREJ2
f=120 Hz, VCC2=0.5 Vpp
Io2=200 mA
40
50
dB
ILM output (8-12 V); ILM_EN=1
Output voltage 1
Vo31
Io3=200 mA, ILM_V[1:0]=00
7.6
8.0
8.4
V
Output voltage 2
Vo32
Io3=200 mA, ILM_V[1:0]=01
8.55
9.0
9.45
V
Output voltage 3
Vo33
Io3=200 mA, ILM_V[1:0]=10
9.97
10.5
11.03
V
Output voltage 4
Vo34
Io3=200 mA, ILM_V[1:0]=11
11.4
12
12.6
V
Output current
Io3
300
mA
Line regulation
∆VoLN3 Vo+2 V<VCC2<16 V, Io3=200 mA
30
90
mV
Load regulation
∆VoLD3 1 mA<Io3<200 mA
70
150
mV
Dropout voltage
VDROP3 Io3=200 mA
0.6
1.05
V
Ripple rejection (Note 5)
RREJ3
f=120 Hz ,Io3=200 mA
40
50
dB
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LV56851UV
Continued from preceding page
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CD output (5-8 V); CD_EN=1
Output voltage 1
Vo41
Io4=1000 mA, CD_V[1:0]=00
4.75
5.0
5.25
V
Output voltage 2
Vo42
Io4=1000 mA, CD_V[1:0]=01
5.7
6.0
6.3
V
Output voltage 3
Vo43
Io4=1000 mA, CD_V[1:0]=10
6.65
7.0
7.35
V
Output voltage 4
Vo44
Io4=1000 mA, CD_V[1:0]=11
7.6
8.0
8.4
V
Output current
Io4
Line regulation
∆VoLN4
Vo+2 V<Vcc2<16 V,Io4=1000 mA
50
100
mV
Load regulation
∆VoLD4
10 mA<Io4<1000 mA
100
200
mV
Dropout voltage 1
VDROP4
Io4=1000 mA
0.9
1.5
V
Dropout voltage 2
VDROP4’
Io4=500 mA
0.45
0.75
V
Ripple rejection
(Note 5)
RREJ4
Vo41≥4.7 V, V44≥7.6 V
f=120 Hz ,Io4=1000 mA
1500
mA
40
50
dB
AUDIO output (5-12 V); AUDIO_EN=1
Output voltage 1
Vo51
Io5=200 mA, AUD_V[1:0]=00
4.75
5.0
5.25
V
Output voltage 2
Vo52
Io5=200 mA, AUD_V[1:0]=01
8.13
8.5
8.87
V
Output voltage 3
Vo53
Io5=200 mA, AUD_V[1:0]=10
8.55
9.0
9.45
V
Output voltage 4
Vo54
Io5=200 mA, AUD_V[1:0]=11
11.4
12
12.6
V
Output current
Io5
Line regulation
∆VoLN5
Vo+1 V<VCC2<16 V,Io5=200 mA
30
90
mV
Load regulation
∆VoLD5
1 mA<Io5<200 mA
70
150
mV
Dropout voltage
VDROP5
Io5=200 mA
0.3
0.6
V
Ripple rejection
(Note 5)
RREJ5
400
f=120 Hz, Io5=200 mA
mA
40
50
dB
Vcc2-1.5
Vcc2-0.75
V
AMP HS-SW; AMP_EN=1
Output voltage
Vo6
Io6=500 mA
Output current
Io6
Vo6≥VCC2-1.5 V
500
mA
ACC detection
Detection voltage 1
Vacc1
ACC_V[1:0]=00, ACCIN falling
2.62
2.7
2.78
V
Detection voltage 2
Vacc2
ACC_V[1:0]=01, ACCIN falling
3.1
3.2
3.3
V
Detection voltage 3
Vacc3
ACC_V[1:0]=10, ACCIN falling
3.49
3.6
3.71
V
Detection voltage 4
Vacc4
ACC_V[1:0]=11, ACCIN falling
4.07
4.2
4.33
V
Release voltage 1
Vaccr1
ACC_V[1:0]=00, ACCIN rising
2.81
2.9
2.99
V
Release voltage 2
Vaccr2
ACC_V[1:0]=01, ACCIN rising
3.3
3.4
3.5
V
Release voltage 3
Vaccr3
ACC_V[1:0]=10, ACCIN rising
3.68
3.8
3.92
V
Release voltage 4
Vaccr4
ACC_V[1:0]=11, ACCIN rising
4.26
4.4
4.54
V
Threshold hysteresis
Vachs
0.2
V
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LV56851UV
Continued from preceding page
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Under-Voltage detection(UVDET)
detection voltage 1
Vuv1
VCC2 falling, UVD_V[1:0]=00
6.3
6.5
6.7
V
detection voltage 2
Vuv2
VCC2 falling, UVD_V[1:0]=01
7.27
7.5
7.73
V
7.5
7.73
V
detection voltage 3
Vuv3
VCC2 falling, UVD_V[1:0]=10
7.27
detection voltage 4
Vuv4
VCC2 falling, UVD_V[1:0]=11
7.76
8.0
8.24
V
7.0
7.21
V
release voltage 1
Vuvr1
VCC2 rising, UVD_V[1:0]=00
6.79
release voltage 2
Vuvr2
VCC2 rising, UVD_V[1:0]=01
7.76
8.0
8.24
V
9.0
9.27
V
8.5
8.76
V
release voltage 3
Vuvr3
VCC2 rising, UVD_V[1:0]=10
8.73
release voltage 4
Vuvr4
VCC2 rising, UVD_V[1:0]=11
8.24
detection hysteresis 1
Vuvhs1
UVD_V[1:0]=00
0.5
detection hysteresis 2
Vuvhs2
UVD_V[1:0]=01
0.5
V
detection hysteresis 3
Vuvhs3
UVD_V[1:0]=10
1.5
V
UVD_V[1:0]=11
0.5
V
detection hysteresis 4
Vuvhs4
V
Over-Voltage detection(OVDET)
detection voltage
Vovd
detection hysteresis
Vodhys
VCC2 rising
17
18
19
V
0.5
V
21
V
0.5
V
Over-Voltage protection(OVP)
detection voltage
Vovp
detection hysteresis
Vovhys
VCC1/VCC2 rising, output disabled
CMOS Output(ACCDET, BDET)
“H” voltage
VflgH
Isource=1 mA
“L” voltage
VflgL
Isink=1 mA
Input “L” voltage
Vilrs
Internal circuit reset
Input “H” voltage
Vihrs
Internal circuit reset released
“L” voltage
VrsbL
Isink=1 mA
VDD-0.3
VDD
V
0.3
0.4
V
0.4
V
VDD
VDD+0.3
V
0.3
0.4
V
0.4
V
VDD
VDD+0.3
V
0.3
0.4
V
RSTB :
0
2.8
2
I C-bus I/F; SCL,SDA
Input “L” voltage
Vils
0
Input “H” voltage
Vihs
2.8
SDA “L” voltage
Vols
Isink=1 mA, ACK or data read
3. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. All the specification is defined based on the tests performed under the conditions where Tj and Ta(=25°C) are almost equal. These tests
were performed with pulse load to minimize the increase of junction temperature (Tj).
5. Guaranteed by design
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LV56851UV
TYPICAL CHARACTERISTICS
Standby Current (Icc)
Standby Current (Icc)
80
800
75
700
70
600
500
60
55
VCC=7V
50
Icc (uA)
Icc (uA)
65
400
300
VCC=14.4V
45
VCC=16V
-45°C
25°C
200
85°C
40
110°C
100
35
0
30
-50
0
50
0
100
5
10
15
20
25
30
35
40
VCC1,VCC2 (V)
temp(deg.)
RESET detection hysteresis
RESET Voltage
3
87
86.5
2.5
86
2
Vrshs (%)
Vrst (%)
85.5
85
84.5
1.5
84
1
83.5
83
0.5
82.5
0
82
-50
0
50
-50
100
0
50
100
temp(deg.)
temp(deg.)
RESET Detection Voltage
RESET Detection Delay (Td1)
2.95
35
33
2.9
Td1 (us)
31
Vreset(V)
2.85
2.8
29
27
25
23
2.75
21
2.7
19
-50
0
50
100
-50
temp(deg.)
RESET Detection Delay (Td2)
130
Td2 (us)
120
110
100
90
80
70
0
50
50
temp(deg.)
140
-50
0
100
temp(deg.)
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100
LV56851UV
ACC Under Voltage Detection2, detection voltage
Under Voltage Detection2, detection voltage
8.2
3.6
8.1
3.5
Vuv2, Vuvr2 (V)
Vacc2, Vaccr2 (V)
8
3.4
Vacc2
Vaccr2
3.3
7.9
Vuv2
7.8
Vuvr2
7.7
3.2
7.6
3.1
7.5
3
7.4
-50
0
50
-50
100
0
100
Over Voltage Protection, detection voltage
Over Voltage Detection, detection voltage
22
18.4
18.2
Vovd
Vovp
21.5
Vovp_r
Vovd_r
18
21
17.8
Vovp (V)
Vovd (V)
50
temp(deg.)
temp(deg.)
17.6
20.5
17.4
20
17.2
19.5
17
-50
0
50
-50
100
0
[VDD] Output voltage (Io=200mA)
3.4
50
100
temp(deg.)
temp(deg.)
[VDD] Dropout voltage (Io=200mA)
0.8
3.38
VCC1=14.4V
3.34
0.6
VCC1=16V
Vdrop (V)
3.32
Vo (V)
0.7
VCC1=7V
3.36
3.3
3.28
0.5
0.4
3.26
3.24
0.3
3.22
3.2
-50
0
50
0.2
100
-50
0
50
100
temp(deg.)
temp(deg.)
[VDD] Output current vs Output voltage (VCC1=14.4V)
[VDD] Ripple Rejection vs frequency (Io=200mA, T=25°C)
4
100
3.5
90
3
80
VCC=7V
VCC=14.4V
VCC=16V
70
60
(dB)
Vo (V)
2.5
2
-45°C
25°C
85°C
1.5
1
50
40
30
110°C
20
0.5
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
10
Io (A)
100
1000
Frequency (Hz)
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10000
100000
LV56851UV
[SYS(3.3V)] Output voltage (Io=200mA)
3.4
[SYS(3.3V)] Dropout voltage (Io=200mA)
0.7
3.38
0.6
3.36
3.34
0.5
Vdrop (V)
Vo (V)
3.32
3.3
3.28
VCC2=7.5V
3.26
0.4
0.3
VCC2=14.4V
3.24
0.2
VCC2=16V
3.22
3.2
0.1
-50
0
50
-50
100
0
temp(deg.)
100
[SYS(3.3V)] Ripple Rejection vs frequency (Io=200mA, T=25°C)
[SYS(3.3V)] Output current vs Output voltage (VCC2=14.4V)
4
50
temp(deg.)
100
90
3.5
VCC=7.5V
80
3
2.5
VCC=16V
60
(dB)
Vo (V)
VCC=14.4V
70
2
-45°C
1.5
40
25°C
1
50
85°C
30
110°C
20
0.5
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.8
10
100
1000
Io (A)
[ILM(8V)] Output voltage (Io=200mA)
8.2
10000
100000
Frequency (Hz)
[ILM(8V)] Dropout voltage (Io=200mA)
0.9
8.15
0.8
8.1
0.7
Vdrop (V)
Vo (V)
8.05
8
7.95
VCC2=10V
7.9
VCC2=16V
0.3
7.8
-50
10
0
temp(deg.)
50
0.5
0.4
VCC2=14.4V
7.85
0.6
0.2
100
-50
0
50
[ILM(8V)] Ripple Rejection vs frequency (Io=200mA, T=25°C)
[ILM(8V)] Output current vs Output voltage (VCC2=14.4V)
80
9
70
8
VCC=10V
VCC=14.4V
60
7
VCC=16V
50
(dB)
6
Vo (V)
100
temp(deg.)
5
40
-45°C
4
30
25°C
3
85°C
2
20
110°C
10
1
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
10
100
1000
Frequency (Hz)
Io (A)
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13
10000
100000
LV56851UV
[CD(8V)] Output voltage (Io=1A)
8.2
1.3
8.15
1.2
8.1
1.1
1
Vdrop (V)
Vo (V)
8.05
8
7.95
VCC2=10V
7.9
0.8
0.6
VCC2=16V
0.5
7.8
0.4
-50
0
temp(deg.)
50
100
-50
[CD(8V)] Output current vs Output voltage (VCC2=14.4V)
9
0
temp(deg.)
50
100
[CD(8V)] Ripple Rejection vs frequency (Io=1000mA, T=25°C)
90
8
80
7
70
6
60
5
50
(dB)
Vo (V)
0.9
0.7
VCC2=14.4V
7.85
4
2
1
VCC=10V
VCC=14.4V
VCC=16V
40
-45°C
25°C
85°C
110°C
3
30
20
10
0
0
0.5
1
Io (A)
1.5
2
0
2.5
10
100
1000
10000
AUDIO Dropout Voltage (Io=200mA)
0.45
8.65
0.4
VCC2=9.5V
8.6
VCC2=14.4V
0.35
VCC2=16V
Vdrop (V)
8.55
8.5
8.45
0.3
0.25
0.2
8.4
0.15
8.35
0.1
8.3
-50
0
50
-50
100
0
temp(deg.)
temp(deg.)
50
100
[AUDIO] Ripple Rejection vs frequency (Io=200mA, T=25°C)
[AUDIO(8.5V)] Output current vs Output voltage (VCC2=14.4V)
10
80
9
70
8
VCC=7.5V
VCC=14.4V
60
VCC=16V
7
50
(dB)
6
Vo (V)
100000
Frequency (Hz)
[AUDIO(8.5V)] Output voltage (Io=200mA)
8.7
Vo (V)
[CD(8V)] Dropout voltage (Io=1A)
1.4
5
-45°C
25°C
85°C
110°C
4
3
2
40
30
20
10
1
0
0
0
0.2
0.4
Io (A)
0.6
0.8
1
10
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14
100
1000
Frequency (Hz)
10000
100000
LV56851UV
[AMP] Output drop voltage (Io=500mA)
1
14
0.9
12
0.8
10
0.7
Vo (V)
Vo (V)
[AMP] Output current vs Output voltage (VCC2=14.4V)
16
0.6
6
VCC2=7.5V
0.5
VCC2=14.4V
VCC2=16V
0.4
-45°C
25°C
85°C
110°C
8
4
2
0
0.3
-50
0
50
100
0
0.2
0.4
0.6
Io (A)
temp(deg.)
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15
0.8
1
1.2
LV56851UV
I2C-bus Interface timing
Parameter
min
Symbol
typ
max
unit
400
kHz
SCL clock frequency
fSCL
0
START condition hold time
tHD;STA
0.6
us
SCL “L” pulse-width
tLOW
1.3
us
SCL “H” pulse-width
tHIGH
0.6
us
DATA hold time
tHD;DAT
0
us
DATA setup time
tSU;DAT
0.1
us
SDA/SCL rise time
tr
0.3
us
SDA/SCL fall time
tf
0.3
us
STOP condition setup time
tSU;STO
0.6
us
Bus free time
tBUF
1.3
us
between STOP and START condition
Bus line load capacitance
Cb
400
SDA
tf
tSU;DAT
tLOW
tr
tr
tBUF
tf
SCL
tHD;STA
ST
tHD;DA
tHIGH
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16
tSU;STO SP
ST
pF
LV56851UV
I2C-bus interface format (MSB first)
This part is I2C controlled power supply, using 2 wires
of SCL,SDA.
The
communication
protocol
comprises
start-condition, device-address, sub-address, data and
stop-condition.
Every 8 bits are followed by ACK bit, and the receiver
device pulls down SDA line during ACK period.
This part doesn't accept sub-address auto increment
format. (Single data byte write per a communication.)
The protocol in Read-mode comprises start-condition,
device-address, data1, data2 and stop-condition.
(Note)The I2C-bus communication may be unstable
when VDD voltage is not stable or out of specification
range, since I2C-BUS circuitry is supplied by VDD.
Write mode
SCL
SDA
S6 S5 S4 S3 S2 S1 S0 W AK A7 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Sub Address(A) + ACK
Device Address + R/W + ACK
Start
Condition
Data(address A) + ACK
Stop
Condition
Read mode
SCL
SDA
S6 S5 S4 S3 S2 S1 S0 R AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Start
Condition
Device Address + R/W + ACK
Read data1 + ACK
Read data2 + ACK
Stop
Condition
• Device address
S6
S5
S4
S3
S2
S1
S0
R/W
0
0
0
1
0
0
0
1/0
• Register map
Write
D7
D6
D5
D4
D3
D2
D1
D0
init
PM
ILM_EN
CD_EN
AUDIO_EN
SYS_EN
AMP_EN
0
0
0
00000000
VCTL
ILM_V1
ILM_V0
CD_V1
CD_V0
AUD_V1
AUD_V0
SYS_V
0
00000000
DET
ACC_V1
ACC_V0
UVD_V1
UVD_V0
BDETMD
0
(Reserved)
00000000
Read
VCTL
FLG
D15
D14
D13
D12
D11
D10
D9
D8
init
ILM_V1
ILM_V0
CD_V1
CD_V0
AUD_V1
AUD_V0
SYS_V
0
00000000
D7
D6
D5
D4
D3
D2
D1
D0
init
ACCUV
UV
OV
OVP
TWARN
OC
0
0
00000000
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17
LV56851UV
Write Register explanation
ADR
bit
Name
init
00h
7
ILM_EN
0
ILM output enable 1: ON 0: OFF
6
CD_EN
0
CD output enable 1: ON 0: OFF
5
AUDIO_EN
0
AUDIO output enable 1: ON 0: OFF
4
SYS_EN
0
SYS output enable 1: ON 0: OFF
3
AMP_EN
0
AMP output enable 1: ON 0: OFF
2
0
1
0
0
0
ADR
bit
01h
[7:6]
ILM_V[1:0]
00
ILM output voltage(*) 11: 12 V 10: 10.5 V 01: 9 V 00: 8 V
[5:4]
CD_V[1:0]
00
CD output voltage(*) 11: 8 V 10: 7 V 01: 6 V 00: 5 V
[3:2]
AUD_V[1:0]
00
AUDIO output voltage(*) 11: 12 V 10: 9 V 01: 8.5 V 00: 5 V
0
SYS output voltage(*) 1: 5 V 0: 3.3 V
1
Name
Description
SYS_V
0
init
Description
0
(*) “Output voltage setting” is only valid when corresponding output is set disabled(xxx_EN=0). It is ignored when the output is
set enabled(xxx_EN=1).
ADR
bit
Name
init
Description
02h
[7:6]
ACC_V[1:0]
00
ACC detection voltage 11: 4.2 V 10: 3.6 V 01: 3.2 V 00: 2.7 V
[5:4]
UVD_V[1:0]
00
UVDET detection voltage
11: 8 V 10: 7.5 V(9 V) 01: 7.5 V(8 V) 00: 6.5 V
3
BDETMD
2
[1:0]
0
BDET output mode 1: BDET/TWARN 0: BDET only
0
(Reserved)
00
(For TEST) Must be set to “00” for normal use.
Read Register explanation
ADR
bit
Name
init
Description
[15:14]
ILM_V[1:0]
00
ILM output voltage 11: 12 V 10: 10.5 V 01: 9 V 00: 8 V
[13:12]
CD_V[1:0]
00
CD output voltage 11: 8 V 10: 7 V 01: 6 V 00: 5 V
[11:10]
AUD_V[1:0]
00
AUDIO output voltage 11: 12 V 10: 9 V 01: 8.5 V 00: 5 V
SYS_V
0
SYS output voltage 1: 5 V 0: 3.3 V
9
8
0
7
ACCUV
0
ACC detection
6
UV
0
Under voltage detection 1: Under voltage 0: Normal
5
OV
0
Over voltage detection 1: Over Voltage 0: Normal
4
OVP
0
Over voltage protection 1: Over Voltage Protection 0: Normal
3
TWARN
0
Thermal Warning 1: High temperature 0: Normal
2
OC
0
Output Over Current
1
0
0
0
1: Under voltage 0: Nornmal
1: Over current 0: Normal
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18
LV56851UV
FUNCTIONAL DESCRIPTION
[Standby mode]
When VCC1 is applied, internal control circuitry is
automatically reset and goes into Stand-by mode.
In Stand-by mode, following functions are active.
VDD(3.3 V) output
I2C-bus communication
Over voltage
protection(OVP)/UVDET/OVDET/ACC
detection/BDET output
Thermal shutdown(TSD)
[VCC1/VCC2]
VCC1 input is necessary for any operation of this
device since VCC1 supplies VDD and common
circuitry such as reference voltage, internal control
circuitry.
VCC2 is the supply for AUDIO/ILM/CD/AMP/SYS
outputs.
LV56851UV can tolerate up to 50 V peak surge
voltage on VCC1/2 or ACCIN, but for more safety
design, adding power clamp such as power zener
diode on battery connected line is recommended in
order to absorb applied surge.
LV56851UV has no protection against battery reverse
connection. If a negative voltage input is possible,
adding Schottky diode between VCC and GND is
recommended to protect the device from the negative
voltage.
[Controls]
The functions of LV56851UV can be controlled via
I2C-bus. See “I2C bus interface format” term for
details.
[Linear Regulators]
VDD output
When VCC1 is applied, VDD output is active
regardless of control states.
SYS/CD/AUDIO/ILM output
These outputs are individually enabled or disabled via
I2C-bus.
The voltage of each output can be selected via I2C-bus.
These commands must be set prior to enabling
corresponding output. If you intend to change the
voltage setting for these outputs, be sure to do it after
the output is set disabled. In order to avoid unintended
output voltage change, each “output voltage setting” is
valid only when corresponding output is set
disabled(xxx_EN=0). The “output voltage setting” is
ignored when the output is set enabled(xxx_EN=1).
Output voltage setting can be referred by reading via
I2C-bus(VCTL register). It is strongly recommended
to read and check VCTL register value just before
setting enable the output in order to avoid unintended
output voltage change even in case if communication
error were to happen and incorrect voltage setting
were written to the device.
Each regulator output limits output current if the
output gets over-loaded condition. The limit current
decreases as the output voltage gets lower, in order to
reduce the stress applied to the device.
All regulators in LV56851UV are low dropout outputs,
because the output stage of all regulators is P-channel
LDMOS.
When you select output capacitors for linear
regulators, you should consider three main
characteristics: startup delay, transient response and
loop stability. The capacitor values and type should be
based on cost, availability, size and temperature
constraints. Tantalum, Aluminum electrolytic, Film,
or Ceramic capacitors are all acceptable solutions.
However, attention must be paid to ESR constraints.
The aluminum electrolytic capacitor is the least
expensive solution, but if the circuit operates at low
temperatures (-25 to -40°C ), both the value and ESR
of the capacitor will vary considerably. The capacitor
manufacturer's datasheet usually provides this
information.
[High-side switch]
AMP is a high-side power switch connected to VCC2.
The output is enabled or disabled via I2C-bus.
The high-side switch limits output current if the output
gets over-loaded condition. The limit current becomes
lower value, if the output voltage gets lower than 2.5
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19
LV56851UV
[Detections]
V(typ) in order to reduce the stress applied to the
device.
If the output is connected to inductive load or loads
which have different ground potential, protection
diodes (D1,D2) are necessary to protect the device
from negative voltage.
RESET circuit
When the VDD voltage drops below the reset
threshold (typ:2.8 V, 85% of Vo1:3.3 V) for more than
Detection delay period(Td1), RSTB is pulled low.
During RSTB=Low, internal control circuitry is reset
and all the registers of I2C-bus are initialized.
When the VDD voltage rises higher than the threshold
(typ:2.86 V, 86.6% of Vo1:3.3 V), RSTB becomes
open state and reaches high level by external resistor
Rrst, internal reset is released after the delay
period(Td2).
Add an optional capacitor between RSTB to GND in
order to obtain longer reset time (>Td2). The
approximate delay time can be calculated by the
expression below.
[Current Limiting]
When the each output becomes in over loaded
condition, the device limits the output current.
All outputs are also protected against short circuit to
GND by fold back current limiter.
If one of each output except VDD is in over-current
condition, OC bit of FLG register is set 1, which can
be read via I2C-bus.
VDD
To
MCU
Rrst
RESET delay time (typ)
= 0.68*Rrst*Crst + Td2 (sec)
I2C
RSTB
Reset
Vrst
VDD
Filter
CTRL
Crst
(Optional)
Vrst : RESET voltage(typ:2.8 V)
RESET circuit block diagram
Vrst+Vrsth
Vrst
VDD
(<Td1)
GND
VDD
(<Td2)
RSTB
Td2
Td2
Td1
Unstable Region
Td1
Unstable Region
RSTB Timing Chart
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20
GND
LV56851UV
Under voltage detection (UVDET)
If the VCC2 voltage gets lower than set value
(UVD_V[1:0]), Under-Voltage is detected and the UV
bit of FLG register is set 1, which can be read via
I2C-bus. BDET pin keeps “Low” during UVDET
condition. Each output status keeps the same
condition even if UV is detected.
Over voltage detection (OVDET)
If the VCC2 voltage exceeds 18V(typ), Over-Voltage
is detected and the OV bit of FLG register is set 1,
which can be read via I2C-bus. BDET pin keeps
“Low” during OVDET condition. Each output status
keeps the same condition even if OV is detected.
ACC Under voltage detection
If the ACCIN voltage gets lower than set value
(ACC_V[1:0]), the ACCUV bit of FLG register is set
1, which can be read via I2C-bus. ACCDET pin keeps
“Low” during ACCUV is detected.
Each output status keeps the same condition even if
ACCUV is detected.
Over voltage protection (OVP)
If the voltage of VCC1 or VCC2 exceeds 21 V(typ),
OVP is detected and the OVP bit of FLG register is set
1, which can be read via I2C-bus. And all the outputs
except VDD are automatically turned off. When the
voltage of VCC1 and VCC2 get lower than 20.5
V(typ), OVP detection is released. But output voltages
are not automatically restored, because once OVP is
detected, PM register of I2C-bus is reset.
BDET pin keeps “Low” during OVP condition.
Thermal Shutdown
To protect the device from overheating, a thermal
shutdown circuitry is included. If the junction
temperature exceeds approximately 175°C(typ), all
outputs are turned off regardless of control state. After
the junction temperature drops below 145°C(typ),
VDD output is automatically restored and I2C-bus
control becomes available.
The thermal shutdown circuit does not guarantee the
protection of the final product because it operates out
of maximum rating (exceeding Tjmax=150°C).
Thermal Warning
To inform over-temperature of the die, when the
junction
temperature
exceeds
approximately
140°C(typ), the TWARN bit of FLG register is set 1,
which can be read via I2C-bus. After the junction
temperature drops below 130°C(typ), TWARN is
released and TWARN bit is reset.
Each output status keeps the same condition even if
TWARN is detected.
If you set BDETMD bit=1 of DET register, BDET pin
becomes “Low” when TWARN is detected.
BDET output
BDET output depends on BDETMD bit setting of
DET register as shown on the table below.
When each of the listed condition is satisfied, BDET is
pulled “Low”.
Conditions for BDET=Low
UV
OV
TWARN
BDETMD
Conditions
0 (default)
1
VCC2 < UVDET Threshold
VCC2 > OVDET Threshold
Tj > 140oC(typ)





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21
ignored
LV56851UV
21 V
18 V
VCC1
VDD output
20.5 V
17.5 V
6.5 V
7V
OVP release
VCC2
OVP detect
Timing Chart
2.86 V
3.8 V
2.8 V
2.8 V
VDD lost
VDD
SYS_EN=0
AMP_EN=0
Initial
Settings
Output enable
Settings
ILM_EN=0
CD_EN=0
AUDIO_EN=0
Output enable
Settings
AMP_EN=1
SYS_EN=1
CD_EN=1
AUDIO_EN=1
ILM_EN=1
2
I C inputs
(SCL/SDA)
Initial
Settings
RSTB
ILM output
CD output
AUDIO output
SYS output
AMP output
ACCIN
2.7 V
2.9 V
ACCDET
VDD
BDET
VDD
OVDET
Note: The above values are obtained when typ. All the voltage setting are default values
www.onsemi.com
22
UVDET
LV56851UV
APPLICATION CIRCUIT EXAMPLE
CD
ACCDET
BDET
14
13
SDA
C10
SCL
RSTB
SDA
VDD
SCL
VCC1
SYS
12
11
15
BDET
ACCDET
C8 C7
R3
R2
SYS
R1
AUDIO
10
9
C9
C6 C5
ILM
8
7
C4
C3
C2
6
5
D2
D1
VCC2
4
3
C1
ACCIN
AUDIO
CD
2
1
ILM
GND
AMP
LV56851UV
VDD
RSTB
D3
ACC
AMP
+B
Peripheral parts
Part name
Description
Recommended value
C1
Capacitor for AMP output stabilization
greater than 2.2 μF
C2,C3,C4,C9,C10
output stabilization capacitor
greater than10 μF(*)
C6,C8
Power supply bypass capacitor
C6: greater than 100 μF
C8: greater than 47 μF
C5,C7
Capacitor for oscillation protector
greater than 0.22 μF
D1,D2
Internal device protection diode
ON Semiconductor
Note
Make sure to
implement close to
VCC and GND.
SB1003M3
D3
Reverse current protection diode
ON Semiconductor
SB1003M3
R1,R2
ACC divider resistors
R3
Pull-up resistor
R1>R2
100 kΩ
(*) Make sure that output capacitors are greater than 10 μF and meets the condition of ESR=0.001 to 10 Ω , in which
voltage/temperature dependence and their tolerances are taken into consideration. Moreover, in case of electrolytic
capacitor, high-frequency characteristics should be sufficiently good.
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23
LV56851UV
HZIP15 Heat sink attachment
Heat sinks are used to lower the semiconductor device
junction temperature by leading the head generated by
the device to the outer environment and dissipating the
heat.
Heat sink
gap
a. Unless otherwise specified, for power ICs with tabs
and power ICs with attached heat sinks, solder must
not be applied to the heat sink or tabs.
via hole
b. Heat sink attachment
Binding-head
machine-screw
Countersunk head
ma chine screw
• Use flat-head screws to attach heat sinks.
• Use also washer to protect the package.
• Use tightening torques in the ranges 39-59 Ncm(4-6
kgcm) .
• If tapping screws are used, do not use screws with a
diameter larger than the holes in the semiconductor
device itself.
• Do not make gap, dust, or other contaminants to get
between the semiconductor device and the tab or
heat sink.
• Take care to the position of via hole.
• Do not allow dirt, dust, or other contaminants to get
between the semiconductor device and the tab or
heat sink.
• Verify that there are no press burrs or screw-hole
burrs on the heat sink.
• Warping in heat sinks and printed circuit boards
must be no more than 0.05 mm between screw holes,
for either concave or convex warping.
• Twisting must be limited to under 0.05 mm.
• Heat sink and semiconductor device should be
mounted in parallel.
Take care of electric or compressed air screw driver
• The speed of these torque wrenches must not exceed
700 rpm, and should typically be about 400 rpm.
c. Silicone grease
• Spread the silicone grease evenly when mounting
heat sinks.
• Sanyo recommends YG-6260 (Momentive
Performance Materials Japan LLC)
d. Mount
• First mount the heat sink on the semiconductor
device, and then mount that assembly on the printed
circuit board.
• In case of attaching a heat sink after mounting a
semiconductor device into the printed circuit board,
be sure not to apply mechanical stress to the
semiconductor device and the external pins when
tightening up a heat sink with the screw.
e. When mounting the semiconductor device to the heat
sink using jigs, etc.,
• Take care not to allow the device to ride onto the jig
or positioning dowel.
• Design the jig so that no unreasonable mechanical
stress is applied to the semiconductor device.
f. Heat sink screw holes
• Be sure that chamfering and shear drop of heat sinks
must not be larger than the diameter of screw head
used.
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24
LV56851UV
• When using nuts, do not make the heat sink hole
diameters larger than the diameter of the head of the
screws used. A hole diameter about 15 % larger than
the diameter of the screw is recommended.
• When tap screws are used, be sure that the diameter
of the holes in the heat sink are not too small. A
diameter about 15 % smaller than the diameter of the
screw is recommended.
g. There is a method to mount the semiconductor device
to the heat sink by using a spring band. But this
method is not recommended because of possible
displacement due to fluctuation of the spring force
with time or vibration.
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25
LV56851UV
Package Dimensions
unit : mm
HZIP15
CASE 945AB
ISSUE A
SOLDERING FOOTPRINT*
Through Hole Area
(Unit: mm)
Package name
HZIP15
2.54
1.2
2.54
(1.91)
2.54
2.54
NOTE: The measurements are not to guarantee but for reference only.
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26
LV56851UV
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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