NCP5304 D

NCP5304
High Voltage, High and Low
Side Driver
The NCP5304 is a High Voltage Power gate Driver providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration.
It uses the bootstrap technique to insure a proper drive of the
High−side power switch. The driver works with 2 independent inputs
with cross conduction protection.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: up to 600 V
dV/dt Immunity ±50 V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to VCC Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays between Both Channels
Outputs in Phase with the Inputs
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
Under VCC LockOut (UVLO) for Both Channels
Pin−to−Pin Compatible with Industry Standards
These are Pb−Free Devices
1
SOIC−8
D SUFFIX
CASE 751
8
P5304
ALYW
G
1
NCP5304
AWL
YYWWG
1
PDIP−8
P SUFFIX
CASE 626
NCP5304
A
L or WL
Y or YY
W or WW
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
• Half−bridge Power Converters
• Full−bridge Converters
PINOUT INFORMATION
IN_LO
IN_HI
VCC
GND
1
2
3
4
8
7
6
5
VBOOT
DRV_HI
BRIDGE
DRV_LO
8 Pin Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP5304PG
PDIP−8
(Pb−Free)
50 Units / Rail
NCP5304DR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 7
1
Publication Order Number:
NCP5304/D
NCP5304
Vbulk
+
C1
D4
GND
Q1
Vcc
T1
C3
U1
8
IN_LO VBOOT
2
7
IN_HI DRV_HI
3
6
Vcc
Bridge
4
5
GND DRV_LO
1
GND
NCP1395
L1
Out+
+
C4
C3
Lf
Out−
D2
C6
Q2
NCP5304
GND
D1
GND
GND
R1
D3
GND
U2
Figure 1. Typical Application Resonant Converter (LLC type)
Vbulk
+
C1
C5
D4
GND
Q1
Vcc
C3
T1
U1
1
8
IN_LO VBOOT
2
7
IN_HI DRV_HI
3
6
Vcc
Bridge
4
5
GND DRV_LO
GND
NCP1395
L1
Out+
+
C3
Out−
D2
C6
Q2
NCP5304
GND
D1
C4
GND
GND
R1
D3
GND
U2
Figure 2. Typical Application Half Bridge Converter
VCC
VCC
VBOOT
UV
DETECT
IN_HI
PULSE
TRIGGER
GND
IN_LO
LEVEL
SHIFTER
GND
CROSS
CONDUCTION
PREVENTION
S Q
R Q
UV
DETECT
DRV_HI
BRIDGE
VCC
DRV_LO
DELAY
GND
GND
GND
Figure 3. Detailed Block Diagram
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2
NCP5304
PIN DESCRIPTIONS
Pin No.
Pin Name
Pin Function
1
IN_LO
Logic Input for Low side driver output in phase
2
IN_HI
Logic Input for High side driver output in phase
3
VCC
Low side and main power supply
4
GND
Ground
5
DRV_LO
Low side gate drive output
6
BRIDGE
Bootstrap return or High side floating supply return
7
DRV_HI
High side gate drive output
8
VBOOT
Bootstrap power supply
MAXIMUM RATINGS
Rating
VCC
VCC_transient
Symbol
Main power supply voltage
Main transient power supply voltage:
IVCC_max = 5 mA during 10 ms
VBRIDGE
VHV: High Voltage BRIDGE pin
VBRIDGE
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
Value
Unit
−0.3 to 20
V
23
V
−1 to 600
V
−10
V
VBOOT−VBRIDGE
VHV: Floating supply voltage
−0.3 to 20
V
VDRV_HI
VHV: High side output voltage
VBRIDGE − 0.3 to
VBOOT + 0.3
V
VDRV_LO
Low side output voltage
−0.3 to VCC + 0.3
V
50
V/ns
−1.0 to VCC + 0.3
V
2
kV
200
V
dVBRIDGE/dt
VIN_XX
Allowable output slew rate
Inputs IN_HI, IN_LO
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
Latch up capability per Jedec JESD78
RqJA
TJ_max
°C/W
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
100
178
Maximum Operating Junction Temperature
+150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP5304
ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, −40°C < TJ < 125°C, Outputs loaded with 1 nF)
TJ −40°C to 125°C
Symbol
Min
Typ
Max
Units
Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1)
IDRVsource
−
250
−
mA
Output low short circuit pulsed current VDRV = VCC, PW v 10 ms (Note 1)
Rating
OUTPUT SECTION
IDRVsink
−
500
−
mA
Output resistor (Typical value @ 25°C) Source
ROH
−
30
60
W
Output resistor (Typical value @ 25°C) Sink
ROL
−
10
20
W
High level output voltage, VBIAS−VDRV_XX @ IDRV_XX = 20 mA
VDRV_H
−
0.7
1.6
V
Low level output voltage VDRV_XX @ IDRV_XX = 20 mA
VDRV_L
−
0.2
0.6
V
Turn−on propagation delay (Vbridge = 0 V)
tON
−
100
170
ns
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
tOFF
−
100
170
ns
Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load
tr
−
85
160
ns
Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load
tf
−
35
75
ns
Propagation delay matching between the High side and the Low side
@ 25°C (Note 3)
Dt
−
20
35
ns
Internal fixed dead time (Note 4)
DT
65
100
190
ns
Minimum input width that changes the output
tPW1
−
−
50
ns
Maximum input width that does not change the output
tPW2
20
−
−
ns
Low level input voltage threshold
VIN
−
−
0.8
V
Input pull−down resistor (VIN < 0.5 V)
RIN
−
200
−
kW
High level input voltage threshold
VIN
2.3
−
−
V
Logic “1” input bias current @ VIN_XX = 5 V @ 25°C
IIN+
−
5
25
mA
Logic “0” input bias current @ VIN_XX = 0 V @ 25°C
IIN−
−
−
2.0
mA
DYNAMIC OUTPUT SECTION
INPUT SECTION
SUPPLY SECTION
VCC UV Start−up voltage threshold
VCC_stup
8.0
8.9
9.9
V
VCC_shtdwn
7.3
8.2
9.1
V
Hysteresis on VCC
VCC_hyst
0.3
0.7
−
V
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot_stup
8.0
8.9
9.9
V
Vboot UV Shut−down voltage threshold
Vboot_shtdwn
7.3
8.2
9.1
V
Hysteresis on Vboot
Vboot_shtdwn
0.3
0.7
−
V
IHV_LEAK
−
5
40
mA
Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
ICC1
−
4
5
mA
Consumption in inhibition mode (VCC = Vboot)
ICC2
−
250
400
mA
VCC current consumption in inhibition mode
ICC3
−
200
−
mA
Vboot current consumption in inhibition mode
ICC4
−
50
−
mA
VCC UV Shut−down voltage threshold
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 600 V)
1. Parameter guaranteed by design
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Timing diagram definition see Figure 7.
5. Timing diagram definition see Figure 5 and Figure 6.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCP5304
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 4. Input/Output Timing Diagram
50%
IN_HI
(IN_LO)
50%
tr
ton
90%
DRV_HI
(DRV_LO)
tf
toff
90%
10%
10%
Figure 5. Propagation Delay and Rise / Fall Time Definition
50%
IN_HI
50%
toff_HI
ton_HI
90%
DRV_HI
10%
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
IN_LO
50%
50%
toff_LO
ton_LO
90%
DRV_LO
10%
Figure 6. Matching Propagation Delay
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5
NCP5304
IN_HI
IN_LO
DRV_HI
DRV_LO
Internal Deadtime
Internal Deadtime
Figure 7. Input/Output Cross Conduction Output Protection Timing Diagram
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6
NCP5304
CHARACTERIZATION CURVES
140
TON, PROPAGATION DELAY (ns)
TON, PROPAGATION DELAY (ns)
140
120
TON High Side
100
80
60
40
TON Low Side
20
0
10
12
14
16
18
80
60
TON High Side
40
20
−20
0
40
60
80
100
TEMPERATURE (°C)
Figure 8. Turn ON Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
Figure 9. Turn ON Propagation Delay vs.
Temperature
120
120
120
TOFF Low Side
100
80
60
TOFF High Side
40
20
12
14
16
18
100
TOFF Low Side
80
60
TOFF High Side
40
20
0
−40
20
−20
0
VCC, VOLTAGE (V)
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 11. Turn OFF Propagation Delay vs.
Temperature
Figure 10. Turn OFF Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
140
160
TOFF PROPAGATION DELAY (ns)
TON, PROPAGATION DELAY (ns)
20
VCC, VOLTAGE (V)
TOFF, PROPAGATION DELAY (ns)
TOFF, PROPAGATION DELAY (ns)
100
0
−40
20
140
0
10
TON Low Side
120
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
0
10
20
30
40
50
0
10
20
30
40
BRIDGE PIN VOLTAGE (V)
BRIDGE PIN VOLTAGE (V)
Figure 12. High Side Turn ON Propagation
Delay vs. VBRIDGE Voltage
Figure 13. High Side Turn OFF Propagation
Delay vs. VBRIDGE Voltage
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7
50
NCP5304
160
140
120
tr High Side
120
TON, RISETIME (ns)
TON, RISETIME (ns)
140
100
80
60
40
100
80
60
tr Low Side
20
14
16
18
0
−40
20
45
60
80
100
120
tf Low Side
40
60
tf Low Side
40
30
35
30
25
20
tf High Side
15
tf High Side
10
10
5
12
14
16
18
0
−40
20
−20
0
VCC, VOLTAGE (V)
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 16. Turn OFF Falltime vs. Supply
Voltage (VCC = VBOOT)
Figure 17. Turn OFF Falltime vs. Temperature
35
200
180
30
160
25
DEAD TIME (ns)
PROPAGATION DELAY MATCHING (ns)
40
Figure 15. Turn ON Risetime vs. Temperature
70
0
10
20
Figure 14. Turn ON Risetime vs. Supply
Voltage (VCC = VBOOT)
50
20
0
TEMPERATURE (°C)
80
50
−20
VCC, VOLTAGE (V)
TOFF, FALLTIME (ns)
TOFF, FALLTIME (ns)
12
tr Low Side
40
20
0
10
tr High Side
20
15
10
140
120
100
80
60
40
5
0
−40
20
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Propagation Delay Matching Between High
Side and Low Side Driver vs. Temperature
Figure 19. Dead Time vs. Temperature
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8
120
1.4
1.4
1.2
1.2
LOW LEVEL INPUT VOLTAGE
THRESHOLD (V)
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
NCP5304
1
0.8
0.6
0.4
0.2
0
10
12
14
16
18
0.6
0.4
0.2
−20
0
20
40
60
80
100
120
VCC, VOLTAGE (V)
TEMPERATURE (°C)
Figure 20. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
Figure 21. Low Level Input Voltage Threshold
vs. Temperature
2.5
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
0.8
0.0
−40
20
2.5
2
1.5
1
0.5
0
10
12
14
16
18
2.0
1.5
1.0
0.5
0.0
−40
20
−20
0
20
40
60
80
100
120
VCC, VOLTAGE (V)
TEMPERATURE (°C)
Figure 22. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
Figure 23. High Level Input Voltage Threshold
vs. Temperature
LOGIC “0” INPUT CURRENT (mA)
4
LOGIC “0” INPUT CURRENT (mA)
1.0
3.5
3
2.5
2
1.5
1
0.5
0
10
12
14
16
18
20
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−40
VCC, VOLTAGE (V)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 24. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT)
Figure 25. Logic “0” Input Current vs.
Temperature
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9
120
NCP5304
10
LOGIC “1” INPUT CURRENT (mA)
LOGIC “1” INPUT CURRENT (mA)
8
7
6
5
4
3
2
1
6
4
2
0
0
10
12
14
16
18
20
−40
−20
0
40
60
80
100 120
VCC, VOLTAGE (V)
TEMPERATURE (°C)
Figure 27. Logic “1” Input Current vs.
Temperature
LOW LEVEL OUTPUT VOLTAGE (V)
1.0
0.8
0.6
0.4
0.2
0
10
12
14
16
18
0.8
0.6
0.4
0.2
0.0
−40
20
−20
0
VCC, VOLTAGE (V)
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 28. Low Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
Figure 29. Low Level Output Voltage vs.
Temperature
1.6
1.6
HIGH LEVEL OUTPUT VOLTAGE (V)
HIGH LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
20
Figure 26. Logic “1” Input Current vs. Supply
Voltage (VCC = VBOOT)
1
LOW LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
8
1.2
0.8
0.4
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
10
12
14
16
18
20
VCC, VOLTAGE (V)
−40
20
40
60
TEMPERATURE (°C)
Figure 30. High Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
Figure 31. High Level Output Voltage vs.
Temperature
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10
−20
0
80
100
120
NCP5304
400
350
OUTPUT SOURCE CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
400
Isrc High Side
300
250
200
Isrc Low Side
150
100
50
0
10
12
14
16
18
Isrc High Side
300
250
200
150
Isrc Low Side
100
50
0
−40
20
−20
0
40
60
80
100 120
TEMPERATURE (°C)
Figure 32. Output Source Current vs. Supply
Voltage (VCC = VBOOT)
Figure 33. Output Source Current vs.
Temperature
OUTPUT SINK CURRENT (mA)
600
Isrc High Side
500
400
Isrc Low Side
300
200
100
0
10
Isrc High Side
500
400
300
Isrc Low Side
200
100
0
12
14
16
18
20
−40
−20
0
VCC, VOLTAGE (V)
20
40
60
80
100 120
TEMPERATURE (°C)
Figure 34. Output Sink Current vs. Supply
Voltage (VCC = VBOOT)
Figure 35. Output Sink Current vs.
Temperature
0.2
20
LEAKAGE CURRENT ON HIGH
VOLTAGE PINS (600 V) to GND (mA)
HIGH SIDE LEAKAGE CURRENT ON
HV PINS TO GND (mA)
20
VCC, VOLTAGE (V)
600
OUTPUT SINK CURRENT (mA)
350
0.16
0.12
0.08
0.04
0
0
100
200
300
400
500
600
15
10
5
0
−40
−20
0
20
40
60
80
100
HV PINS VOLTAGE (V)
TEMPERATURE (°C)
Figure 36. Leakage Current on High Voltage
Pins (600 V) to Ground vs. VBRIDGE Voltage
(VBRIGDE = VBOOT = VDRV_HI)
Figure 37. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
(VBRIDGE = VBOOT = VDRV_HI = 600 V)
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120
NCP5304
100
VBOOT CURRENT SUPPLY (mA)
VBOOT SUPPLY CURRENT (mA)
100
80
60
40
20
0
0
4
8
12
16
80
60
40
20
0
−40
20
−20
0
60
80
100
120
Figure 39. VBOOT Supply Current vs.
Temperature
240
400
200
VCC CURRENT SUPPLY (mA)
VCC SUPPLY CURRENT (mA)
40
TEMPERATURE (°C)
VBOOT, VOLTAGE (V)
Figure 38. VBOOT Supply Current vs. Bootstrap
Supply Voltage
160
120
80
40
0
0
4
8
12
16
300
200
100
0
−40
20
−20
0
VCC, VOLTAGE (V)
9.8
8.8
UVLO SHUTDOWN VOLTAGE (V)
9.0
VCC UVLO Startup
9.4
9.2
9.0
8.8
8.6
VBOOT UVLO Startup
8.4
8.2
8.0
−40
−20
0
20
40
60
40
60
80
100
120
Figure 41. VCC Supply Current vs. Temperature
10.0
9.6
20
TEMPERATURE (°C)
Figure 40. VCC Supply Current vs. VCC Supply
Voltage
UVLO STARTUP VOLTAGE (V)
20
80
100
120
VCC UVLO Shutdown
8.6
8.4
8.2
8.0
VBOOT UVLO Shutdown
7.8
7.6
7.4
7.2
7.0
−40
TEMPERATURE (°C)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 42. UVLO Startup Voltage vs.
Temperature
Figure 43. UVLO Shutdown Voltage vs.
Temperature
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12
120
NCP5304
40
ICC+ IBOOT CURRENT SUPPLY (mA)
ICC+ IBOOT CURRENT SUPPLY (mA)
25
CLOAD = 1 nF/Q = 15 nC
20
15
10
5
RGATE = 0 R to 22 R
0
CLOAD = 2.2 nF/Q = 33 nC
35
30
25
20
15
10
RGATE = 0 R to 22 R
5
0
0
100
200
300
400
500
600
0
100
SWITCHING FREQUENCY (kHz)
Figure 44. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
VCC = 15 V
300
400
500
600
Figure 45. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
VCC = 15 V
120
ICC+ IBOOT CURRENT SUPPLY (mA)
70
CLOAD = 3.3 nF/Q = 50 nC
60
50
40
30
20
RGATE = 0 R to 22 R
10
0
CLOAD = 6.6 nF/Q = 100 nC
100
RGATE = 0 R
80
RGATE = 10 R
60
40
RGATE = 22 R
20
0
0
100
200
300
400
500
600
0
100
SWITCHING FREQUENCY (kHz)
200
300
−5
−40°C
−10
25°C
−15
125°C
−20
−25
−30
100
500
600
Figure 47. ICC1 Consumption vs. Switching
Frequency with 100 nC Load on Each Driver @
VCC = 15 V
0
−35
0
400
SWITCHING FREQUENCY (kHz)
Figure 46. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
VCC = 15 V
NEGATIVE PULSE VOLTAGE (V)
ICC+ IBOOT CURRENT SUPPLY (mA)
200
SWITCHING FREQUENCY (kHz)
200
300
400
500
600
NEGATIVE PULSE DURATION (ns)
Figure 48. NCP5304, Negative Voltage Safe Operating Area on the Bridge Pin
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13
NCP5304
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
Summary:
• If the negative pulse characteristic (negative voltage
level & pulse width) is above the curves the driver
runs in safe operating area.
• If the negative pulse characteristic (negative voltage
level and pulse width) is below one or all curves the
driver will NOT run in safe operating area.
Note, each curve of the Figure 48 represents the negative
voltage and width level where the driver starts to fail at the
corresponding die temperature.
If in the application the bridge pin is too close of the safe
operating limit, it is possible to limit the negative voltage
to the bridge pin by inserting one resistor and one diode as
follows:
When the driver is used in a half bridge configuration, it
is possible to see negative voltage appearing on the bridge
pin (pin 6) during the power MOSFETs transitions. When
the high−side MOSFET is switched off, the body diode of
the low−side MOSFET starts to conduct. The negative
voltage applied to the bridge pin thus corresponds to the
forward voltage of the body diode. However, as pcb copper
tracks and wire bonding introduce stray elements
(inductance and capacitor), the maximum negative voltage
of the bridge pin will combine the forward voltage and the
oscillations created by the parasitic elements. As any
CMOS device, the deep negative voltage of a selected pin
can inject carriers into the substrate, leading to an erratic
behavior of the concerned component. ON Semiconductor
provides characterization data of its half−bridge driver to
show the maximum negative voltage the driver can safely
operate with. To prevent the negative injection, it is the
designer duty to verify that the amount of negative voltage
pertinent to his/her application does not exceed the
characterization curve we provide, including some safety
margin.
In order to estimate the maximum negative voltage
accepted by the driver, this parameter has been
characterized over full the temperature range of the
component. A test fixture has been developed in which we
purposely negatively bias the bridge pin during the
freewheel period of a buck converter. When the upper gate
voltage shows signs of an erratic behavior, we consider the
limit has been reached.
Figure 48, illustrates the negative voltage safe operating
area. Its interpretation is as follows: assume a negative
10 V pulse featuring a 100 ns width is applied on the bridge
pin, the driver will work correctly over the whole die
temperature range. Should the pulse swing to −20 V,
keeping the same width of 100 ns, the driver will not work
properly or will be damaged for temperatures below
125°C.
Vcc
D4
Vbulk
1
IN_LO
MUR160
U2
NCP5304
IN_LO
2
IN_Hi
3
0
4
8
C2
100n
M3
BOOT
IN_HI
DRV_HI
VCC
BRIDGE
GND
DRV_LO
7
6
R1
5
10R
M4
D1
MUR160
0
Figure 49. R1 and D1 Improves the Robustness of the
Driver
R1 and D1 should be placed as close as possible of the
driver. D1 should be connected directly between the bridge
pin (pin 6) and the ground pin (pin 4). By this way the
negative voltage applied to the bridge pin will be limited
by D1 and R1 and will prevent any wrong behavior.
www.onsemi.com
14
NCP5304
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE N
D
A
E
H
8
5
1
4
E1
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
TOP VIEW
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
M
D1
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTE 6
www.onsemi.com
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT
TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NCP5304
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in
SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products
are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products
for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against
all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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www.onsemi.com
16
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NCP5304/D