MC10E136 D

MC10E136, MC100E136
5VECL 6-Bit Universal
Up/Down Counter
Description
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. The device generates a look-ahead-carry
output and accepts a look-ahead-carry input. These two features allow
for the cascading of multiple E136’s for wider bit width counters that
operate at very nearly the same frequency as the stand alone counter.
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count.
For more information on utilizing the look-ahead-carry features of the
device please refer to the applications section of this data sheet. The
differential COUT output facilitates the E136’s use in programmable
divider and self-stopping counter applications.
Unlike the H136 and other similar universal counter designs, the E136
carry−out and look-ahead-carry−out signals are registered on chip.
This design alleviates the glitch problem seen on many counters
where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the
E136 and H136 counters. The user, regardless of familiarity with the
H136, should read this data sheet carefully. Note specifically (see
logic diagram) the operation of the carry out outputs and the
look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input
pull−down resistor. The master reset is an asynchronous signal which
when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function
properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left
open. This practice will minimize switching noise which can reduce
the maximum count frequency of the device or significantly reduce
margins against other noise in the system.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE136G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Features
•
•
•
•
•
•
•
•
• Meets or Exceeds JEDEC Standard EIA/JESD78
550 MHz Count Frequency
Fully Synchronous Up and Down Counting
Look-Ahead-Carry Input and Output
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model: > 2 kV,
Machine Model: > 200 V
•
•
•
•
IC Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 506 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 9
1
Publication Order Number:
MC10E136/D
19
18
S2
27
17
S1
28
16
VCC
VEE
1
15
VCCO
CLK
2
14
COUT
CIN
3
13
COUT
CLIN
4
12
CLOUT
Pinout: 28-lead PLCC
(Top View)
5
6
7
8
9
10
Q3
Q2
Q5
20
11
Q2 − Q4 D5
D1
MR
D0 VCCO Q0
Q1 VCCO
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
D2 − D4
Bits 2 − 4
Figure 1. 28−Lead Pinout
Table 1. PIN DESCRIPTION
FUNCTION
Q1
PIN
Q0 D1
D Q
RQ
ECL Preset Data Inputs
ECL Data Outputs
Mode Control Pins
Master Reset
ECL Clock Input
ECL Differential Carry-Out Output (Active
LOW)
ECL Look-Ahead-Carry Out (Active LOW)
ECL Carry-In Input (Active LOW)
ECL Look-Ahead-Carry In Input (Active LOW)
Positive Supply
Negative Supply
D Q
RQ
D0 − D5
Q0 − Q5
S1, S2
MR
CLK
COUT,
COUT
CLOUT
CIN
CLIN
VCC, VCCO
VEE
Table 2. FUNCTION TABLE
FUNCTION
L
L
L
H
H
H
X
L
H
H
L
L
H
X
X
L
H
L
H
X
X
L
L
L
L
L
L
H
Z
Z
Z
Z
Z
Z
X
Preset Parallel Data
Increment (Count Up)
Hold Count
Decrement (Count Down)
Hold Count
Hold Count
Reset (Qn = LOW)
MR
CLK
CLK
S
MR
CLIN
CIN
CIN
S2
S1
S2
S1
D Q
D0
(Expanded Truth Table on page 3)
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions
are achieved internally without incurring a full gate delay
21
26
QM0
22
D2
S
23
VCCO
QM1
24
Q4
D Q
25
Q5
D Q
RQ
VCCO
COUT
COUT
D5
D Q
SQ
D4
QM0
D3
CLOUT
MC10E136, MC100E136
Figure 2. E136 Universal Up/Down Counter Logic
Diagram
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2
MC10E136, MC100E136
Table 3. EXPANDED TRUTH TABLE
Function
S1
S2
MR
CIN
CLIN
CLK
D5
D4
D3
D2
D1
D0
Q5
Q4
Q3
Q2
Q1
Q0
COUT
CLOUT
Preset
L
L
L
X
X
Z
L
L
L
L
H
H
L
L
L
L
H
H
H
H
Down
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
L
H
H
Preset
L
L
L
X
X
Z
H
H
H
H
L
L
H
H
H
H
L
L
H
H
Up
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
H
L
H
H
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
Hold
Hold
Preset
Up
Hold
Up
Hold
Hold
Z = Low to High Transition
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3
MC10E136, MC100E136
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
Tsol
Wave Solder
265
265
°C
VI v VCC
VI w VEE
Pb
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
125
150
Min
85°C
Typ
Max
125
150
Min
Typ
Max
Unit
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E136, MC100E136
Table 6. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
125
150
Min
85°C
Typ
Max
125
150
Min
Typ
Max
Unit
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 4)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.3
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 7. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
125
150
Min
85°C
Typ
Max
125
150
Min
Typ
Max
Unit
140
170
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 6)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 8. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
125
150
Min
85°C
Typ
Max
125
150
Min
Typ
Max
Unit
140
170
mA
IEEf
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 8)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E136, MC100E136
Table 9. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
0°C
25°C
85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fCOUNT
Maximum Count Frequency
550
650
−
550
650
−
550
650
−
MHz
tPLH
tPHL
Propagation Delay to Output
CLK to Q
MR to Q
CLK to COUT
CLK to CLOUT
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
ts
Setup Time
S1, S2
D
CLIN
CIN
1000
800
150
800
650
400
0
400
−
−
−
−
1000
800
150
800
650
400
0
400
−
−
−
−
1000
800
150
800
650
400
0
400
−
−
−
−
th
Hold Time
S1, S2
D
CLIN
CIN
150
150
300
150
−200
−250
0
−250
−
−
−
−
150
150
300
150
−200
−250
0
−250
−
−
−
−
150
150
300
150
−200
−250
0
−250
−
−
−
−
tRR
Reset Recovery Time
1000
700
−
1000
700
−
1000
700
−
tJITTER
Random Clock Jitter
tPW
Minimum Pulse Width
tr
tf
Rise/Fall Times 20% - 80%
Symbol
<1
CLK, MR
<1
<1
ps
ps
ps
ps
ps
700
400
−
700
400
−
700
400
−
250
425
600
250
425
600
250
425
600
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
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MC10E136, MC100E136
APPLICATIONS INFORMATION
Overview
result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately
these types of counters require external gating for cascading
designs of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there
is a performance impact with this type of architecture it is
minor compared to the impact of the ripple propagate
designs. As a result the E016 type counters have been used
extensively in applications requiring very high speed, wide
bit width synchronous counters.
ON Semiconductor has incorporated several improvements
to past universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader in
its class. With the addition of look-ahead-carry features on the
terminal count signal, very large counter chains can be
designed which function at very nearly the same clock
frequency as a single free running device. More importantly
these counter chains require no external gating. Figure 1 below
illustrates the interconnect scheme for using the
look-ahead-carry features of the E136 counter.
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. Using the S1 and S2 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CLIN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.
Note from the schematic the use of the master information
from the least significant bits for control of the two carry out
functions. This architecture not only reduces the carry out
delay, but is essential to incorporate the registered carry out
functions. In addition to being faster, because these
functions are registered the resulting carry out signals are
stable and glitch free.
Cascading Multiple E136 Devices
Many applications require counters significantly larger
than the 6 bits available with the E136. For these
applications several E136 devices can be cascaded to
increase the bit width of the counter to meet the needs of the
application.
In the past cascading several 136 type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the
Q0 −> Q5
CLOCK
Q0 −> Q5
CLK
Q0 −> Q5
CLK
CLK
Q0 −> Q5
CLK
LSB
“LO”
CIN
“LO”
CLIN
COUT
CLOUT
MSB
“LO”
CLIN
D0 −> D5
111101
COUT
CIN
COUT
CIN
CLOUT
CLIN
D0 −> D5
CLOUT
D0 −> D5
111110
111111
CLK
CLOUT
COUT
Figure 3. 24-bit Cascaded E136 Counter
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7
000000
COUT
CIN
CLIN
CLOUT
D0 −> D5
000001
MC10E136, MC100E136
CIN
CLIN
presented by the CLOUT of the LSC. The CIN’s in the
higher order counter will ripple propagate through the chain
to update the count status for the next occurrence of terminal
count on the LSC. This ripple propagation will not affect the
count frequency as it has 26−1 or 63 clock pulses to ripple
through without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the setup time of the CLIN input. This limit
will consist of the CLK to CLOUT delay of the E136 plus
the CLIN setup time plus any path length differences
between the CLOUT output and the clock.
ACTIVE
LOW
D
Q
CLK
Figure 4. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry
output (CLOUT) pulses low one clock pulse before the
counter reaches terminal count. Also note that both CLOUT
and the carry out pin (COUT) of the device pulse low for
only one clock period. The input structure for
look-ahead-carry in (CLIN) and carry in (CIN) is pictured
in Figure 2.
The CLIN input is registered and then ORed with the CIN
input. From the truth table one can see that both the CIN and
the CLIN inputs must be in a LOW state for the E136 to be
enabled to count (either count up or count down). The CLIN
inputs are driven by the CLOUT output of the lowest order
E136 and therefore are only asserted for a single clock
period. Since the CLIN input is registered it must be asserted
one clock period prior to the CIN input.
If the counter previous to a given counter is at terminal
count its COUT output and thus the CIN input of the given
counter will be in the “LOW” state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CLOUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CLOUT signal will be clocked
into the CLIN input of the higher order counters on the
following positive clock transition. Since both CIN and
CLIN are in the LOW state the next clock pulse will cause
the least significant counter to roll over and all higher order
counters, if signaled by their CIN inputs, to count by one.
Programmable Divider
Using external feedback of the COUT pin, the E136 can
be configured as a programmable divider. Figure 3
illustrates the configuration for a 6-bit count down
programmable divider. If for some reason a count up divider
is preferred the COUT signal is simply fed back to S2 rather
than S1. Examination of the truth table for the E136 shows
that when both S1 and S2 are LOW the counter will parallel
load on the next positive transition of the clock. If the S2
input is low and the S1 input is high the counter will be in the
count down mode and will count towards an all zero state
upon successive clock pulses. Knowing this and the
operation of the COUT output it becomes a trivial matter to
build programmable dividers.
For a programmable divider one wants to load a
predesignated number into the counter and count to terminal
count. Upon terminal count the counter should
automatically reload the divide number. With the
architecture shown in Figure 3 when the counter reaches
terminal count the COUT output and thus the S1 input will
go LOW, this combined with the low on S2 will cause the
counter to load the inputs present on D0-D5. Upon loading
the divide value into the counter COUT will go HIGH as the
counter is no longer at terminal count thereby placing the
counter back into the count mode.
Q0 −> Q5
Table 10. Preset Inputs Versus Divide Ratio
S2
CLOCK
CLK
Divide
“LO”
S1
COUT
COUT
D0 −> D5
Figure 5. 6-bit Programmable Divider
Ratio
D5
D4
D3
D2
D1
D0
2
3
4
5
•
•
36
37
38
•
•
62
63
64
L
L
L
L
•
•
H
H
H
•
•
H
H
H
L
L
L
L
•
•
L
L
L
•
•
H
H
H
L
L
L
L
•
•
L
L
L
•
•
H
H
H
L
L
L
H
•
•
L
H
H
•
•
H
H
H
L
H
H
L
•
•
H
L
L
•
•
L
H
H
H
L
H
L
•
•
H
L
H
•
•
H
L
H
During the clock pulse in which the higher order counter
is counting by one the CLIN is clocking in the high signal
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8
Preset Data Inputs
MC10E136, MC100E136
LOAD
100100
100011
100010
000011
000010
000001
000000
LOAD
• ••
CLOCK
•••
S1
•••
COUT
DIVIDE BY 37
Figure 6. Programmable Divider Waveforms
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N−1 must
be loaded into the counter. A single E136 device is capable
of divide ratios of 2 to 64 inclusive, Table 1 outlines the load
values for the various divide ratios. Figure 4 presents the
waveforms resulting from a divide by 37 operation. Note
that the availability of the COUT complementary output
COUT allows the user to choose the polarity of the divide by
output.
For single device programmable counters the E016
counter is probably a better choice than the E136. The E016
has an internal feedback to control the reloading of the
counter, this not only simplifies board design but also will
result in a faster maximum count frequency.
Q0 −> Q5
CLK
CLOCK
For programmable dividers of larger than 8 bits the
superiority of the E016 diminishes, and in fact for very wide
dividers the E136 will provide the capability of a faster count
frequency. This potential is a result of the cascading features
mentioned previously in this document. Figure 5 shows the
architecture of a 24-bit programmable divider implemented
using E136 counters. Note the need for one external gate to
control the loading of the entire counter chain. An ideal
device for the external gating of this architecture would be
the 4-input OR function in the 8-lead SOIC ECLinPS Lite™
family. However the final decision as to what device to use
for the external gating requires a balancing of performance
needs, cost and available board space. Note that because of
the need for external gating the maximum count frequency
of a given sized programmable divider will be less than that
of a single cascaded counter.
Q0 −> Q5
CLK
S1
Q0 −> Q5
Q0 −> Q5
CLK
S1
S1
CLK
LSB
“LO”
CIN
“LO”
CLIN
COUT
CLOUT
D0 −> D5
S1
MSB
“LO”
CIN
CLIN
COUT
CIN
CLOUT
COUT
CLIN
D0 −> D5
CLOUT
D0 −> D5
OUT
Figure 7. 24-bit Programmable Divider Architecture
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9
CIN
COUT
CLIN
CLOUT
D0 −> D5
MC10E136, MC100E136
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E136FN
PLCC−28
37 Units / Rail
MC10E136FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E136FNR2
PLCC−28
500 / Tape & Reel
MC10E136FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E136FN
PLCC−28
37 Units / Rail
MC100E136FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E136FNR2
PLCC−28
500 / Tape & Reel
MC100E136FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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10
MC10E136, MC100E136
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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11
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E136, MC100E136
ECLinPS and ECLinPS Lite are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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12
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For additional information, please contact your local
Sales Representative
MC10E136/D