MC14018B D

MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Anti−lock gating is included in the
MC14018B to assure proper counting sequence.
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SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Features
• Fully Static Operation
• Schmitt Trigger on Clock Input
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
•
•
•
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4018B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
Din
1
16
VDD
JAM 1
2
15
R
JAM 2
3
14
C
Q2
4
13
Q5
Q1
5
12
JAM 5
Q3
6
11
Q4
JAM 3
7
10
PE
VSS
8
9
JAM 4
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
PD
Power Dissipation, per Package
(Note 1)
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
±10
mA
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
MARKING DIAGRAM
16
14018BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
FUNCTIONAL TRUTH TABLE
Clock
Reset
Preset
Enable
Jam
Input
Qn
X
X
X
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn
Dn *
1
0
1
*Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 8
1
Publication Order Number:
MC14018B/D
MC14018B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
Characteristic
Symbol
25_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
125_C
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
“1” Level
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
−1.3
−3.4
–4.2
–0.88
–2.25
−8.8
−
−
−
−
–1.7
−0.36
–0.9
−2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
VIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.3 mA/kHz) f + IDD
IT = (0.7 mA/kHz) f + IDD
IT = (1.0 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001.
ORDERING INFORMATION
Package
Shipping†
MC14018BDG
SOIC−16
(Pb−Free)
48 Units / Rail
NLV14018BDG*
SOIC−16
(Pb−Free)
48 Units / Rail
MC14018BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14018B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
All Types
Symbol
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
tTLH, tTHL
ns
tPLH,
tPHL
Propagation Delay Time
Clock to Q
tPLH, tPHL = (0.90 ns/pF) CL + 265 ns
tPLH, tPHL = (0.36 ns/pF) CL + 102 ns
tPLH, tPHL = (0.26 ns/pF) CL + 72 ns
Unit
ns
5.0
10
15
−
−
−
310
120
85
620
240
170
Reset to Q
tPLH = (0.90 ns/pF) CL + 325 ns
tPLH = (0.36 ns/pF) CL + 132 ns
tPLH = (0.26 ns/pF) CL + 81 ns
5.0
10
15
−
−
−
370
150
100
740
300
200
Preset Enable to Q
tPLH, tPHL = (0.90 ns/pF) CL + 325 ns
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns
tPLH, tPHL = (0.26 ns/pF) CL + 81 ns
5.0
10
15
−
−
−
370
150
100
740
300
200
5.0
10
15
200
100
80
0
0
0
−
−
−
5.0
10
15
200
100
80
0
0
0
−
−
−
ns
th
5.0
10
15
540
500
480
270
250
240
−
−
−
ns
Clock Pulse Width
tWH
5.0
10
15
400
200
160
200
100
80
−
−
−
ns
Reset or Preset Enable
Pulse Width
tWH
5.0
10
15
290
130
110
145
65
55
−
−
−
ns
tTLH, tTHL
5.0
10
15
ns
ns
tsu
Setup Time
Data (Pin 1) to Clock
ns
Jam Inputs to Preset Enable
Data (Jam Inputs)−to−Preset
Enable Hold Time
Clock Rise and Fall Time
Clock Pulse Frequency
fcl
ns
No Limit
5.0
10
15
−
−
−
2.5
6.5
8.0
1.25
3.25
4.0
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
VDD
90%
50%
10%
ANY INPUT
VSS
tPLH
tPHL
VOH
90%
ANY OUTPUT
50%
10%
VOL
tTLH
tTHL
Figure 1. Switching Time Waveforms
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3
MHz
MC14018B
1
CLOCK
0
1
0
1
0
1
0
1
0
RESET
PRESET ENABLE
JAM 1
JAM 2
TIMING DIAGRAM
(Q5 Connected to Data Input)
JAM 3
JAM 4
1
0
1
0
1
0
1
DON'T CARE
UNTIL PRESET ENABLE
GOES HIGH
JAM 5
Q1
0
1
Q2
0
1
0
1
0
1
Q3
Q4
Q5
0
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
Q1
No external
components needed.
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 • Q4
Q4 • Q3
Q3 • Q2
Q2 • Q1
Gate package needed
to provide AND
function. Counter
Skips all 1’s state
Comments
LOGIC DIAGRAM
CLOCK14
JAM 1
2
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK
SHAPER
DATA1
D
S
Q
D
C
S
Q
D
C
Q
D
C
Q
R P
R P
S
S
Q
D
C
R P
S
Q
C
R P
R P
RESET15
PRESET ENABLE10
VDD = PIN 16
VSS = PIN 8
5
4
Q1
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4
Q2
6
11
Q3
13
Q4
Q5
MC14018B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
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For additional information, please contact your local
Sales Representative
MC14018B/D