A8735 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status change: December 3, 2013 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A8735 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver Features and Benefits Description ▪ Ultra small 2 × 2 DFN/MLP-8 package ▪ Low quiescent current draw (0.5 μA max. in shutdown mode) ▪ Primary-side output voltage sensing; no resistor divider required ▪ Fixed 1 A peak current limit ▪ 1V logic (VHI(min)) compatibility ▪ Integrated IGBT driver with internal gate resistors ▪ Optimized for mobile phone, 1-cell Li+ battery applications ▪ Zero-voltage switching for lower loss ▪ >75% efficiency ▪ Charge complete indication ▪ Integrated 50 V DMOS switch with self-clamping protection The Allegro™ A8735 is a Xenon photoflash charger IC designed to meet the needs of ultra low power, small form factor cameras, particularly camera phones. By using primary-side voltage sensing, the need for a secondary-side resistive voltage divider is eliminated. This has the additional benefit of reducing leakage currents on the secondary side of the transformer. To extend battery life, the A8735 features very low supply current draw (0.5 μA max in shutdown mode). The IGBT driver also has internal gate resistors for minimum external component count. The charge and trigger voltage logic thresholds are set at 1 VHI(min) to support applications implementing low-voltage control logic. Package: 8-pin DFN/MLP (suffix EE) The A8735 is available in an 8-contact 2 mm × 2 mm DFN/MLP package with a 0.60 maximum overall package height, and an exposed pad for enhanced thermal performance. It is lead (Pb) free with 100% matte tin leadframe plating. 2 mm × 2 mm, 0.60 mm height Not to scale Typical Applications Battery Input 2.3 to 5.5 V + C1 Battery Input 1.5 to 5.5 V COUT 100F 315 V VBAT + C1 VOUT Detect VOUT Detect SW VIN_VDRV SW VIN_VDRV Control Block C2 COUT 100F 315 V VBAT Control Block C2 ISW sense ISW sense VPULLUP CHARGE 100 kΩ DONE VPULLUP CHARGE DONE DONE VIN_VDRV TRIG VIN_VDRV IGBT Driver IGBT Gate TRIG IGBT Driver IGBT Gate GATE GND (A) Figure 1. Typical applications: (A) with single battery supply and (B) with separate bias supply 8735-DS 100 kΩ DONE GATE GND (B) Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Selection Guide Part Number A8735EEETR-T Packing Package 3000 pieces per reel 8-contact DFN/MLP with exposed thermal pad Absolute Maximum Ratings Characteristic SW Pin VIN_DRV, VBAT Pins Symbol Notes VSW DC voltage. (VSW is self-clamped by internal active clamp and is allowed to exceed 50 V during flyback spike durations. Maximum repetitive energy during flyback spike: 0.5 μJ at frequency ≤ 400 kHz.) ISW DC current, pulse width = 1 ms Care should be taken to limit the current when –0.6 V is applied to these pins. Remaining Pins Operating Ambient Temperature Maximum Junction Storage Temperature Units –0.3 to 50 V 3 A –0.3 to 6.0 V –0.6 to VIN + 0.3 V V VIN ¯N̄¯Ē¯ Pins CHARGE, TRIG, D̄¯Ō Rating –0.3 to VIN + 0.3 V V –40 to 85 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC TA Range E THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* 4-layer PCB, based on JEDEC standard Value Units 49 ºC/W *Additional thermal information available on Allegro Web site. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Functional Block Diagram SW VBAT VSW – VBAT ILIM Reference DCM Detector toff(max) Control Logic DMOS 18 μs VDSref HmL Triggered Timer OCP S Q R Q ton(max) 18 μs Enable VIN_DRV S Q R Q DONE CHARGE VIN_DRV IGBT Driver GATE TRIG GND Terminal List Pin-out Diagram DONE 1 TRIG 2 GATE 3 PAD GND 4 (Top View) Number Name Function 1 ¯N̄¯Ē¯ D̄¯Ō Open collector output, pulls low when output reaches target value and CHARGE is high. Goes high during charging or whenever CHARGE is low. 2 TRIG IGBT trigger input. GATE IGBT gate drive output. GND Ground connection. 8 CHARGE 7 VIN_DRV 3 6 VBAT 4 5 SW 5 SW 6 VBAT 7 VIN_DRV Input voltage. Connect to 3 to 5.5 V bias supply. Decouple VIN voltage with 0.1 μF ceramic capacitor placed close to this pin. 8 CHARGE Charge enable pin. Set this pin low to shut down the chip. – PAD Drain connection of internal DMOS switch. Connect to transformer primary winding. Battery voltage. Exposed pad for enhanced thermal dissipation. Connect to ground plane. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 ELECTRICAL CHARACTERISTICS Typical values are valid at VIN = VBAT = 3.6 V; TA = 25°C, except guaranteed from −40°C to 85°C ambient, unless otherwise noted Characteristics VBAT Voltage Range1 VIN_DRV Voltage Range1 UVLO Enable Threshold UVLO Hysteresis Symbol Min. Typ. Max. Unit VBAT 1.5 – 5.5 V VIN 2.3 – 5.5 V – 2.05 2.2 V – 150 – mV Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.02 0.5 μA Charging complete – 50 100 μA VINUV Test Conditions VIN rising VINUV(hys) VIN Supply Current indicates specifications IIN VBAT Pin Supply Current IBAT Charging (CHARGE = VIN, TRIG = 0 V) – 2 – mA Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.01 1 μA Charging done (CHARGE = VIN, ¯N̄¯Ē¯ = 0 V) D̄¯Ō – – 5 μA Charging (CHARGE = VIN, TRIG = 0 V) – – 50 μA Current Limit Primary-Side Current Limit2 Switch On-Resistance Switch Leakage Current1 ISWLIM RSWDS(on) ISWLK CHARGE Input Current ICHARGE CHARGE Input Voltage1 VCHARGE CHARGE On/Off Delay Switch-Off Timeout tCH 0.9 1.0 1.1 A VIN_DRV = 3.6 V, ID = 600 mA, TA = 25°C – 0.4 – Ω VSW = 5.5, over full temperature range – – 2 μA VCHARGE = VIN – 36 – μA High, over input supply range 1.0 – – V Low, over input supply range – – 0.4 V Time between CHARGE = 1 and charging enabled – 20 – us – 18 – μs toff(max) Switch-On Timeout ton(max) Output Comparator Trip Voltage3 VOUTTRIP Measured as VSW – VBAT Pulse width = 200 ns (90% to 90%) – 18 – μs 31.0 31.5 32.0 V – 200 400 mV 1 μA Output Comparator Voltage Overdrive VOUTOV ¯N̄¯Ē¯ Output Leakage Current1 D̄¯Ō IDONELK ¯N̄¯Ē¯ Output Low D̄¯Ō VDONEL ¯N̄¯Ē¯ pin 32 μA into D̄¯Ō – – 100 mV dV/dt Measured at SW pin – 20 – V/μs VTRIG(H) Input = logic high, over input supply range 1 – – V VTRIG(L) Input = logic low, over input supply range – – 0.4 V Voltage1 dV/dt Threshold for ZVS Comparator IGBT Driver TRIG Input Voltage1 TRIG Pull-Down Resistor – 100 – kΩ GATE Resistance to VIN_DRV RSrcDS(on) RTRIGPD VGATE = 1.8 V – 21 – Ω GATE Resistance to GND RSnkDS(on) VGATE = 1.8 V – 27 – Ω ¯N̄¯Ē ¯ pin, Measurement taken at D̄¯Ō CL= 6500 pF – 25 – ns Propagation Delay (Rising)4,5 tDr Propagation Delay (Falling)4,5 tDf – 60 – ns tr – 290 – ns tf – 380 – ns RGTPD – 20 – kΩ Output Rise Time4,5 Output Fall Time4,5 GATE Pull-Down Resistor 1Specifications throughout the range TA = –40°C to 85°C guaranteed by design and characterization. limit guaranteed by design and correlation to static test. 3Specifications throughout the range T = –20°C to 85°C guaranteed by design and characterization. A 4Guaranteed by design and characterization. 5See IGBT Drive Timing Definition diagram for further information. 2Current Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 IGBT Drive Timing Definition 50% TRIG 50% tDr tr tDf 90% GATE tf 90% 10% 10% Operation Timing Diagram VBAT VIN UVLO CHARGE SW Target VOUT VOUT DONE T2 T1 T3 TRIG GATE A B C D E F Explanation of Events A: Start charging by pulling CHARGE to high, provided that VIN is above UVLO level. B: Charging stops when VOUT reaches the target voltage. C: Start a new charging process with a low-to-high transition at the CHARGE pin. D: Pull CHARGE to low to put the controller in low-power standby mode. E: Charging does not start, because VIN is below UVLO level when CHARGE goes high. F: After VIN goes above UVLO, another low-to-high transition at the CHARGE pin is required to start the charging. T1, T2, T3 (Trigger instances): IGBT driver output pulled high whenever the TRIG pin is at logic high. It is recommended to avoid applying any trigger pulses during charging. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Characteristic Performance IGBT Drive Performance IGBT drive waveforms are measured at pin, with capacitive load of 6800 pF tr Rising Signal VIN Symbol C1 C2 C3 t Conditions Parameter VTRIGGER VGATE VIN time Parameter tDr tr CLOAD Units/Division 1V 1V 1V 100 ns Value 23 ns 320 ns 6.8 nF C2,C3 VGATE C1 VTRIGGER t tf Falling Signal VIN Symbol C1 C2 C3 t Conditions Parameter VTRIGGER VGATE VIN time Parameter tDr tr CLOAD Units/Division 1V 1V 1V 100 ns Value 58 ns 402 ns 6.8 nF VGATE C2,C3 VTRIGGER C1 t Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Characteristic Performance Charge Time versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, COUT = 100 μF / 330 V UCC, at room temperature 20 18 16 Time (Sec) 14 12 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 Battery Voltage (V) 4.5 5.0 5.5 Efficiency versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature 86% 84% 82% 80% 78% Efficiency (%) 76% 74% 72% 70% 68% 66% 64% 62% 60% 58% 56% 54% 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Final Output Voltage versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature 328 327 326 VOUT (V) 325 324 323 322 321 320 1.5 2.0 2.5 3.0 3.5 4.0 Battery Voltage (V) 4.5 5.0 5.5 Note: Output voltage is sensed from the primary side winding when the switch turns off. This duration, toff , has to be long enough (>200 ns) in order to obtain an accurate measurement. The value of toff depends on ISWlim, primary inductance, LPrimary , and the turns ratio, N, as given by: toff = (ISWlim × LPRIMARY × N) / VOUT . Average Input Current versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature 0.50 0.45 Current (A) 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 Battery Voltage (V) 4.5 5.0 5.5 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Charging Waveforms Output Capacitor Charging at Various Battery Voltages Test conditions: VIN = 3.6 V, COUT = 100 μF / 330 V UCC, transformer = T-16-024A (LPRIMARY =12.8 μH, N = 10.25), at room temperature ¯N̄¯Ē¯ (5 V / div), Ch2 = Battery Voltage (1 V / div), Ch3 = Output Voltage (50 V / div), Ch4 = Input Current (100 mA V / div), Oscilloscope settings: Ch1 = D̄¯Ō Time scale = 1 sec / div VOUT VBAT = 3.0 V VBAT IIN C2,C3,C4 VDONE C1 VOUT VBAT VBAT = 3.7 V IIN C2,C3,C4 VDONE C1 VOUT VBAT VBAT = 4.2 V IIN C2,C3,C4 VDONE C1 VOUT VBAT VBAT = 5.0 V IIN C2,C3,C4 C1 VDONE t Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Functional Description General Operation Overview The charging operation is started by a low-to-high signal on the CHARGE pin, provided that VIN is above the VUVLO level. It is strongly recommended to keep the CHARGE pin at logic low during power-up. After VIN exceeds the UVLO level, a lowto-high transition on the CHARGE pin is required to start the ¯ open-drain indicator is pulled low when charging. The D̄¯¯ Ō¯¯N̄¯Ē CHARGE is high and target output voltage is reached. When a charging cycle is initiated, the transformer primary side current, IPRIMARY , ramps-up linearly at a rate determined by the combined effect of the battery voltage, VBAT , and the primary side inductance, LPRIMARY . When IPRIMARY reaches the current limit, ISWLIM , the internal MOSFET is turned off immediately, allowing the energy to be pushed into the photoflash capacitor, COUT , from the secondary winding. The secondary side current drops linearly as COUT charges. The switching cycle starts again, either after the transformer flux is reset, or after a predetermined time period, tOFF(max) (18 μs), whichever occurs first. Timer Mode and Fast Charging Mode The A8735 achieves fast charging times and high efficiency by operating in discontinuous conduction mode (DCM) through most of the charging process. The relationship of Timer mode and Fast Charging mode is shown in figure 2. The IC operates in Timer mode when beginning to charge a completely discharged photoflash capacitor, usually when the output voltage, VOUT , is less than approximately 30 V (depending on transformer used). Timer mode is a fixed period, 18 μs, off-time control. One advantage of having Timer mode is that it limits the initial battery current surge and thus acts as a “soft-start.” A timeexpanded view of a Timer mode interval is shown in figure 3. VOUT The A8735 senses output voltage indirectly on primary side. This eliminates the need for high voltage feedback resistors required for secondary sensing. Flyback converter stops switching when output voltage reaches: IIN VOUT = K × N – Vd , Where: K = 31.5 V typically, Figure 2. Timer mode and Fast Charging mode: t = 1 s/div; VOUT = 50 V/div; IIN = 100 mA/div., VIN = VBAT = 3.6 V; COUT = 100 μF / 330 V; and ILIM = 1.0 A. Vd is the forward drop of the output diode (approximately 2 V), and N is transformer turns ratio. Switch On-Time and Off-Time Control The A8735 implements an adaptive on-time/off-time control. Ontime duration, ton , is approximately equal to ISW C4 VSW ton = ISWlim × LPRIMARY / VBAT . Off-time duration, toff , depends on the operating conditions during switch off-time. The A8735 applies two charging modes: Fast Charging mode and Timer mode, according to the conditions described in the next section. VBAT C2,C3 VOUT C1 Figure 3. Expanded view of Timer mode: VOUT ≤ 10 V, VBAT = 5.5 V, Ch1: VOUT = 20 V / div., Ch2: VBAT = 5 V / div., Ch3: VSW = 5 V / div., Ch4: ISW = 500 mA / div., t = 5 μs / div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8735 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver As soon as a sufficient voltage has built up at the output capacitor, the IC enters Fast-Charging mode. In this mode, the next switching cycle starts after the secondary side current has stopped flowing, and the switch voltage has dropped to a minimum value. A proprietary circuit is used to allow minimum-voltage switching, even if the SW pin voltage does not drop to 0 V. This enables C4 ISW Fast-Charging mode to start earlier, thereby reducing the overall charging time. Minimum-voltage switching is shown in figure 4. During Fast-Charging mode, when VOUT is high enough (over 50 V), true zero-voltage switching (ZVS) is achieved. This further improves efficiency as well as reduces switching noise. A ZVS interval is shown in figure 5. ISW C4 VSW VSW VBAT VBAT C2,C3 C2,C3 VOUT VOUT C1 Figure 4. Minimum-voltage switching: VOUT ≥ 35 V, VBAT = 5.5 V, Ch1: VOUT = 20 V / div., Ch2: VBAT = 5 V / div., Ch3: VSW = 5 V / div., Ch4: ISW = 500 mA / div., t = 1 μs / div. C1 Figure 5. True zero-voltage switching (ZVS): VOUT = 75 V, VBAT = 5.5 V, Ch1: VOUT = 20 V / div., Ch2: VBAT = 5 V / div., Ch3: VSW = 5 V / div., Ch4: ISW = 500 mA / div., t = 0.5 μs / div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Applications Information Transformer Design 1. The transformer turns ratio, N, determines the output voltage: N = NS / NP VOUT = 31.5 × N – Vd , where 31.5 is the typical value of VOUTTRIP , and Vd is the forward drop of the output diode. 2. The primary inductance, LPRIMARY , determines the on-time of the switch: ton = (–LPRIMARY / R ) × ln (1 – ISWlim × R /VIN) , where R is the total resistance in the primary current path (including RSWDS(on) and the DC resistance of the transformer). If VIN is much larger than ISWlim × R, then ton can be approximated by: ton = ISWlim × LPRIMARY /VIN . 3. The secondary inductance, LSECONDARY, determines the offtime of the switch. Given: LSECONDARY / LPRIMARY = N × N , then toff = (ISWlim / N) × LSECONDARY /VOUT = (ISWlim × LPRIMARY × N) /VOUT . ton The minimum pulse width for toff determines what is the minimum LPRIMARY required for the transformer. For example, if ILIM = 1.0 A, N = 10, and VOUT = 315 V, then LPRIMARY must be at least 6.3 μH in order to keep toff at 200 ns or longer. These relationships are illustrated in figure 6. In general, choosing a transformer with a larger LPRIMARY results in higher efficiency (because a larger LPRIMARY corresponds to a lower switch frequency and hence lower switching loss). But transformers with a larger LPRIMARY also require more windings and larger magnetic cores. Therefore, a trade-off must be made between transformer size and efficiency. Leakage Inductance and Secondary Capacitance The transformer design should minimize the leakage inductance to ensure the turn-off voltage spike at the SW node does not exceed the absolute maximum specification on the SW pin (refer to the Absolute Maximum Ratings table). An achievable minimum leakage inductance for this application, however, is usually compromised by an increase in parasitic capacitance. Furthermore, the transformer secondary capacitance should be minimized. Any secondary capacitance is multiplied by N2 when reflected to the primary, leading to high initial current swings when the switch turns on, and to reduced efficiency. toff VSW ISW Vr tf VIN VIN VSW ISW tneg Figure 6. Transformer Selection Relationships Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Effects of Input Filters Input Capacitor Selection Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, CIN. During initial Timer mode the device operates with 18 μs off-time. The resonant period caused by input filter inductor and capacitor should be at least 2 times greater or smaller than the 18 μs Timer period, to reduce input ripple current during this period. The typical input LC filter is shown in figure 7. VBAT C2 C3 IBAT C1 The resonant period is given by: Tres = 2 VOUT (L × CIN)1/2 . The effects of input filter components are shown in figures 8, 9, and 10. It is recommended to use at least 10 μF / 6.3 V to decouple the battery input, VBAT , at the primary of the transformer. Decouple the VIN pin using 0.1 μF / 6.3 V bypass capacitor. Figure 8. Input current waveforms with Li+ battery connected by 5-in. wire and decoupled by 4.7 μF capacitor, COUT = 100 μF, VIN = VBAT = 3.6 V, Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div, Ch3: IBAT = 500 mA/div, t = 1 s/div VOUT VBAT Output Diode Selection Choose rectifying diodes, D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse voltage and forward current requirements. The peak reverse voltage of the diodes, VDPeak , occurs when the internal MOSFET switch is closed. It can be calculated as: VDPeak = VOUT + N × VBAT . The peak current of the rectifying diode, IDPeak, is calculated as: IDPeak = IPRIMARY_Peak / N . C2 C3 IBAT C1 Figure 9. Input current waveforms with Li+ battery connected through 4.7 μH inductor and 4.7 μF capacitor, COUT = 100 μF, VIN = VBAT = 3.6 V, Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div, Ch3: IBAT = 200 mA/div, t = 1 s/div VOUT LIN + VBAT C2 VBAT CIN A8735 C3 IBAT C1 Figure 7. Typical input section with input inductance (inductance, LIN, may be an input filter inductor or inductance due to long wires in test setup) Figure 10. Input current waveforms with Li+ battery connected through 4.7 μH inductor and 10 μF capacitor, COUT = 100 μF, VIN = VBAT = 3.6 V, Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div, Ch3: IBAT = 200 mA/div, t = 1 s/div Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Layout Guidelines Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick traces for connections to the transformer primary ¯ signal trace and other and SW pin. It is important that the D̄¯¯ Ō¯¯N̄¯Ē signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. In addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board. Avoid placing any ground plane area underneath the transformer secondary and diode, to minimize parasitic capacitance. For low threshold logic (<1.2 V) add 1 nF capacitors across the CHARGE and TRIGGER pins to GND to avoid malfunction due to noise. Connect the EE package PAD to the ground pad for better thermal performance. Use ground planes on the top and bottom layers below the IC and connect them through multiple thermal vias. Refer to the figures on page 18 for recommended layout. Recommended Components Component Rating C1, Input Capacitor 10 μF, ±10%, 6.3 V, X5R ceramic capacitor (0805) C2 0.1 μF, 6.3 V X5R ceramic capacitor COUT, Photoflash Capacitor D1, Output Diode T1, Transformer Part Number Source JMK212BJ106K Taiyo Yuden 100 μF / 330 V EPH-31ELL101B131S Chemi-Con 2 x 250 V, 225 mA, 5 pF BAV23S Philips Semiconductor, Fairchild Semiconductor LPRIMARY = 12.8 μH, N= 10.25, 6.5 × 8 × 4 mm T-16-024A Tokyo Coil Electric LPRIMARY = 7.8 μH, N= 9.9, 4.6 × 4.6 × 2.4 mm MTF-S2 Union Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Recommended layout: Vout 3 D1 VBAT 1 2 BAV23S X2 C2 C4 Schematic 10uF 0.1uF TCE_T-16-024A 1 DONE CHARGE Cout1 100uF 4 2 R10 2k TP_Gate 6 A8735 VBAT 5 SW 7 1 3 VIN_DRV GATE DONE TRIG 2 4 8 CHARGE C5 1nF 3 C6 1nF GND Rg 12 U1 TRIGGER Top side Bottom side Top components Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver A8735 Package EE 8-Contact DFN/MLP with Exposed Thermal Pad 0.30 0.50 8 2.00 ±0.15 8 0.83 2.00 ±0.15 0.90 2.13 A 1 9X 2 D SEATING PLANE 0.08 C +0.05 0.55 –0.04 0.25 ±0.05 0.50 BSC 1 C 1.60 PCB Layout Reference View All dimensions nominal, not for tooling use (reference JEDEC MO-229UCCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 2 0.325 ±0.050 0.90 B 8 1 C 1.60 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2010-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16