2N6344 D

2N6344
Preferred Device
Triacs
Silicon Bidirectional Thyristors
Designed primarily for full-wave ac control applications, such as
light dimmers, motor controls, heating controls and power supplies; or
wherever full−wave silicon gate controlled solid−state devices are
needed. Triac type thyristors switch from a blocking to a conducting
state for either polarity of applied main terminal voltage with positive
or negative gate triggering.
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TRIACS
8 AMPERES RMS
600 thru 800 VOLTS
Features
• Blocking Voltage to 800 V
• All Diffused and Glass Passivated Junctions for Greater Parameter
Uniformity and Stability
MT2
• Small, Rugged, Thermowatt Construction for Low Thermal
•
•
•
MT1
G
Resistance, High Heat Dissipation and Durability
Gate Triggering Guaranteed in all Four Quadrants
For 400 Hz Operation, Consult Factory
Pb−Free Package is Available*
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
†Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to +110°C, Sine Wave
50 to 60 Hz, Gate Open)
2N6344
2N6349
VDRM,
VRRM
†On−State RMS Current (TC = +80°C) Full
Cycle Sine Wave 50 to 60 Hz (TC = +90°C)
IT(RMS)
8.0
4.0
A
†Peak Non−Repetitive Surge Current (One
Full Cycle, Sine Wave 60 Hz, TC = +25°C)
Preceded and followed by rated current
ITSM
100
A
I2t
40
A2s
PGM
20
W
PG(AV)
0.5
W
†Peak Gate Current
(TC = +80°C, Pulse Width = 2.0 ms)
IGM
2.0
A
†Peak Gate Voltage
(TC = +80°C, Pulse Width = 2.0 ms)
VGM
10
V
Circuit Fusing Consideration (t = 8.3 ms)
†Peak Gate Power
(TC = +80°C, Pulse Width = 2 ms)
†Average Gate Power
(TC = +80°C, t = 8.3 ms)
600
800
2
3
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
TJ
−40 to +125
°C
Storage Temperature Range
Tstg
−40 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†Indicates JEDEC Registered Data.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
May, 2006 − Rev. 4
2N6344G
AYWW
TO−220AB
CASE 221A
STYLE 4
1
†Operating Junction Temperature Range
© Semiconductor Components Industries, LLC, 2006
4
V
1
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
Device
Package
Shipping
2N6344
TO−220AB
500 Units / Box
2N6344G
TO−220AB
(Pb−Free)
500 Units / Box
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
2N6344/D
2N6344
THERMAL CHARACTERISTICS
Characteristic
†Thermal Resistance, Junction−to−Case
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Sec
Symbol
Max
Unit
RqJC
2.2
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
−
−
−
−
10
2.0
mA
mA
−
1.3
1.55
V
−
−
−
−
−
−
12
12
20
35
−
−
50
75
50
75
100
125
−
−
−
−
−
−
0.9
0.9
1.1
1.4
−
−
2.0
2.5
2.0
2.5
2.5
3.0
OFF CHARACTERISTICS
†Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
IDRM,
IRRM
TJ = 25°C
TJ = 100°C
ON CHARACTERISTICS
†Peak On−State Voltage
(ITM = "11 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p2%)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 W)
Quadrant I: MT2(+), G(+)
Quadrant II: MT2(+), G(−)
Quadrant III: MT2(−), G(−)
Quadrant IV: MT2(−), G(+)
†MT2(+), G(+); MT2(−), G(−) TC = −40°C
†MT2(+), G(−); MT2(−), G(+) TC = −40°C
IGT
Both
2N6349 only
Both
2N6349 only
Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 W)
Quadrant I: MT2(+), G(+)
Quadrant II: MT2(+), G(−)
Quadrant III: MT2(−), G(−)
Quadrant IV: MT2(−), G(+)
†MT2(+), G(+); MT2(−), G(−) TC = −40°C
†MT2(+), G(−); MT2(−), G(+) TC = −40°C
mA
VGT
Both
2N6349 only
Both
2N6349 only
Gate Non−Trigger Voltage (Continuous dc)
(VD = Rated VDRM, RL = 10 k W, TJ = 100°C)
†MT2(+), G(+); MT2(−), G(−); MT2(+), G(−); MT2(−), G(−)
V
VGD
†Holding Current (VD = 12 Vdc, Gate Open)
(Initiating Current = "200 mA)
TC = 25°C
*TC = −40°C
†Turn-On Time
(VD = Rated VDRM, ITM = 11 A, IGT = 120 mA, Rise Time = 0.1 ms, Pulse Width = 2 ms)
V
0.2
−
−
IH
−
−
6.0
−
40
75
mA
tgt
−
1.5
2.0
ms
dv/dt(c)
−
5.0
−
V/ms
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Commutation Voltage
(VD = Rated VDRM, ITM = 11 A, Commutating di/dt = 4.0 A/ms, Gate Unenergized, TC = 80°C)
†Indicates JEDEC Registered Data.
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2
2N6344
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VDRM
Peak Repetitive Forward Off State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On State Voltage
IH
Holding Current
VTM
on state
IH
IRRM at VRRM
off state
IH
Quadrant 3
MainTerminal 2 −
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
2N6349
only
(+) MT2
Quadrant I
(+) IGT
GATE
(−) IGT
GATE
Both
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
Quadrant III
Both
Quadrant 1
MainTerminal 2 +
(−) MT2
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
2N6349
only
+ Voltage
IDRM at VDRM
2N6344
100
10
PAV , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE ( °C)
α = 30°
60°
96
90°
120°
92
180°
α
88
α
84
80
α = CONDUCTION ANGLE
dc
8.0
1.0
2.0
3.0
4.0
5.0
6.0
IT(RMS), RMS ON-STATE CURRENT, (AMP)
7.0
2.0
8.0
0
1.0
5.0
2.0
3.0
4.0
6.0
IT(RMS), RMS ON-STATE CURRENT (AMP)
7.0
8.0
Figure 2. On−State Power Dissipation
50
OFF-STATE VOLTAGE = 12 V
I GT , GATE TRIGGER CURRENT (mA)
Vgt , GATE TRIGGER VOLTAGE (VOLTS)
90°
4.0
1.8
1.6
1.4
QUADRANT 4
1.2
1.0
1
QUADRANTS 2
0.6
0.4
−60
120°
α = CONDUCTION ANGLE
60°
TJ [ 100°C
30°
Figure 1. RMS Current Derating
0.8
α = 180°
α
6.0
0
0
dc
α
3
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
OFF-STATE VOLTAGE = 12 V
30
20
10
QUADRANT
7.0
5.0
−60
120 140
Figure 3. Typical Gate Trigger Voltage
−40
1
2
3
4
−20
0
20
40
60
80 100
TJ, JUNCTION TEMPERATURE (°C)
120 140
Figure 4. Typical Gate Trigger Current
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4
2N6344
20
100
GATE OPEN
I H , HOLDING CURRENT (mA)
70
50
30
TJ = 100°C
25°C
10
7.0
5.0
MAIN TERMINAL #2
POSITIVE
10
3.0
7.0
2.0
−60
−40
60
0
20
40
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
140
Figure 6. Typical Holding Current
3.0
2.0
100
1.0
0.7
0.5
0.3
0.2
0.1
0.4
80
60
CYCLE
40
TJ = 100°C
f = 60 Hz
Surge is preceded and followed by rated current
20
0
0.8 1.2
1.6
2.0
2.4
2.8
3.2 3.6 4.0
vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
1.0
4.4
2.0
3.0
5.0
NUMBER OF CYCLES
7.0
10
Figure 7. Maximum Non−Repetitive
Surge Current
Figure 5. On−State Characteristics
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
−20
5.0
I TSM , PEAK SURGE CURRENT (AMP)
i TM , INSTANTANEOUS ON-STATE CURRENT (AMP)
20
MAIN TERMINAL #1
POSITIVE
1.0
0.5
0.2
ZqJC(t) = r(t) • RqJC
0.1
0.05
0.02
0.01
0.1
0.2
0.5
1.0
2.0
5.0
20
50
t,TIME (ms)
100
200
Figure 8. Typical Thermal Response
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5
500
1.0 k
2.0 k
5.0 k
10 k
2N6344
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−07
ISSUE AA
−T−
B
F
SEATING
PLANE
C
T
S
4
Q
A
1 2 3
U
H
K
Z
R
L
V
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.014
0.022
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 4:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.36
0.55
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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2N6344/D
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