BTA12 600BW3 D

BTA12-600BW3G,
BTA12-800BW3G
Triacs
Silicon Bidirectional Thyristors
Designed for high performance full−wave ac control applications
where high noise immunity and high commutating di/dt are required.
http://onsemi.com
Features
•
•
•
•
•
•
•
•
•
TRIACS
12 AMPERES RMS
600 thru 800 VOLTS
Blocking Voltage to 800 V
On-State Current Rating of 12 A RMS at 25°C
Uniform Gate Trigger Currents in Three Quadrants
High Immunity to dV/dt − 2000 V/ms minimum at 125°C
Minimizes Snubber Networks for Protection
Industry Standard TO-220AB Package
High Commutating dI/dt − 2.5 A/ms minimum at 125°C
Internally Isolated (2500 VRMS)
These Devices are Pb−Free and are RoHS Compliant*
MT2
MT1
G
MARKING
DIAGRAM
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 125°C, Sine Wave,
50 to 60 Hz, Gate Open)
BTA12−600BW3G
BTA12−800BW3G
VDRM,
VRRM
On-State RMS Current
(Full Cycle Sine Wave, 60 Hz, TC = 80°C)
IT(RMS)
12
A
ITSM
105
A
I2t
46
A2sec
VDSM/
VRSM
VDSM/VRSM
+100
V
Peak Gate Current (TJ = 125°C, t = 20ms)
IGM
4.0
A
Peak Gate Power
(Pulse Width ≤ 1.0 ms, TC = 80°C)
PGM
20
W
Average Gate Power (TJ = 125°C)
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
TC = 25°C)
Circuit Fusing Consideration (t = 8.3 ms)
Non−Repetitive Surge Peak Off−State
Voltage (TJ = 25°C, t = 10ms)
Value
Unit
V
1
600
800
PG(AV)
1.0
W
Operating Junction Temperature Range
TJ
−40 to +125
°C
Storage Temperature Range
Tstg
−40 to +150
°C
RMS Isolation Voltage
(t = 300 ms, R.H. ≤ 30%, TA = 25°C)
Viso
2500
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 1
1
2
BTA12−xBWG
AYWW
TO−220AB
CASE 221A
STYLE 12
3
x
A
Y
WW
G
= 6 or 8
= Assembly Location (Optional)*
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is optional. In
cases where the Assembly Location is stamped
on the package the assembly code may be blank.
PIN ASSIGNMENT
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
No Connection
ORDERING INFORMATION
Device
Package
Shipping
BTA12−600BW3G
TO−220AB
(Pb−Free)
50 Units / Rail
BTA12−800BW3G
TO−220AB
(Pb−Free)
50 Units / Rail
Publication Order Number:
BTA12−600BW3/D
BTA12−600BW3G, BTA12−800BW3G
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
Junction−to−Case (AC)
Junction−to−Ambient
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 seconds
Symbol
Value
Unit
RqJC
RqJA
2.5
60
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Symbol
Min
Typ
Max
−
−
−
−
0.005
2.0
−
−
1.55
2.5
2.5
2.5
−
−
−
50
50
50
−
−
50
−
−
−
−
−
−
70
80
70
0.5
0.5
0.5
−
−
−
1.7
1.1
1.1
0.2
0.2
0.2
−
−
−
−
−
−
(dI/dt)c
2.5
−
−
A/ms
Critical Rate of Rise of On−State Current
(TJ = 125°C, f = 120 Hz, IG = 2 x IGT, tr ≤ 100 ns)
dI/dt
−
−
50
A/ms
Critical Rate of Rise of Off-State Voltage
(VD = 0.66 x VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
dV/dt
2000
−
−
V/ms
Characteristic
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
TJ = 25°C
TJ = 125°C
IDRM,
IRRM
mA
ON CHARACTERISTICS
Peak On-State Voltage (Note 2)
(ITM = ± 17 A Peak)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 30 W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IGT
Holding Current
(VD = 12 V, Gate Open, Initiating Current = ±100 mA)
IH
Latching Current (VD = 12 V, IG = 60 mA)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IL
Gate Trigger Voltage (VD = 12 V, RL = 30 W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
VGT
Gate Non−Trigger Voltage (TJ = 125°C)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
VGD
V
mA
mA
mA
V
V
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current, See Figure 10.
(Gate Open, TJ = 125°C, No Snubber)
2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.
http://onsemi.com
2
BTA12−600BW3G, BTA12−800BW3G
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VTM
VDRM
Peak Repetitive Forward Off State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On State Voltage
IH
Holding Current
on state
IRRM at VRRM
IH
Quadrant 3
MainTerminal 2 −
IH
off state
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
Quadrant III
(−) MT2
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
http://onsemi.com
3
Quadrant 1
MainTerminal 2 +
+ Voltage
IDRM at VDRM
BTA12−600BW3G, BTA12−800BW3G
20
PAV, AVERAGE POWER (W)
120°, 90°, 60°, 30°
110
95
180°
80
DC
65
0
2
4
6
8
10
180°
16
120°
14
12
10
8
90°
60°
6
30°
4
2
0
12
0
2
4
6
8
10
IT(RMS), RMS ON-STATE CURRENT (A)
IT(RMS), ON-STATE CURRENT (A)
Figure 1. RMS Current Derating
Figure 2. On−State Power Dissipation
1000
100
Typical @
TJ = −40°C
Typical @ TJ = 125°C
Typical @ TJ = 25°C
12
1
0.1
0.01
0.1
1
10
100
t, TIME (ms)
1000
1·104
Figure 4. Thermal Response
10
Typical @ TJ = 125°C
55
Typical @ TJ = 25°C
45
IH, HOLD CURRENT (mA)
IT, INSTANTANEOUS ON−STATE CURRENT (A)
DC
18
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
TC, CASE TEMPERATURE (°C)
125
1
Typical @ TJ = −40°C
0.1
0.5
1
1.5
2
2.5
3
3.5
4
4.5
35
MT2 Positive
25
5
5
MT2 Negative
15
−40 −25 −10 5
VT, INSTANTANEOUS ON-STATE VOLTAGE (V)
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. On-State Characteristics
Figure 5. Hold Current Variation
http://onsemi.com
4
BTA12−600BW3G, BTA12−800BW3G
2.0
Q3
10
VD = 12 V
RL = 30 W
Q1
Q2
1
−40 −25 −10 5
20
35
50
65
80
95
1.6
Q1
1.4
1.2
1.0
Q3
0.8
0.6
Q2
0.4
−40 −25 −10
110 125
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Gate Trigger Voltage Variation
Figure 6. Gate Trigger Current Variation
dv/dt , CRITICAL RATE OF RISE OF OFF‐STATE VOLTAGE (V/μ s)
VD = 12 V
RL = 30 W
1.8
GATE TRIGGER VOLTAGE (V)
IGT, GATE TRIGGER CURRENT (mA)
100
120
5k
4k
3k
2k
1k
0
10
100
1000
VD = 12 V
RL = 30 W
100
LATCHING CURRENT (mA)
VD = 800 Vpk
TJ = 125°C
Q2
80
60
Q1
40
Q3
20
0
−40 −25 −10 5
20 35 50 65 80 95
TJ, JUNCTION TEMPERATURE (°C)
10000
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (W)
Figure 8. Critical Rate of Rise of Off-State Voltage
(Exponential Waveform)
Figure 10. Latching Current Variation
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON‐POLAR
CL
TRIGGER CONTROL
CHARGE
1N4007
+
200 V
MT2
1N914 51 W
MT1
G
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 9. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
http://onsemi.com
5
110 125
BTA12−600BW3G, BTA12−800BW3G
PACKAGE DIMENSIONS
TO−220
CASE 221A−07
ISSUE AA
−T−
B
F
4
Q
SEATING
PLANE
C
T
S
A
U
1 2 3
H
K
Z
R
L
V
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.014
0.022
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
STYLE 12:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.36
0.55
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
BTA12−600BW3/D