INTERSIL HCTS7266HMSR

HCTS7266MS
Radiation Hardened
Quad 2-Input Exclusive NOR Gate
August 1995
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14
TOP VIEW
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
12
• Dose Rate Survivability: >1 x 10
10
• Dose Rate Upset >10
RAD (Si)/s
RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = 2.0V Min
A1 1
14 VCC
B1 2
13 B4
Y1 3
12 A4
Y2 4
11 Y4
A2 5
10 Y3
B2 6
9 B3
GND 7
8 A3
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14
TOP VIEW
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS7266MS is a Radiation Hardened quad 2-Input
exclusive NOR Gate. A logic level high on either one of the inputs
(A or B) will force the output (y) low. A high on both inputs, or a low
on both inputs will force the output to a logic high.
The HCTS7266MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family with TTL
input compatibility.
The HCTS7266MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
Y2
4
11
Y4
A2
5
10
Y3
B2
6
9
B3
GND
7
8
A3
Functional Diagram
An
Ordering Information
Yn
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
HCTS7266DMSR
-55oC to +125oC
Intersil Class
S Equivalent
14 Lead
SBDIP
HCTS7266KMSR
-55oC to +125oC
Intersil Class
S Equivalent
14 Lead
Ceramic
Flatpack
PACKAGE
HCTS7266D/
Sample
+25oC
Sample
14 Lead
SBDIP
HCTS7266K/
Sample
+25oC
Sample
14 Lead
Ceramic
Flatpack
Die
HCTS7266HMSR
+25oC
Die
Bn
TRUTH TABLE
INPUTS
OUTPUTS
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
H
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number
File Number
518627
3384.1
Specifications HCTS7266MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
74oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 116oC/W
30oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .500ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Delta ICC
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2, 3
+125oC, -55oC
-
200
µA
1
+25oC
-
1.6
mA
2, 3
+125oC, -55oC
-
3.2
mA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.80V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
∆ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 5.5V,
VIN = VCC or GND
1 Input = 2.4V
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
(Note 2)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V (Note 2)
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V (Note 3)
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. Force/Measure functions may be interchanged.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
2
518627
Specifications HCTS7266MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Propagation Delay
Input to Output
TPHL
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
20
ns
10, 11
+125oC, -55oC
2
22
ns
9
+25oC
2
27
ns
10, 11
+125oC, -55oC
2
29
ns
VCC = 4.5V, VIH = 3.0V
VIL = 0V
TPLH
VCC = 4.5V, VIH = 3.0V
VIL = 0V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
CIN
Output Transition
Time
TTHL
TTLH
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
30
pF
1
+125oC
-
45
pF
1
+25oC
-
10
pF
1
+125oC
-
10
pF
1
+25oC
1
15
ns
1
+125oC, -55oC
1
22
ns
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, F = 1MHz
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, F = 1MHz
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Delta ICC
SYMBOL
ICC
∆ICC
(NOTES 1, 2)
CONDITIONS
200K RAD
LIMITS
TEMPERATURE
MIN
MAX
UNITS
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.2
mA
VCC = 5.5V,
VIN = VCC or GND
1 Input = 2.4V
+25oC
-
3.2
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25oC
4.0
-
mA
Output Current (Source)
IOH
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC-0.4V, VIL = 0V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V and 5.5V,
VIH = VCC/2,
VIL = 0.8V, IOL = 50µA
+25oC
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V and 5.5V,
VIH = VCC/2,
VIL = 0.8V, IOH = -50µA
+25oC
VCC
-0.1
-
V
Spec Number
3
518627
Specifications HCTS7266MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Input Leakage Current
IIN
Noise Immunity
Functional Test
FN
200K RAD
LIMITS
TEMPERATURE
MIN
MAX
UNITS
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V @ 200K RAD,
(Note 3)
+25oC
-
-
-
Propagation Delay
Input to Outputt
TPHL
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
22
ns
Propagation Delay
Input to Output
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25oC
2
29
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
3µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
NOTE:
1. Alternate Group A in accordance with method 5005 of MIL-STD-883 may be exercised.
Spec Number
4
518627
Specifications HCTS7266MS
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
Group E Subgroup 2
NOTE:
1. Except FN which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
1/2 VCC = 3V ± 0.5V
GROUND
VCC = 6V ± 0.5V
50kHz
25kHz
-
14
-
-
-
1, 2, 5, 6, 8, 9, 12,
13, 14
-
-
3, 4, 10, 11
14
1, 5, 8, 12
2, 6, 9, 13
STATIC BURN-IN I TEST CONDITIONS (Note 1)
3, 4, 10, 11
1, 2, 5, 6, 7, 8, 9, 12, 13
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
3, 4, 10, 11
7
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
7
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
5
518627
HCTS7266MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% External Visual, Method 2009
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
6
518627
HCTS7266MS
AC Timing Diagrams
AC Load Circuit
DUT
TEST
POINT
VIH
INPUT
VS
CL
VIL
RL
TPLH
TPHL
VOH
CL = 50pF
VS
OUTPUT
RL = 500Ω
VOL
VOH
TTLH
TTHL
80%
VOL
20%
80%
20%
OUTPUT
AC VOLTAGE LEVELS
PARAMETER
HCTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
7
518627
HCTS7266MS
Die Characteristics
DIE DIMENSIONS:
84 x 84 mils
2.20 x 2.24mm
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4mm
Metallization Mask Layout
HCTS7266MS
A1
(1)
VCC
(14)
B4
(13)
B1 (2)
(12) A4
(11) Y4
Y1 (3)
(10) Y3
Y2 (4)
A2 (5)
(9) B3
(6)
B2
(7)
GND
(8)
A3
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCTS7266 is TA14436A.
Spec Number
8
518627