EMI9406 PRAETORIAN) L-C LCD and Camera EMI Array with ESD Protection Functional Description The EMI9406 is an inductor−based (L−C) EMI filter array with ESD protection, which integrates six filters in a uDFN package with 0.40 mm pitch. Each EMI filter channel of the EMI9406 is implemented with the component value of 1.8 pF 35 nH– 4.7 pF−35 nH– 6 pF. The cut−off frequency at −3 dB attenuation is 300 MHz and can be used in applications where the data rates are as high as 160 Mbps, while providing greater than −35 dB attenuation over the 800 MHz to 2.7GHz frequency range. The parts include ESD diodes on every I/O pin and provide a high level of protection against electrostatic discharge (ESD). The ESD protection diodes connected to the external filter ports are designed and characterized to safely dissipate ESD strikes of ±14 kV, which is beyond the maximum requirement of the IEC61000−4−2 international standard. This device is particularly well suited for wireless handsets, mobile LCD modules and PDAs because of its small package format and easy−to−use pin assignments. In particular, the EMI9406 is ideal for EMI filtering and protecting data and control lines for the LCD display and camera interface in mobile handsets. The EMI9404 is housed in space saving, low profile, 0.40 mm pitch UDFN packages in a RoHS compliant, Pb−Free format. Features • Six Channels of EMI Filtering with Integrated ESD Protection • Pi−Style EMI Filters in a Capacitor−Inductor−Capacitor (C−L−C) • • • • • • Network ±14 kV ESD Protection (IEC 61000−4−2 Level 4, contact discharge) at External Pin Greater than −35 dB Attenuation (typical) at 1 GHz UDFN Pb−Free Package with 0.40 mm Lead Pitch: 6−ch. = 12−Lead UDFN UDFN Pb−Free Package with 0.40 mm Lead Pitch: 12−lead: 2.50 mm x 1.35 mm Increased Robustness Against Vertical Impacts During Manufacturing Process These Devices are Pb−Free and are RoHS Compliant Applications • LCD and Camera Data Lines in Mobile Handsets • I/O Port Protection for Mobile Handsets, Notebook • December, 2011 − Rev. 0 MARKING DIAGRAMS L6 MG G UDFN12 CASE 517BD 12 1 1 = Specific Device Code = Month Code = Pb−Free Package L6 M G (*Note: Microdot may be in either location) PINOUTS Internal Pins (Lower ESD Event) 1 2 3 4 5 6 9 8 7 GND 12 11 10 External Pins (Higher ESD Event) (Bottom View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. • Wireless Handsets • Handheld PCs/PDAs • LCD and Camera Modules Computers, PDAs, etc. EMI Filtering for Data Ports in Cell Phones, PDAs or Notebook Computer © Semiconductor Components Industries, LLC, 2011 http://onsemi.com 1 Publication Order Number: EMI9406/D EMI9406 Figure 1. Electrical Schematic Table 1. PIN DESCRIPTIONS Pin # Name Description 1 FILTER1 Filter + ESD Channel 1 (Internal) 2 FILTER2 Filter + ESD Channel 2 (Internal) 3 FILTER3 Filter + ESD Channel 3 (Internal) 4 FILTER4 Filter + ESD Channel 4 (Internal) 5 FILTER5 Filter + ESD Channel 5 (Internal) 6 FILTER6 Filter + ESD Channel 6 (Internal) 7 FILTER6 Filter + ESD Channel 6 (External) 8 FILTER5 Filter + ESD Channel 5 (External) 9 FILTER4 Filter + ESD Channel 4 (External) 10 FILTER3 Filter + ESD Channel 3 (External) 11 FILTER2 Filter + ESD Channel 2 (External) 12 FILTER1 Filter + ESD Channel 1 (External) GND PAD GND Device Ground SPECIFICATIONS MAXIMUM RATINGS Parameter Value Unit –65 to +150 °C Current per Inductor 15 mA DC Package Power Rating 500 mW Storage Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range http://onsemi.com 2 Rating Unit –40 to +85 °C EMI9406 ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol 1. 2. 3. 4. Parameter LTOT Total Channel Inductance Conditions Min Typ Max 70 RTOT Total Channel DC Resistance CTOT_0V Total Channel Capacitance, 0 V bias CTOT_2.5V Total Channel Capacitance, 2.5 V bias nH 45 0 V dc; 1 MHz, 30 mVrms 17.5 2.5 V dc; 1 MHz, 30 mVrms Stand−off Voltage ILEAK Diode Leakage Current VSIG Signal Clamp Voltage Positive Clamp Negative Clamp ILOAD = 10 mA ILOAD = −10 mA 5.6 −1.5 VESD In−system ESD Withstand Voltage a) Contact discharge per IEC 61000−4−2 standard, Level 4 (External Pins) b) Contact discharge per IEC 61000−4−2 standard, Level 4 (Internal Pins) c) Air discharge per IEC61000−4−2 standard, Level 4 (External Pins) Notes 2 and 3 ±14 I = 10 mA Clamping Voltage TLP (Note 4) See Figures 4 through 7 fC Cut−off frequency ZSOURCE = 50 W, ZLOAD = 50 W pF pF 5.5 VIN = +3.3 V VC W 24 11.5 VST Unit V 0.1 0.5 mA 6.8 −0.8 9.0 −0.4 V kV ±2 ±16 IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 13.7 20 −4.4 −7.6 V 345 MHz TA = 25°C unless otherwise specified. ESD applied to input and output pins with respect to GND, one at a time. Unused pins are left open. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. PERFORMANCE INFORMATION TYPICAL FILTER PERFORMANCE TYPICAL DIODE CAPACITANCE VS. INPUT VOLTAGE (TA = 25°C, DC Bias = 0 V, 50 W Environment) Figure 3. Filter Capacitance vs. Input Voltage (Normalized to Capacitance at 0 VDC and 25°C) Figure 2. Typical Filter Insertion Loss ORDERING INFORMATION Device EMI9406MUTAG Pins Marking Package Shipping† 12 96 UDFN12 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 CURRENT (A) CURRENT (A) EMI9406 VOLTAGE (V) VOLTAGE (V) Figure 4. Positive TLP I−V Curve Figure 5. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement detail on TLP datasheet parameters, while application note AND9006/D provides a more complete explanation of the use of TLP for understanding protection product characteristics. Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 6. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 7 where an 8 kV IEC 61000−4−2 current waveform into a short is compared with TLP current pulses at 8 A and 16 A, also into a short. A TLP I−V curve shows the voltage at which the device turns on, as well as how well the device clamps voltage over a range of current levels. Typical TLP I−V curves for the EMI9404 are shown in Figures 4 and 5 for positive and negative stress respectively. Application note AND9007/D gives more L 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 6. Simplified Schematic of a Typical TLP System Figure 7. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 4 EMI9406 PACKAGE DIMENSIONS UDFN12, 2.5x1.35, 0.4P CASE 517BD ISSUE O A B D 2X 0.10 C PIN ONE REFERENCE 2X ÉÉÉ ÉÉÉ 0.10 C L L1 DETAIL A E OPTIONAL CONSTRUCTIONS TOP VIEW EXPOSED Cu A DETAIL B (A3) 0.05 C 12X A1 0.05 C NOTE 4 12X A1 SIDE VIEW 6 1 K 12 C SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MOLD CMPD ÇÇ ÉÉ A3 DETAIL B OPTIONAL CONSTRUCTION DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 2.50 BSC 1.90 2.10 1.35 BSC 0.30 0.50 0.40 BSC 0.15 −−− 0.20 0.30 −−− 0.05 DETAIL A D2 L L 7 e RECOMMENDED SOLDERING FOOTPRINT* E2 PACKAGE OUTLINE 12X 2.20 12X 0.40 b 0.10 C A B BOTTOM VIEW 0.05 C 1.55 NOTE 3 0.50 12X 0.40 PITCH 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PRAETORIAN is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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