MC74HC125A D

MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
PIN ASSIGNMENT
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7 A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
HC125A
Active−Low Output Enables
A1
OE1
A2
OE2
A3
OE3
A4
OE4
2
3
Y1
1
5
OE1
6
Y2
4
9
OE2
8
Y3
10
12
A2
A3
OE3
11
Y4
13
A4
OE4
OE1
1
14
VCC
A1
2
13
OE4
Y1
3
12
A4
OE2
4
11
Y4
A2
5
10
OE3
Y2
6
9
A3
GND
7
8
Y3
MARKING DIAGRAMS
14
14
HC
12xA
ALYWG
G
HC12xAG
AWLYWW
1
1
HC126A
Active−High Output Enables
A1
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
2
3
SOIC−14 NB
x
A
L, WL
Y, YY
W, WW
G or G
Y1
1
5
6
Y2
= 5, 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
4
9
TSSOP−14
FUNCTION TABLE
8
HC125A
Y3
Inputs
Output
HC126A
Inputs
Output
10
A
OE
Y
A
OE
Y
12
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
11
Y4
13
ORDERING INFORMATION
PIN 14 = VCC
PIN 7 = GND
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 15
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1
Publication Order Number:
MC74HC125A/D
MC74HC125A, MC74HC126A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air
500
450
mW
Tstg
Storage Temperature
–65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
V
0
VCC
V
–55
+125
_C
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
http://onsemi.com
2
MC74HC125A, MC74HC126A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
–55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Vin = VIH
VOL
|Iout| v 3.6 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIL
|Iout| v 20 mA
Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 3.6 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
IOZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
V
–55 to
25_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
36
18
15
115
45
23
20
135
60
27
23
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
80
36
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
90
36
18
15
115
45
23
20
135
60
27
23
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Parameter
Symbol
Cin
Maximum Input Capacitance
−
10
10
10
pF
Cout
Maximum 3−State Output Capacitance (Output in High−Impedance State)
−
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD
30
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
http://onsemi.com
3
pF
MC74HC125A, MC74HC126A
SWITCHING WAVEFORMS
VCC
OE (HC125A)
50%
tf
tr
GND
VCC
90%
50%
10%
INPUT A
VCC
OE (HC126A)
GND
50%
GND
tPHL
tPLH
tPZL
90%
50%
10%
OUTPUT Y
OUTPUT Y
tPZH
10%
VOL
90%
VOH
tPHZ
50%
OUTPUT Y
Figure 1.
HIGH
IMPEDANCE
50%
tTHL
tTLH
tPLZ
HIGH
IMPEDANCE
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
VCC
OE
A
Y
HC125A
(1/4 OF THE DEVICE)
VCC
OE
A
Y
HC126A
(1/4 OF THE DEVICE)
http://onsemi.com
4
MC74HC125A, MC74HC126A
ORDERING INFORMATION
Package
Shipping†
MC74HC125ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74HC125ADR2G
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
MC74HC125ADTG
TSSOP−14
(Pb−Free)
96 Units / Rail
MC74HC125ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
MC74HC126ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74HC126ADR2G
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NLV74HC125ADG*
SOIC−14 NB
(Pb−Free)
55 Units / Rail
NLV74HC125ADR2G*
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
NLV74HC125ADTG*
TSSOP−14
(Pb−Free)
55 Units / Rail
NLV74HC125ADTR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Device
MC74HC126ADTR2G
NLV74HC126ADR2G*
NLV74HC126ADTR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
http://onsemi.com
5
MC74HC125A, MC74HC126A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC125A, MC74HC126A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74HC125A/D