NLAS54405 D

NLAS54405
Low THD+N Stereo SPDT
Switch with Click and Pop
Elimination
The NLAS54405 is a single supply, bidirectional, dual single−pole /
double−throw (SPDT) ultra-low distortion, high OFF−Isolation
analog switch that can pass analog signals that are positive and
negative with respect to ground. It is primarily targeted at consumer
and professional audio switching applications such as computer sound
cards and home theater products. The inputs can accommodate ground
referenced signals up to 2 VRMS while operating from a single 3.3 V or
5 V DC supply. The digital logic inputs are 1.8 V logic−compatible
when using a single 3.3 V or 5 V supply. It can be used in both AC− or
DC−coupled ground-referenced applications.
The NLAS54405 has a delayed turn−on feature and click/pop
circuitry at each signal pin that eliminates clicks and pops associated
with power−up/down conditions of the preceding amplifier outputs.
With −117 dB THD+N performance with a 2 VRMS signal into
20 kW load, superior signal muting, high PSRR and very flat
frequency response, the NLAS54405 meets the exacting requirements
of consumer and professional audio engineers.
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1
WQFN16
MT SUFFIX
CASE 488AP
MARKING DIAGRAM
AH M
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual SPDT Switch or 2−to−1 MUX
Clickless Audio Switching
2 VRMS Signal Switching from 3.3 V or 5 V Supply
−117 dB THD+N into 20 kW Load at 2 VRMS
−106 dB THD+N into 32 W Load at 3.9 mW
Signal to Noise Ratio: > 119 dBV
±0.006 dB Insertion Loss at 1 kHz, 20 kW Load
±0.002 dB Gain Variation 20 Hz to 20 kHz
107 dB Signal Muting into 20 kW Load
125 dB PSRR 20 Hz to 20 kHz
Single Supply Operation: 3.3 V or 5 V
16−Lead WQFN Package, 1.8 mm x 2.6 mm
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
AH = Specific Device Code
M = Date Code & Assembly Location
G
= Pb−Free Device
ORDERING INFORMATION
Device
Package
Shipping†
NLAS54405MT2TBG
WQFN16
(Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
•
•
•
•
•
•
Computer Sound Cards
Home Theater Audio Products
SACD / DVD Audio
DVD Player Audio Output Switching
Headsets for MP3 / Cellphone Switching
Hi−Fi Audio Switching Application
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 1
1
Publication Order Number:
NLAS54405/D
NLAS54405
5V_Supply
VDD
L1
L
L2
R1
R
R2
DIR_SEL
AC/DC
CLICK / POP
SUPPRESSION
and
LOGIC CONTROL
MUTE
SEL
CAP_SS
NLAS54405
GND
For 5 V operation, connect the 5 V_Supply pin to 5 V and float the VDD pin. For
3.3 V operation, connect the VDD pin to 3.3 V and float the 5 V_Supply pin.
Figure 1. Block Diagram
Table 1. FUNCTION TABLE
Inputs
Outputs
L1, R1
L2, R2
COM (L, R)
C/P SHUNTS
0
ON
OFF
OFF
OFF
OFF
1
OFF
ON
OFF
OFF
OFF
1
X
OFF
OFF
OFF
OFF
OFF
0
0
ON
OFF
OFF
OFF
ON
0
0
1
OFF
ON
OFF
ON
OFF
1
0
1
X
OFF
OFF
OFF
ON
ON
1
1
0
0
ON
OFF
OFF
OFF
OFF
1
1
0
1
OFF
ON
OFF
OFF
OFF
1
1
1
X
OFF
OFF
ON
OFF
OFF
AC/DC
DIR
MUTE
SEL
0
X
0
0
X
0
0
X
1
0
1
L1, R1
C/P SHUNTS
L2, R2
C/P SHUNTS
NOTE: MUTE, AC/DC, DIR: Logic “0” ≤ 0.5 V, Logic “1” ≥ 1.4 V or float with a 3.3 V supply or 5 V supply.
SEL: Logic “0” ≤ 0.5 V, Logic “1” ≥ 1.4 V with a 3.3 V supply or 5 V supply.
X = Don’t Care
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NLAS54405
Figure 2. WQFN16 Pinout – Top View
Table 2. PIN DESCRIPTIONS
Pin Name
Pin Number
Description
VDD
14
System power supply pin (+3 V to +3.6 V) (float pin for 5 V applications)
5V_Supply
15
5 V supply pin (+4.5 V to +5.5 V) (float pin for 3.3 V applications)
GND
5, 7, 8
CAP_SS
13
Delayed turn−on capacitor pin
MUTE
1
Signal mute control pin
Ground connection
SEL
4
Input select control pin
AC/DC
16
AC/DC select control pin
DIR_SEL
6
Direction select control pin
R
3
Analog switch common pin for Right
L
2
Analog switch common pin for Left
R2, L2
9, 11
R1, L1
10, 12
Analog switch normally open pin
Analog switch normally closed pin
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3
NLAS54405
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
VDD
Positive 3 V DC Supply Voltage
−0.5 to +4.1
V
5V_Supply
Positive 5 V DC Supply Voltage
−0.5 to +7.0
V
VIS
Analog Input/Output Voltage (L1, L2, R1, R2, L, R)
−3.1 to VDD + 0.5
V
VIN
Digital Select Input Voltage (SEL, MUTE, AC/DC, DIR_SEL)
−0.5 to VDD + 0.5
V
IIO
Switch Continuous Current (L1, L2, R1, R2, L, R)
±300
mA
Switch Peak Current (L1, L2, R1, R2, L, R)
(Pulsed 1ms, 10% Duty Cycle, Max).
±500
mA
PD
Power Dissipation in Still Air
800
mW
TL
Lead Temperature, 1 mm from Case for 10 seconds
260
°C
IIO_PK
TJ
Junction Bias Under Bias
150
°C
qJA
Thermal Resistance
80
°C/W
Ts
Storage Temperature
−65 to +150
°C
MSL
Moisture Sensitivity
FR
Flammability Rating
ESD
IL
Level 1
Oxygen Index: 30% − 35%
ESD Protection
UL94−V0 (0.125 in)
Human Body Model
Charged Device Model
Latch−up Current, Above VCC and below GND at 125°C (Note 1)
> 1000
> 2000
V
±300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VDD
Positive 3 V DC Supply Voltage
3.0
3.6
V
5V_Supply
Positive 5 V DC Supply Voltage
4.5
5.5
V
VS
Switch Input / Output Voltage (L1, L2, R1, R2, L, R)
−2.9
VDD
V
VIN
Digital Select Input Voltage
GND
VDD
V
TA
Operating Temperature Range
−40
+85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NLAS54405
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
3.3 V Supply: VDD = +3.0 V to +3.6 V, GND = 0 V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2 VRMS, RLOAD = 20 kW,
f = 1 kHz, VSELH = VMUTEH = 1.4 V, VSELL = VMUTEL = 0.5 V, CAP_SS = 0.1 mF, (Note 2), Unless otherwise specified.
Supply
(V)
Test Conditions
Parameter
Temp
Min
(5C) (Notes 3, 4)
Max
Typ
(Notes 3, 4)
Units
ANALOG SWITCH CHARACTERISTICS
3.3, 5
Analog Signal Range,
VANALOG
ON−Resistance, rON
VDD = 3.3 V, IR or IL = 80 mA, VLx or VRx
3.3
= −2.828 V to +2.828 V (See Figure 6)
−
2
−
VRMS
W
25
−
2.1
−
Full
−
2.5
−
25
−
0.046
−
W
Full
−
0.23
−
W
25
−
0.047
0.05
W
Full
−
0.092
−
25
225
300
375
Full
−
345
−
25
−
< −117
−
VSIGNAL = 1.9 VRMS, f = 1 kHz,
A−weighted filter, RLOAD = 20 kW
25
−
< −117
−
VSIGNAL = 1.8 VRMS, f = 1 kHz,
A−weighted filter, RLOAD = 20 kW
25
−
< −117
−
VSIGNAL = 0.707 VRMS, f = 1 kHz,
A−weighted filter, RLOAD = 32 W
25
−
< −106
−
3.3, 5
25
−
> 119
−
dBV
rON Matching Between
Channels, DrON
VDD = 3.3 V, IR or IL = 80 mA, VLx or VRx
rON Flatness, rFLAT(ON)
VDD = 3.3 V, IR or IL = 80 mA, VLx or VRx
3.3
= Voltage at max rON over −2.828 V to
+2.828 V (Note 7)
3.3
= −2.828 V, 0 V, +2.828 V (Note 5)
L, R, Lx, Rx Pull−down
Resistance
Full
VDD = 3.6 V, VLx or VRx = −2.83 V, 2.83 V,
VL or VR = −2.83 V, 2.83 V, VAC/DC = 0 V,
3.6
VMUTE = 3.6 V, measure current, calculate resistance.
kW
DYNAMIC CHARACTERISTICS
THD+N
VSIGNAL = 2 VRMS, f = 1 kHz, A−weighted filter, RLOAD = 20 kW
3.3, 5
dB
SNR
f = 20 Hz to 20 kHz, A−weighted filter, inputs grounded, RLOAD = 20 kW or 32 W
Insertion Loss, GON
f = 1 kHz, RLOAD = 20 kW
3.3
25
−
±0.006
−
dB
Gain vs Frequency, Gf
f = 20 Hz to 20 kHz, RLOAD = 20 kW, reference to GON at 1 kHz
3.3
25
−
±0.002
−
dB
Stereo Channel Imbalance
L1 and R1, L2 and R2
f = 20 Hz to 20 kHz, RLOAD = 20 kW
3.3
25
−
±0.001
−
dB
OFF−Isolation (Muting)
f = 20 Hz to 22 kHz, L = R = 2 VRMS,
RLOAD = 20 kW, MUTE = AC/DC =
3.3 V, DIR_SEL = GND, SEL = “X”
3.3, 5
25
−
107
−
dB
f = 20 Hz to 22 kHz, L1, R1, L2, R2 =
2 VRMS, RLOAD = 20 kW, MUTE = AC/DC
= DIR_SEL = 3.3 V, SEL = “X”
25
−
108.8
−
f = 20 Hz to 22 kHz, VL or VR =
0.7 VRMS, RLOAD = 32 W
25
−
108.5
−
2. VIN = input voltage to perform proper function.
3. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
5. Flatness is defined as the difference between maximum and minimum value of ON−resistance at the specified analog signal voltage points.
6. Limits established by characterization and are not production tested.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max
rON value.
8. Crosstalk is inversely proportional to source impedance.
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NLAS54405
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
3.3 V Supply: VDD = +3.0 V to +3.6 V, GND = 0 V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2 VRMS, RLOAD = 20 kW,
f = 1 kHz, VSELH = VMUTEH = 1.4 V, VSELL = VMUTEL = 0.5 V, CAP_SS = 0.1 mF, (Note 2), Unless otherwise specified.
Supply
(V)
Test Conditions
Parameter
Temp
Min
(5C) (Notes 3, 4)
Max
Typ
(Notes 3, 4)
Units
dB
DYNAMIC CHARACTERISTICS
Crosstalk (Channel−to−
Channel)
RL = 20 kW, f = 20 Hz to 20 kHz, VSIGNAL = 2 VRMS, signal source impedance
= 20 W, (Note 8)
3.3
RL = 32 W, f = 20 Hz to 20 kHz, VSIGNAL
= 0.7 VRMS, signal source impedance =
20 W, (Note 8)
PSRR
f = 1 kHz, VSIGNAL= 100 mVRMS, inputs
grounded
3.3, 5
f = 20 kHz, VSIGNAL= 100 mVRMS, inputs grounded
25
−
97
−
25
−
108
−
25
−
125
−
25
−
125
−
dB
Bandwidth, −3 dB
RLOAD = 50 W
3.3
25
−
450
−
MHz
ON to Mute Time,
TTRANS−OM
CAP_SS = 0.1 mF
3.3
25
−
250
−
ns
Mute to ON Time,
TTRANS−MO
CAP_SS = 0.1 mF, RLOAD = 32 W, VIS =
1.5 V
3.3
25
−
1680
−
ms
Turn−ON Time, tON
VDD = 3.3 V, VLx or VRx = 1.5 V, VMUTE =
0 V, RL = 32 W (See Figure 3)
3.3
25
−
11
−
ms
Turn−OFF Time, tOFF
VDD = 3.3 V, VLx or VRx = 1.5 V, VMUTE =
0 V, RL = 32 W (See Figure 3)
3.3
25
−
95
−
ns
Break−Before−Make Time
Delay, tD
VDD = 3.6 V, VLx or VRx = 1.5 V, VMUTE =
0 V, RL = 32 W (See Figure 4)
3.6
25
−
10
−
ms
OFF−Isolation
RL = 50 W, f = 1 MHz, VL or VR =
1 VRMS (See Figure 5)
3.3
25
−
68
−
dB
Crosstalk (Channel−to−
Channel)
RL = 50 W, f = 1 MHz, VL or VR =
1 VRMS (See Figure 7)
3.3
25
−
77
−
dB
Lx, Rx OFF Capacitance,
COFF
f = 1 MHz, VLx or VRx = VL or VR = 0 V
(See Figure 8)
3.3
25
−
3.3
−
pF
L, R ON Capacitance,
CCOM(ON)
f = 1 MHz, VLx or VRx = VCOM = 0 V
(See Figure 8)
3.3
25
−
10.5
−
pF
3.3
Full
3
−
3.6
V
5
Full
4.5
−
5.5
V
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
5V_Supply = Float
Power Supply Range,
5V_Supply
VDD = Float
Positive Supply
Current, I+
VDD = +3.6 V, VMUTE = 0 V,
3.6
VSEL = 0 V or VDD
3.6
VDD = +3.6 V, VMUTE = VDD,
VSEL = 0 V or VDD
3.6
VDD = +3.6 V, VMUTE = 0 V,
VSEL = 1.8 V
25
−
54
65
mA
Full
−
59
−
mA
25
−
14
20
mA
Full
−
15
−
mA
25
−
55
65
mA
Full
−
58
−
mA
2. VIN = input voltage to perform proper function.
3. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
5. Flatness is defined as the difference between maximum and minimum value of ON−resistance at the specified analog signal voltage points.
6. Limits established by characterization and are not production tested.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max
rON value.
8. Crosstalk is inversely proportional to source impedance.
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NLAS54405
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
3.3 V Supply: VDD = +3.0 V to +3.6 V, GND = 0 V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2 VRMS, RLOAD = 20 kW,
f = 1 kHz, VSELH = VMUTEH = 1.4 V, VSELL = VMUTEL = 0.5 V, CAP_SS = 0.1 mF, (Note 2), Unless otherwise specified.
Supply
(V)
Test Conditions
Parameter
Temp
Min
(5C) (Notes 3, 4)
Max
Typ
(Notes 3, 4)
Units
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL,
VMUTEL
3.3, 5
Full
−
−
0.5
V
Input Voltage High, VSELH,
VMUTEH
3.3, 5
Full
1.4
−
−
V
Input Current, ISELH, ISELL
VDD = 3.6 V, VMUTE = 0 V,
VSEL = 0 V or VDD
3.6
Full
−0.5
0.01
0.5
mA
Input Current, IAC/DCL,
IDIR_SELL
VDD = 3.6 V, VAC/DC, VDIR_SEL = 0 V,
VMUTE = Float, VSEL = VDD
3.6
Full
−1.3
−0.7
0.3
mA
Input Current, IAC/DCH,
IDIR_SELH
VDD = 3.6 V, VAC/DC, VDIR_SEL = VDD,
VMUTE = 0 V, VSEL = 0 V
3.6
Full
−0.5
0.01
0.5
mA
Input Current, IMUTEL
VDD = 3.6 V, VSEL = VDD, VMUTE = 0 V
3.6
Full
−1.3
−0.7
0.3
mA
Input Current, IMUTEH
VDD = 3.6 V, VSEL = 0 V, VMUTE = VDD
3.6
Full
−0.5
0.01
0.5
mA
2. VIN = input voltage to perform proper function.
3. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
5. Flatness is defined as the difference between maximum and minimum value of ON−resistance at the specified analog signal voltage points.
6. Limits established by characterization and are not production tested.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max
rON value.
8. Crosstalk is inversely proportional to source impedance.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
TEST CIRCUITS AND WAVEFORMS
MEASUREMENT POINTS
TEST CIRCUIT
Figure 3. Switching Times
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NLAS54405
MEASUREMENT POINTS
TEST CIRCUIT
Figure 4. Break−Before−Make Time
Figure 5. Off−Isolation Test Circuit
Figure 6. rON Test Circuit
Figure 7. Crosstalk Test Circuit
Figure 8. Capacitance Test Circuit
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NLAS54405
3.3 V
VDD
5V_Supply
LOUT
L1
L
L2
AUDIO
CODEC
R1
ROUT
R
R2
DIR_SEL
AC/DC
MUTE
SEL
CAP_SS
CPU
0.1 μF
TURN−ON DELAY
CAPACITOR
FRONT PANEL
LINE OUT /
HEADPHONE
JACK
REAR PANEL
LINE OUT /
HEADPHONE
JACK
CLICK / POP
SUPPRESSION
and
LOGIC CONTROL
GND
NLAS54405
3.3 V
5V_Supply
VDD
L1
L
FRONT PANEL
LINE OUT /
HEADPHONE
JACK
L2
R1
R
R2
DIR_SEL
AC/DC
MUTE
SEL
CAP_SS
CPU
0.1 μF
TURN−ON DELAY
CAPACITOR
CLICK / POP
SUPPRESSION
and
LOGIC CONTROL
GND
NLAS54405
Figure 9. Sound Card AC Coupled Application Block Diagrams
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LOUT
AUDIO CODEC
ROUT
LOUT
AUDIO CODEC
ROUT
NLAS54405
Detailed Description
circuitry at each of the signal pins (L, R, L1, L2, R1, and R2).
A pin’s C/P shunt circuitry is activated or deactivated
depending on the logic levels applied at the AC/DC and
DIR_SEL control pins. This shunt circuitry serves two
functions:
1. In an AC coupled application, they are activated
and directed to the source side of the switch to
suppress or eliminate click/pop noise in the
speaker load when powering up or down of the
audio CODEC drivers.
2. For superior muting, the C/P shunt circuitry is
activated and directed to the load side of the
switch which gives >107 dB of OFF−Isolation
when driving a 10 k / 20 kW receiver load with an
audio signal in the range of 20 Hz to 22 kHz.
If the AC/DC pin is driven LOW, all C/P shunt circuitry
at all the signal pins (L, R, L1, R1, L2, and R2) are deactivated
and not operable.
If the AC/DC pin is driven HIGH, then the logic at the
DIR_SEL pin will determine whether the L and R (COM)
C/P shunt circuitry is activated or the L1, L2, R1, and R2
(NOx, NCx) C/P shunt circuitry is activated. When the
DIR_SEL is driven LOW, the L1, R1, L2, R2 C/P shunt
circuitry will be activated while the L and R C/P shunt
circuitry will be deactivated. When the DIR_SEL is driven
HIGH, the L and R C/P shunt circuitry will be activated
while the L1, R1, L2, R2 C/P shunt circuitry will be
deactivated. Note: Shunt circuitry that is activated will be
turned ON when a switch cell is turned OFF and will be OFF
when a switch cell is turned ON.
The NLAS54405 is a single supply, bidirectional, dual
single pole/double throw (SPDT) ultra−low distortion, high
OFF−Isolation analog switch. It was designed to operate
from either a 3.3 V or 5 V single supply. When operated with
a 3.3 V or 5 V single supply, the switches can accommodate
±2.828 VPEAK (2 VRMS) ground−referenced analog signals.
The switch rON flatness across this range is extremely small
resulting in excellent THD+N performance (0.0002% with
20 kW load and 0.0005% with 32 W load at 707 mVRMS).
The T−Type configuration of the switch cells prevents
signals from getting through to the output when a switch is
in the OFF−state providing for superior mute performance
(>107 dB) in audio applications.
The NLAS54405 has special circuitry to eliminate click
and pops in the speakers during power−up and power−down
of the audio CODEC drivers, during removal and insertion
of headphones, and while switching between sources and
loads. The NLAS54405 was designed primarily for
consumer and professional audio switching applications
such as computer sound cards and home theater products.
The “Sound Card AC Coupled Application Block
Diagrams” show two typical sound card applications. In the
upper block diagram, the NLAS54405 is being used to route
a single stereo source to either the front or back panel line
outs of the computer sound card. In the lower block diagram,
the NLAS54405 is being used to multiplex two stereo
sources to a single line out of the computer sound card.
SPDT Switch Cell Architecture and Performance
Characteristics
The normally open (L2, R2) and normally closed (L1, R1)
of the SPDT switches are T−Type switches that have a
typical rON of 2.1 W and an OFF−isolation of > 107 dB. The
low on−resistance (2.1 W and rON flatness (0.047 W) provide
very low insertion loss and minimal distortion to
applications that require hi−fidelity signal reproduction.
The SPDT switch cells have internal charge pumps that
allow for signals to swing below ground. They were
specifically designed to pass audio signals that are ground
referenced and have a swing of ±2.828 VPEAK while driving
either 10 k / 20 kW (receiver) or 32 W (headphone) loads.
Each switch cell incorporates special circuitry to delay the
switch transition from the OFF−state (high impedance) to
the ON−state (2.1 W). This delayed turn−on may help reduce
clicks and pops in the speaker by matching turn−on time to
transient switching events. The delayed turn−on time is
determined by the capacitor value of the delayed turn−on
capacitor connected at the CAP_SS pin, the speaker load and
the DC level of the audio signal. With a 0.1 mF ceramic chip
capacitor, a 32 W load and 1.5 V DC level, the delayed
turn−on is approximately 1700 ms. The delayed turn−on may
be disabled by floating the CAP_SS pin.
In addition to the delayed turn−on feature of the in line
switches, the part has special click and pop (C/P) shunt
Supply Voltage, Signal Amplitude, and Grounding
The power supply connected at VDD or the 5 V_Supply
pin provides power to the NLAS54405 part. The
NLAS54405 is a single supply device that was designed to
be operated with a 3.3 V ±10% DC supply connected at the
VDD pin or a 5 V ±10% DC supply connected at the
5 V_Supply pin.
It was specifically designed to accept ground referenced
2 VRMS (±2.828 VPEAK) audio signals at its signal pins
while driving either 10 k / 20 kW receiver loads or 32 W
headphone loads.
When using the part in a 3.3 V application, the
5 V_Supply pin should be left floating. A 0.1 mF decoupling
capacitor should be connected from the VDD pin to ground
to minimize power supply noise and transients. This
capacitor should be located as close to the pin as possible.
The part also has a 5 V supply pin (5 V_Supply) to allow
it to be used in 5 V ±10% applications. Special circuitry
within the device converts the 5 V, connected at the
5 V_Supply pin, to 3.3 V to properly power the internal
circuitry of the device.
When using the part in a 5 V application, the VDD pin
should be left floating. A 0.1 mF decoupling capacitor should
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10
NLAS54405
be connected from the 5 V_Supply pin to ground to
minimize power supply noise. This capacitor should be
located as close to the pin as possible.
Grounding of the NLAS54405 should follow a star
configuration (see Figure 10). All grounds of the IC should
be directly connected to the power supply ground return
without cascading to other grounds. This configuration
isolates shunt currents of the Click and Pop transients from
the IC ground and optimizes device performance.
Table 3 indicates how mute turn delay is affected by the
CAP_SS capacitor value and the switch input DC voltage
level.
On to Mute
When the MUTE pin is driven HIGH, the switches will
turn off quickly (50 ns) and the active shunt switches will
turn on quickly.
Off−Isolation in the Mute State
3.3 V
VDD
5V_Supply
When in the mute state, the level of OFF−Isolation across
the audio band is dependent on the signal amplitude,
external loading, and location of the activated C/P
(click/pop) shunt circuitry. During muting, the logic of the
NLAS54405 can be configured to activate the C/P shunt
circuitry on the load side of the switch or on the source side
of the switch, or deactivated on both sides of the switch.
With a 0.707 VRMS signal driving a 32 W headphone load,
the location of the C/P shunt circuitry has little effect on the
off−isolation performance (>109 dB of off−isolation in all
configurations), see Figure 12.
With a 2 VRMS signal driving a 20 kW amplifier load, the
best OFF−Isolation is achieved by placing the C/P shunt
circuitry on the load side of the switch (>120 dB across the
audio band).
Note: For AC coupled applications, when powering up or
down of the audio drivers, the C/P shunts should be activated
on the source side of the switch. See “Click and Pop
Operation”.
When using the switch for muting of the audio signal, the
C/P shunt circuitry should be deactivated on the source side
of the switch and directed to the load side of the switch for
best possible OFF−Isolation.
L1
L
L2
0.1 μF
R1
R
R2
DIR_SEL
AC/DC
MUTE
SEL
CAP_SS
CLICK / POP
SUPPRESSION
and
LOGIC CONTROL
GND1
GND2
GND3
NLAS54405
Figure 10. Star Grounding Configuration
Mute Operation
When the MUTE logic pin is driven HIGH, the part will go
into the mute state. In the mute state, all switches of the SPDTs
are open while the T−Shunt switches are closed. In addition,
any activated click and pop shunt circuitry at the signal pins
is turned on. See “Logic Control” below for more details.
Logic Control
The NLAS54405 has four logic control pins; the AC/DC,
DIR_SEL, MUTE, and SEL. The MUTE and SEL control
pins determine the state of the switches. The AC/DC and
DIR_SEL control pins determine the location of the C/P
(click/pop) shunt circuitry and if it will be active or not. See
“Truth Table”.
The NLAS54405 logic is 1.8 V CMOS compatible (Low
v 0.5 V and High w 1.4 V) over a supply range of 3.0 V to
3.6 V at the VDD pin or 4.5 V to 5.5 V at the 5 V_Supply pin.
This allows control via 1.8 V or 3 V m−controller.
Mute to On
When the MUTE pin is driven LOW, the NLAS54405 will
transition to the ON−state in the following sequence:
1. All active shunt switches turn off quickly.
2. The resistance of the switches selected by the SEL
pin will turn on from their high OFF−resistance to
their ON−resistance of 2.1 W after a time delay. The
delayed turn−on time is determined by the capacitor
value of the delayed turn−on capacitor connected
at the CAP_SS pin, the speaker load and the DC
level of the audio signal. See Figures 30 and 31.
SEL, Mute Control Pins
The state of the SPDT switches of the NLAS54405 device
is determined by the voltage at the MUTE pin and the SEL
pin. The SEL control pin is only active when MUTE is logic
“0”. The MUTE has an internal pull−up resistor to the
internal 3.3V supply rail and can be driven HIGH or
tri−stated (floated) by the m−processor.
These pins are 1.8 V logic compatible. When powering
the part by the VDD pin, the logic voltage can be as high as
the VDD voltage which is typically 3.3 V. When powering
the part by the 5 V_Supply pin, the logic voltage can be as
high as the 5 V_Supply voltage which is typically 5 V.
Table 3. SWITCH TURN−ON DELAY FOR A 32 W LOAD
Capacitor Value
VIS DC Level
Turn−On Delay
No Capacitor
1.5 V
27.4 ms
0.05 mF
1.5 V
543 ms
0.1 mF
1.5 V
1680 ms
No Capacitor
60 mV
24.3 ms
0.05 mF
60 mV
38 ms
0.1 mF
60 mV
50 ms
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11
NLAS54405
AC Coupled Click and Pop Operation
Logic Levels:
MUTE = Logic “0” (Low) when v 0.5 V
MUTE = Logic “1” (High) when w 1.4 V or floating
SEL = Logic “0” (Low) when v 0.5 V
SEL = Logic “1” (High) when w 1.4 V
Single supply audio drivers have their signal biased at a
DC offset voltage, usually at 1/2 the DC supply voltage of
the driver. As this DC bias voltage comes up or goes down
during power up or down of the driver, a transient can be
coupled into the speaker load through the DC blocking
capacitor (see the “Sound Card AC Coupled Application
Block Diagrams”).
When a driver is off and suddenly turned on, the rapidly
changing DC bias voltage at the output of the driver will
cause an equal voltage at the input side of the switch due to
the fact that the voltage across the blocking capacitor cannot
change instantly. If the switch is in audio mode or there is no
low impedance path to discharge the capacitor voltage at the
input of the switch, before turning on the switch, a transient
discharge will occur in the speaker, generating a click and
pop noise.
Proper elimination of a click/pop transient at the speaker
load while powering up or down of the audio driver requires
that the NLAS54405 have its C/P shunts activated on the
source side of the switch and then placed in mute mode. This
allows the transient generated by the audio drivers to be
discharged through the click and pop shunt circuitry.
Once the driver DC bias has reached VDD/2 and the
transient on the switch side of the DC blocking capacitor has
been discharged to ground through the C/P shunt circuitry,
the switches can be turned on and connected through to the
speaker loads without generating an undesirable click/pop in
the speakers.
With a typical DC blocking capacitor of 220 mF and the
C/P shunt circuitry designed to have a resistance of 40 W,
allowing a 100 ms wait time to discharge the transient before
placing the switch in the audio mode, will prevent the
transient from getting through to the speaker load. See
Figures 28 and 29.
AC/DC and DIR_SEL Control Pins
The NLAS54405 contains C/P (click/pop) shunt circuitry
on its COM pins (L, R) and on its signal pins (L1, R1, L2, R2).
The activation of this circuitry and whether it is located on
the COM or signal side of the switch is determined by the
logic levels applied at the AC/DC and DIR_SEL pins. The
DIR_SEL control pin is only active when AC/DC is logic
“1”.
Note: Any activated C/P shunt circuitry is ON when in the
mute state (MUTE = Logic “1”) and OFF in the audio state
(MUTE = Logic “0”).
When AC/DC is logic “0”, all of the C/P shunt circuitry
on both sides of the switch is deactivated and not operable.
When AC/DC is logic “1”, then the DIR_SEL logic level
determines whether the shunt circuitry will be activated on
the COM side of the switch or on the signal side of the
switch. When DIR_SEL = Logic “1”, the C/P shunts on the
COM side (L,R) are activated and inoperable on the signal
side (L1, R1, L2, R2) of the switch. When DIR_SEL = Logic
“0”, the C/P shunts are activated on the signal side (L1, R1,
L2, R2) and inoperable on the COM side (L, R).
Logic Levels:
AC/DC, DIR_SEL = Logic “0” (Low) when v 0.5 V
AC/DC, DIR_SEL = Logic “1” (High) when w 1.4 V or
Floating.
The AC/DC and DIR_SEL have internal pull−up resistors
to the internal 3.3 V supply rail and can be driven HIGH or
tri−stated (floated by the m−processor). They should be
driven to ground for a logic “0” (Low).
Note: For 5 V applications, the AC/DC and DIR_SEL pins
should never be driven to the external 5 V rail. They need to
be driven with 1.8 V logic or 3 V logic circuit.
Click and Pop Elimination when Connected to High
Impedance Source and Load
By design, in order to flatten the RON resistance of the
switch across the signal range (±3 V) a current gets added to
the signal path. When the NLAS54405 part is connected to
a high impedance source (i.e. AC coupled to the input of the
switch) and a high impedance load, (such as the impedance
of a 20 kW to 100 kW preamplifier stage) a DC offset voltage
will be present on the signal line in the range of 35 mV to
135 mV.
When the switch is turned off, this offset voltage gets
pulled to ground. During switching, this change in the offset
voltage can cause a click and pop noise to be heard in the
downstream speaker.
Placing a 1 kW resistor from the output of the switch to
ground will lower the offset voltage to around 1.5 mV,
thereby effectively eliminating the click and pop noise. The
1 kW resistor is small enough to reduce the voltage offset
significantly while not increasing power dissipation
AC Coupled or DC Coupled Operation
The Audio CODEC drivers can be directly coupled to the
NLAS54405 when the audio signals from the drivers are
ground referenced or do not have a significant DC offset
voltage, <50 mV. Otherwise, the signal should be AC
coupled to the NLAS54405 part.
Click and Pop Operation
The NLAS54405 has special circuitry to eliminate click
and pops in the speakers during power−up and power−down
of the Audio CODEC Drivers and during removal and
insertion of headphones.
A different click and pop scheme is required depending on
whether the audio CODEC drivers are AC coupled or DC
coupled to the inputs of the NLAS54405 part.
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12
NLAS54405
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be
used to provided additional protection to limit the current in
the event that the voltage at a signal pin goes below ground
by more than −3 V or above the VDD rail and the logic pin
goes below ground or above the VDD rail.
Logic inputs can be protected by adding a 1 kW resistor in
series with the logic input (see Figure 11). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub−microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins, as shown in Figure 11 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current and to clamp when the voltage reaches
the overvoltage limit.
dramatically. Power consumption will need to be considered
when using a smaller impedance under this scenario.
When connected to a low impedance load such as
headphones (32 W), the current added to the signal line results
in a minimal DC offset voltage on the signal line and does
not cause click and pop noise when the switch is turned off.
DC Coupled Click and Pop Operation
The NLAS54405 can pass ground−referenced audio
signals which allows it to be directly connected to audio
drivers that output ground−referenced audio signals,
eliminating the need for a DC blocking capacitor.
Audio drivers that swing around ground, however, do
generate some DC offset, from a few millivolts to tens of
millivolts. When switching between audio channels or
muting the audio signal, these small DC offset levels of the
drivers can generate a transient that can cause unwanted
clicks and pops in the speaker loads.
In a DC coupled application, the C/P shunt resistors
placed at the source side of the switch have no effect in
eliminating the transients at the speaker loads when
transitioning in and out of the mute state or switching
between channels. In fact, having these C/P shunts active on
the source side unnecessarily increases the power
consumption. So, for DC coupled connection, the C/P shunt
circuitry should not be applied at the source (driver) side of
the switch.
For DC coupled applications, the NLAS54405 has a
special turn−on delay feature that delays the connection
from the audio driver output to the speaker load when
turning on a switch channel. The delayed turn−on time is
determined by the capacitor value of the delayed turn−on
capacitor connected at the CAP_SS pin, the speaker load and
the DC level of the audio signal.
The turn−on delay may help reduce clicks and pops in the
speaker by matching turn−on time to transient switching
events. A delayed turn−on capacitor value of 0.1 mF, coupled
with a 32 W load and a 1.5 V DC level, provides a turn−on
delayed of approximately 1700 ms. See Figures 30 and 31.
See “MUTE to ON” section for more detail of how turn−on
delay works.
Figure 11. Overvoltage Protection
High−Frequency Performance
In 50 W systems, the NLAS54405 has a −3 dB bandwidth
of 450 MHz (see Figure 32). The frequency response is very
consistent over varying analog signal levels.
An OFF−switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed−
through from a switch’s input to its output. OFF−Isolation is
the resistance to this feed−through, while crosstalk indicates
the amount of feed−through from one switch to another.
Figure 33 details the high OFF−Isolation and crosstalk
rejection provided by this part. At 1 MHz, Off−Isolation is
about 68 dB in 50 W systems, decreasing approximately
20 dB per decade as frequency increases. Higher load
impedances decrease OFF−Isolation and crosstalk rejection
due to the voltage divider action of the switch off impedance
and the load impedance.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing
is required to protect the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes or diode stacks from the
pin to VDD and to GND (see Figure 11). To prevent forward
biasing these diodes, VDD must be applied before any input
signals, and the signal voltages must remain between VDD
and −3 V and the logic voltage must remain between VDD
and ground.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
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13
NLAS54405
TYPICAL CHARACTERISTICS
Figure 12. On−Resistance vs. Switch Voltage
Figure 13. Off−Isolation, 2 VRMS Signal, 20 kW
Load
Figure 14. Off−Isolation, 0.707 VRMS Signal,
32 W Load
Figure 15. Channel−to−Channel Crosstalk
Figure 16. Channel−to−Channel Crosstalk
Figure 17. Insertion Loss vs. Frequency
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14
NLAS54405
TYPICAL CHARACTERISTICS
Figure 18. Gain vs. Frequency
Figure 19. Stereo Imbalance vs. Frequency
Figure 20. THD+N vs. Signal Levels vs.
Frequency
Figure 21. THD+N vs. Signal Levels vs.
Frequency
Figure 22. THD+N vs. Signal Levels vs.
Frequency
Figure 23. THD+N vs. Signal Levels vs.
Frequency
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15
NLAS54405
TYPICAL CHARACTERISTICS
Figure 24. THD+N vs. Signal Levels vs.
Frequency
Figure 25. THD+N vs. Signal Levels vs.
Frequency
Figure 26. PSRR vs. Frequency
Figure 27. PSRR vs. Frequency
Figure 28. 20 kW AC Coupled Click / Pop
Reduction
Figure 29. 32 W AC Coupled Click / Pop
Reduction
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16
NLAS54405
TYPICAL CHARACTERISTICS
Figure 30. Turn−on Delay (0.1 mF) Click/Pop
Reduction
Figure 31. Turn−on Delay (0.05 mF) Click/Pop
Reduction
Figure 32. Frequency Response
Figure 33. Crosstalk and Off−Isolation
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17
NLAS54405
PACKAGE DIMENSIONS
WQFN16, 1.8x2.6, 0.4P
CASE 488AP
ISSUE B
D
PIN 1 REFERENCE
2X
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
EXPOSED Cu
0.15 C
B
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
A1
DETAIL B
A
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.08 C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
L
L1
L2
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.050
0.20 REF
0.15
0.25
1.80 BSC
2.60 BSC
0.40 BSC
0.30
0.50
0.00
0.15
0.40
0.60
MOUNTING FOOTPRINT*
A1
DETAIL A
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
L1
0.15 C
0.10 C
L
L
A
C
A3
0.562
0.0221
8
15 X L
0.400
0.0157
9
4
0.225
0.0089
1
e
1
2.900
0.1142
12
16
L2
16 X
b
0.463
0.0182
0.10 C A B
0.05 C
1.200
0.0472
NOTE 3
2.100
0.0827
SCALE 20:1
mm Ǔ
ǒinches
For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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www.onsemi.com
18
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NLAS54405/D