UCT NT R O D A C EM E a t P E r T L ® E P t en e OL RE OBS ENDED upport C om/tsc lS MM sil.c ECO echnica w.inter R O T w N r w Sheet uData I L or act o cont -INTERS 8 1-88 August 2000 Two control inputs, ENABLE and DISABLE, are used to determine the direction of data flow, and to set both the in puts and outputs in the high impedance state. The control inputs may be driven by either TTL or CMOS logic drivers capable of sinking one standard TTL load. The HS-3374RH is a non-inverting version of the industry standard CD40116. The non-inverting outputs of the HS-3374RH reduce PC board chip count by eliminating the need to restore data back to a non-inverted format. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-96786. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened EPI-CMOS - Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 105RAD(Si) - Latch-Up Immune . . . . . . . >1 x 1012RAD(Si)/s (Note 1) • Low Propagation Delay Time - Typical CMOS to TTL Pre-RAD . . . . . . . . . . . . . . . 40ns - Typical CMOS to TTL Post 100KRAD . . . . . . . . . . 40ns - Typical TTL to CMOS Pre-RAD . . . . . . . . . . . . . . . 50ns - Typical TTL to CMOS Post 100KRAD . . . . . . . . . . 50ns • Low Standby Power • +10V CMOS and +5V TTL Power Supply Inputs • Eight Non-Inverting Three-State Input/Output Channels • No External TTL Input Pull-Up Resistors Required • High TTL Sink Current • Equivalent to Sandia SA2996 • Military Temperature Range . . . . . . . . . . . . -55oC to 125oC NOTE: 1. For operation at 10V and transient levels above 1 x 1010RAD(Si)/s, please refer to Application Note 401. Pinout Ordering Information INTERNAL MKT. NUMBER HS-3374RH MIL-STD-1835, CDIP2-T22 (SBDIP) TOP VIEW TEMP. RANGE (oC) 5962R9678601QWC HS1-3374RH-8 -55 to 125 5962R9678601VWC HS1-3374RH-Q -55 to 125 Functional Diagram VDD = 1 VCC = 22 GND = 11 DISABLE 13 8 8 2-9 LEVEL SHIFTER ENABLE 3038.2 • Electrically Screened to SMD # 5962-96786 The Intersil HS-3374RH is a radiation hardened 8-bit bidirectional level converter designed to interface CMOS logic levels with TTL logic levels in radiation hardened bus oriented systems. The HS-3374RH is fabricated using a radiation hardened EPI-CMOS process and features eight parallel bidirectional buffer/level converters. CMOS IN/OUT File Number Features Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter ORDERING NUMBER HS-3374RH TTL OUT (IN) 14-21 CMOS INPUT/OUTPUT VDD 1 22 VCC A0 2 21 B0 A1 3 20 B1 A2 4 19 B2 A3 5 18 B3 A4 6 17 B4 A5 7 16 B5 A6 8 15 B6 A7 9 14 B7 ENABLE 10 GND 11 TTL INPUT/OUTPUT 13 DISABLE 12 NC 10 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HS-3374RH Functional Block Diagram 1 OF 8 IDENTICAL CIRCUITS VDD VDD VCC DISABLE VCC 2 (3, 4, 5, 6, 7, 8, 9) A1 CMOS INPUT (OUTPUT) B1 TTL OUTPUT (INPUT) VDD D LEVEL SHIFTER 21 (20, 19, 18, 17, 16, 15, 14) LEVEL SHIFTER 13 GND D VDD ENABLE E LEVEL SHIFTER 10 E GND GND GND NOTES: 2. Enable and disable are TTL type inputs 3. D and E outputs are common to all 8 channels INPUT (OUTPUT) TRUTH TABLE OUTPUT (INPUT) ENABLE DISABLE X 0 Convert CMOS Level to TTL Level 21 1 1 Convert TTL Level to CMOS Level B1 20 0 1 High Impedance (Z) 4 B2 19 A3 5 B3 18 A4 6 B4 17 A5 7 B5 16 A6 8 B6 15 A7 9 B7 14 DATA TERMINAL NUMBER DATA TERMINAL NUMBER A0 2 B0 A1 3 A2 FUNCTION 0 = Low Level 1 = High Level X = Don’t Care Z = High Impedance on Both CMOS and TTL sides. NOTE: An important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of regenerative latches on the following HS-3374RH pins: A0 - 7. The functional block diagram depicts one of these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-state condition. A transient drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions. WARNING: Do not activate the Disable input by hardwiring to any TTL input pins. This is an incorrect mode of operation. 2 HS-3374RH Die Characteristics DIE DIMENSIONS: Substrate: 89.4 mils x 76.0 mils x 14 mils ±1 mil Radiation Hardened Silicon Gate, Dielectric Isolation INTERFACE MATERIALS: Backside Finish: Glassivation: Silicon Type: SiO2 Thickness: 11kÅ ±2kÅ ASSEMBLY RELATED INFORMATION: Top Metallization: Substrate Potential: Type: AlSi Thickness: 8kÅ ±1kÅ Unbiased (DI) Metallization Mask Layout (21) B0 (22) VCC (1) VDD (2) A0 (3) A1 HS-3374RH (20) B1 A2 (4) (19) B2 A3 (5) (18) B3 A4 (6) (17) B4 A5 (7) (16) B5 A6 (8) (15) B6 A7 (9) 3 DISABLE (13) GND (11) ENABLE (10) (14) B7