MC100LVEL40 D

MC100LVEL40
3.3/5VECL Differential
Phase−Frequency Detector
Description
The MC100LVEL40 is a three state phase frequency−detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V power supply.
When the reference (R) and the feedback (FB) inputs are unequal in
frequency and/or phase the differential up (U) and down (D) outputs
will provide pulse streams which when subtracted and integrated
provide an error voltage for control of a VCO.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
For application information, refer to AND8040/D, “Phase Lock
Loop Operation.”
The 100 Series Contains Temperature Compensation
Features
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MARKING
DIAGRAM
20
20
100LVEL40
AWLYYWWG
1
SO−20
DW SUFFIX
CASE 751D
A
WL
YY
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
• 250 MHz Typical Bandwidth
• PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
ORDERING INFORMATION
• NECL Mode Operating Range:
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
VCC = 0 V with VEE = −3.0 V to −5.5 V
• Internal Input Pulldown Resistor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC100LVEL40/D
MC100LVEL40
NC VCCO
U
U
VEE
D
D
20
18
17
16
15
14
19
VCCO NC
NC
12
11
13
1
2
3
4
5
6
7
8
9
10
NC
NC
R
R
VBB
FB
FB
VCC
NC
NC
Table 1. PIN DESCRIPTION
PIN
FUNCTION
U, U
D, D
FB, FB
R, R
VBB
VCC, VCCO
VEE
NC
ECL Up Differential Outputs
ECL Down Differential Outputs
ECL Feedback Differential Inputs
ECL Reference Differential Inputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Pinout (Top View)
R
S
R
U
Q
U
R
VBB
VEE
D
D
R
FB
S
FB
Q
Figure 2. Logic Diagram
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Moisture Sensitivity (Note 1)
SOIC−20
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 3
UL 94 V−0 @ 0.125 in
356 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100LVEL40
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
306
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20
30 to 35
°C/W
Tsol
Wave Solder
265
265
°C
VI v VCC
VI w VEE
Pb
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
38
45
38
47
38
47
mA
VOH
Output HIGH Voltage (Note 3)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 3)
1470
1605
1745
1490
1595
1380
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 7)
Vpp < 500 mV
Vpp y 500 mV
1.3
1.5
3.3
3.3
1.2
1.4
3.3
3.3
1.2
1.4
3.3
3.3
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
Others
R, FB
0.5
−300
150
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V.
3. Outputs are terminated through a 50 W resistor to VCC − 2 V.
4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and
1 V.
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MC100LVEL40
Table 5. LVNECL DC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V (Note 5)
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
38
45
Min
85°C
Typ
Max
38
47
Min
Typ
Max
Unit
38
47
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 6)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage
(Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common
Mode Range (Note 7)
Vpp < 500 mV
Vpp y 500 mV
−2.0
−1.8
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
Others
R, FB
0.5
−300
150
0.5
−300
0.5
−300
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V.
6. All loading with 50 W resistor to VCC − 2 V.
7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and
1 V.
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0 V; VEE = −3.3 V (Note 8)
−40°C
Symbol
Characteristic
Fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay
VPP
Input Swing (Differential Configuration)
(Note 9)
tJITTER
Cycle−to−Cycle Jitter
tr, tf
Output Rise/Fall Times
R to U, FB to D
Min
Typ
25°C
Max
Min
TBD
Typ
85°C
Max
Min
TBD
Typ
Max
TBD
Unit
GHz
430
1200
630
1400
450
1250
650
1450
480
1370
680
1590
ps
150
1000
150
1000
150
1000
mV
TBD
175
TBD
475
175
TBD
475
175
ps
475
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. VEE can vary ± 0.3 V.
9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈ 40.
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4
MC100LVEL40
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10LVEL40DW
SOIC−20
38 Units / Rail
MC10LVEL40DWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC10LVEL40DWR2
SOIC−20
1000 / Tape & Reel
MC10LVEL40DWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVEL40
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC100LVEL40/D