ENA0693 D

Ordering number : ENA0693
LV5609V
Bi-CMOS LSI
Vertical Clock Driver for CCD
http://onsemi.com
Overview
The LV5609V is vertical clock driver for CCD.
Functions
• Ternary output ×2ch
• Binary output ×2ch
• SHT output ×1ch
• Output ON resistance : 30Ω typ
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = VM = 0V
Parameter
Symbol
Maximum supply voltage
Allowable power dissipation
Conditions
Ratings
Unit
VDD max
6
V
VH max
20
V
VL max
-10
V
VH-VL max
24
V
0.67
W
Pd max
with specified substrate *
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-40 to +125
°C
* : Specified substrate :
114.3×76.1×1.6mm3,
glass epoxy board
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ratings at Ta = 25°C, VSS = VM = 0V
Parameter
Symbol
Ratings
Conditions
min
Supply voltage
VDD
typ
2.0
VH
VL
-8.5
VH-VL
Unit
max
3.3
5.5
15
17
V
V
-7.5
-4
V
23.5
V
CMOS input High voltage
VINH
0.8VDD
VDD
V
CMOS input Low voltage
VINL
-0.1
0.4
V
Semiconductor Components Industries, LLC, 2013
August, 2013
32207 MS PC 20061109-S00003 No.A0693-1/8
LV5609V
Electrical Characteristics at Ta = 25°C, VDD = 3.3V, VSS = 0V, VH = 15V, VL = -7.5V, VM = 0V,
Unless otherwise specified
Parameter
Symbol
Ratings
Conditions
min
Static current drain
Unit
max
1
μA
IH
VH pin
10
μA
IL
VL pin
1
μA
VDD pin See *1 and *2.
1
mA
IDD
Dynamic current drain
typ
IDD
VDD pin
IH
VH pin See *1 and *2.
2.4
4.5
mA
IL
VL pin See *1 and *2.
3
5
mA
RL
IO = +10mA
20
30
Ω
RM
IO = ±10mA
30
45
Ω
RH
IO = -10mA
30
40
Ω
RSHT
IO = -10mA
30
40
Ω
TPLM
No load
200
ns
TPMH
No load
200
ns
Output ON resistance
Propagation delay time
TPLH
No load
200
ns
TPML
No load
200
ns
TPHM
No load
200
ns
TPHL
No load
200
ns
TTLM
VL → VM V1, V3 See *1.
800
ns
VL → VM V2, V4 See *1.
800
ns
TTMH
VM → VL V1, V3 See *1.
800
ns
TTLH
VL → VH SHT See *1.
200
ns
TTML
VM → VL V1, V3 See *1.
800
ns
VM → VL V2, V4 See *1.
800
ns
TTHM
VH → VM V1, V3 See *1.
800
ns
TTHL
VH → VL SHT See *1.
200
ns
Rise time
Fall time
*1 : Refer to the CCD equivalent load shown below.
*2 : Refer to the timing waveform on Page 7.
2000pF
2000pF
1000pF
V1
(Ternary)
V4
(Ternary)
3000pF
SHT
3000pF
1600pF
1000pF
V2
(Binary)
V3
(Binary)
2000pF
2000pF
No.A0693-2/8
LV5609V
Package Dimensions
unit : mm (typ)
3179C
Pd max – Ta
6.5
0.5
6.4
11
4.4
20
1
10
0.65
0.15
0.22
1.5max
(1.3)
(0.33)
Allowable power dissipation, Pd max – W
1.0
Specified circuit board : 114.3×76.1×1.6mm3
glass epoxy board
0.8
0.67
0.6
0.4
0.30
0.2
0
– 20
0
20
40
60
80
100
0.1
Ambient temperature, Ta – °C
SANYO : SSOP20(225mil)
No.A0693-3/8
LV5609V
Pin Assignment
SSOP20
V3
1
20 V4
V2
2
19 SHT
V1
3
18 NC
VM
4
17 VL
NC
5
16 VSS
VH
6
15 VDD
XV1
7
14 XSHT
XSG1
8
13 NC
XV2
9
12 XV4
LV5609V
XV3 10
11 XSG3
Top view
Pin Function
Pin No.
Name
1
V3
Level shift output (ternary VH, VM, VL)
Mode
2
V2
Level shift output (binary VM, VL)
3
V1
Level shift output (ternary VH, VM, VL)
4
VM
GND for output
5
NC
6
VH
Hi power supply (15V system) for output
7
XV1
V1 transfer pulse input
8
XSG1
9
XV2
10
XV3
11
XSG3
V1 read pulse input
V2 transfer pulse input
V3 transfer pulse input
V3 read pulse input
12
XV4
13
NC1
V4 transfer pulse input
14
XSHT
15
VDD
Power supply (3.3V system) for input buffer
16
VSS
GND for input buffer
17
VL
SHT pulse input
LO power supply (-7.5V system) for output
18
NC
19
SHT
Level shift output (binary VH, VL)
20
V4
Level shift output (ternary VM, VL)
No.A0693-4/8
LV5609V
Block Diagram
VDD
Level Shift
& Output Buffer
20
Input Buffer
0.1μF
9
VH
1μF
XV1 12
30
6 V1
30
5 V2
XSG1 13
XV2 14
7
VM
XV3 15
30
4 V3
XV4 17
30
3 V4
XSHT 18
30
2 SHT
XSG3 16
VSS
21
1
VL
1μF
Logical Function Table
Input
Output
XV1
XSG1
XV2
XV3
XSG3
XV4
L
L
X
V1
V2
V3
V4
X
VH
X
XSHT
SHT
X
L
H
X
X
VM
X
X
H
L
X
X
VL
X
X
H
H
X
X
VL
X
X
X
X
L
X
X
VM
X
X
X
H
X
X
VL
X
X
X
X
L
X
X
VH
X
X
X
H
X
X
VL
No.A0693-5/8
LV5609V
Timing Chart
VDD
50%
XV1 to XV4
XSG1
XSG3
50%
VSS
VDD
TTHM
VSS
TPMH
TTMH
VH
V1
V3
TPHM
50%
TTLM
TTML
90%
TPLM
TPML
VM
90%
10%
10%
VL
TTLM
TPLM
V2
V4
TTML
TPML
VM
90%
10%
VL
VDD
XSHT
50%
50%
VSS
TTLH
TTHL
TPLH
VH
SHT
VL
TPHL
90%
10%
No.A0693-6/8
LV5609V
CCD Equivalent Load Measurement Timing Waveform
63.5μs
127μs
2μs
XV1
XV2
XV3
XV4
XSG1
2.5μs
XSG3
63.5μs
2.5μs
2μs
16.7ms
XSHT
Enlarged View of overlapped portion
XV1
XV2
XV3
XV4
0μs 0.7μs 1.4μs 2.1μs 2.8μs 3.5μs 4.2μs 4.9μs
No.A0693-7/8
LV5609V
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PS No.A0693-8/8
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