MC100LVE310 3.3V ECL 2:8 Differential Fanout Buffer Description The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 W, even if only one side is being used. In most applications all eight differential pairs will be used and therefore terminated. In the case where fewer than eight pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10 - 20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVE310 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE310's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC - 2.0 V will need to be provided. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single‐ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. http://onsemi.com PLCC-28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MC100LVE310G AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Features • 200 ps Part-to-Part Skew • 50 ps Output-to-Output Skew • PECL Mode Operating Range: • Q Output will Default LOW with All Inputs Open or at VEE • The 100 Series Contains Temperature Compensation • Pb-Free Packages are Available* VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2007 October, 2007 - Rev. 5 1 Publication Order Number: MC100LVE310/D MC100LVE310 Q0 Q0 25 24 Q1 VCCO Q1 23 22 21 Q2 Q2 20 19 Q0 Q0 VEE 26 18 Q3 CLK_SEL 27 17 Q3 16 Q4 Q1 Q1 CLKa 28 Q2 Q2 CLKa VCC CLKa Pinout: 28-Lead PLCC (Top View) 1 15 2 14 VCCO CLKa Q4 CLKb Q3 Q3 Q4 CLKb VBB 3 13 Q5 CLKb 4 12 Q5 5 6 7 8 9 10 Q4 Q5 CLK_SEL Q5 11 Q6 CLKb NC Q7 VCCO Q7 Q6 Q6 Q6 Q7 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Q7 Figure 1. Logic Diagram and Pinout Assignment VBB Figure 2. Logic Symbol Table 1. PIN DESCRIPTION FUNCTION PIN CLKa, CLKa; ,CLKb CLKb Q0:7, Q0:7 CLK_SEL VBB VCC, VCCO VEE NC Table 2. TRUTH TABLE ECL Differential Input Clocks ECL Differential Outputs ECL Input Clock Select Reference Voltage Output Positive Supply Negative Supply No Connect Input Clock CLK_SEL CLKa Selected CLKb Selected L H Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor YES Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PLCC-28 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V Pb Pkg Pb-Free Pkg Level 1 Level 3 UL 94 V-0 @ 0.125 in 212 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVE310 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V -8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 -6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range -40 to +85 °C Tstg Storage Temperature Range -65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm PLCC-28 PLCC-28 63.5 43.5 °C/W °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board PLCC-28 22 to 26 ± 5% °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb-Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V, VEE = 0 V (Note 2) -40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 55 60 55 60 65 70 mA VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.8 2.9 1.8 2.9 1.8 2.9 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC - 2 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). http://onsemi.com 3 MC100LVE310 Table 6. LVNECL DC CHARACTERISTICS VCC = 5.0 V, VEE = -3.3 V (Note 5) -40°C Symbol Characteristic Min 25°C Typ Max 55 60 Min 85°C Typ Max 55 60 Min Typ Max Unit 65 70 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) -1085 -1005 -880 -102 5 -955 -880 -1025 -955 -880 mV VOL Output LOW Voltage (Note 6) -1830 -1695 -1555 -181 0 -170 5 -1620 -1810 -1705 -1620 mV VIH Input HIGH Voltage (Single-Ended) -1165 -880 -1165 -880 -1165 -880 mV VIL Input LOW Voltage (Single-Ended) -1810 -1475 -181 0 -1475 -1810 -1475 mV VBB Output Voltage Reference -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) -1.5 -0.4 -1.5 -0.4 -1.5 -0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 0.5 0.5 mA 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). Table 7. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 8) -40°C Symbol Characteristic Min Typ 0.5 1.0 25°C Max Min Typ 0.5 1.0 85°C Max Min Typ 0.5 1.0 Max Unit fmax Maximum Toggle Frequency @ Vout >500 mVpp GHz tPLH tPHL Propagation Delay to Output IN (Differential Configuration) (Note 9) IN (Single-Ended) (Note 10) tskew Within-Device Skew (Note 11) Part-to-Part Skew (Differential Configuration) tJITTER Additive CLOCK Jitter (RMS) <0.5 GHz 2.0 ps VPP Input Swing (Note12) 500 1000 500 1000 500 1000 mV tr/tf Output Rise/Fall Time (20%-80%) 200 600 200 600 200 600 ps ps 525 500 725 750 550 550 750 800 75 250 1.5 575 600 775 850 50 200 2.0 1.5 50 200 2.0 1.5 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. VEE can vary ± 0.3 V. 9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. The single‐ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output. http://onsemi.com 4 MC100LVE310 Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC100LVE310FN PLCC-28 37 Units / Rail MC100LVE310FNG PLCC-28 (Pb-Free) 37 Units / Rail MC100LVE310FNR2 PLCC-28 500 / Tape & Reel MC100LVE310FNR2G PLCC-28 (Pb-Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVE310 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E 0.007 (0.180) B M T L-M N S T L-M S S Y BRK -N- 0.007 (0.180) U M N S D Z -M- -L- W 28 D X 0.010 (0.250) G1 T L-M S N S S V 1 VIEW D-D A 0.007 (0.180) R 0.007 (0.180) M T L-M S N S C M T L-M S N 0.007 (0.180) H Z M T L-M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) -T- T L-M S N S VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10_ 0.410 0.430 0.040 --- http://onsemi.com 6 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10_ 10.42 10.92 1.02 --- 0.007 (0.180) M T L-M S N S MC100LVE310 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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