NB3M8304C 3.3 V 200 MHz 1:4 LVCMOS/LVTTL Low Skew Fanout Buffer Description The NB3M8304C is 1:4 fanout buffer with LVCMOS/LVTTL input and output. The device supports the core supply voltage of 3.3 V (VDD pin) and output supply voltage of 2.5 V or 3.3 V (VDDO pin). The VDDO pin powers the four single ended LVCMOS/LVTTL outputs. The NB3M8304C is Form, Fit and Function (pin to pin) compatible to ICS8304 and ICS8304I. The NB3M8304C is qualified for industrial operating temperature range. Features • • • • • • • • Input Clock Frequency up to 200 MHz Low Output to Output Skew: 45 ps max Low Part to Part Skew: 500 ps max Low Additive RMS Phase Jitter Input Clock Accepts LVCMOS/ LVTTL Levels Operating Voltage: ♦ Core Supply: VDD = 3.3 V ±5% ♦ Output Supply: VDDO = 3.3 V ±5% or 2.5 V ±5% Operating Temperature Range: ♦ Industrial: −40°C to +85°C These Devices are Pb−Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 A L Y W G 8304C ALYWG G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2014 December, 2014 − Rev. 3 1 Publication Order Number: NB3M8304C/D NB3M8304C Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Number Name Type Description 1 VDDO Output Power 2 VDD Input and Core Power Input and Core Supply pin. 3 CLK LVCMOS/LVTTL Input Clock Input. Internally pull−down. Clock output Supply pin. 4 GND Ground 5, 6, 7, 8 Q[0:3] LVCMOS/LVTTL Output Supply Ground. LVCMOS/LVTTL Clock output. Table 2. MAXIMUM RATINGS Symbol Parameter Condition Min Max Unit V VDD, VDDO Power Supply − 4.6 VI Input Voltage −0.5 VDD + 0.5 V Tstg Storage Temperature −65 +150 °C θJA Thermal Resistance (Junction−to−Ambient) SOIC−8 θJC Thermal Resistance (Junction to Case) (Note 1) Tsol Wave Solder MSL Moisture Sensitivity SOIC−8 °C/W 0 lfpm 500 lfpm 80 55 3 sec Indefinite Time Out of Drypack (Note 2) 12−17 °C/W 265 °C Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) 2. For additional information, see Application Note AND8003/D. www.onsemi.com 2 NB3M8304C Table 3. DC OPERATING CHARACTERISTICS (VDD = 3.3 V ±5%; TA = −40°C to +85°C) Symbol Parameter Condition Min Typ Max Unit RIN Input Pull−down Resistor (CLK Pin) 51 kW CIN Input Capacitance 4 pF ROUT Output Impedance (Note 3) CPD Power Dissipation Capacitance (per output) VDD Core Supply Voltage 5 7 VDD = VDDO = 3.465 V 15 3.135 IIH Input High Current VIN = VDD = 3.465 V IIL Input Low Current VDD 3.465 V, VIN = 0.0 V 12 3.3 W pF 3.465 V 150 mA mA −0.5 3. Outputs terminated with 50W to VDDO/2. See Figure 4 for supply considerations. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. DC OPERATING CHARACTERISTICS (TA = −40°C to +85°C) Symbol Parameter Condition Min Max Unit 2.375 2.625 V VDD = 3.3 V +5%, VDDO = 2.5 V +5% VDDO Output Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IOH = −100 mA 2.2 IOH = −16 mA 2.1 50 W to VDDO/2 2.1 V IOL = 16 mA 0.25 IOL = 100 mA 0.2 50 W to VDDO/2 0.5 V VDD = VDDO = 3.3 V +5% VDDO Output Supply Voltage VOH Output HIGH Voltage VOL 3.135 Output LOW Voltage IOH = −16 mA 2.9 IOH = −100 mA 3 50 W to VDDO/2 2.6 3.465 V V IOL = 16 mA 0.25 IOL = 100 mA 0.15 50 W to VDDO/2 0.5 V Table 5. DC OPERATING CHARACTERISTICS (TA = −40°C to +85°C; VDD = VDDO = 3.3 V ±5%; VDD = 3.3 V ±5%, VDDO = 2.5 V ±5%) Max Unit IDD Quiescent Power Supply Current No Load 15 mA IDDO Quiescent Power Supply Current No Load 8 mA VIH Input HIGH Voltage 2 VDD + 0.3 V VIL Input LOW Voltage −0.3 1.3 V Symbol Parameter Condition www.onsemi.com 3 Min NB3M8304C Table 6. AC CHARACTERISTICS (Note 4) Symbol Parameter Condition Min Typ Max Unit 200 MHz 3.3 ns TA = −405C to +855C; VDD = 3.3 V +5%, VDDO = 3.3 V +5% FIN Input Frequency tPLH Propagation Delay (Note 5) tSKEW Fin = 200 MHz 1.9 Output to Output Skew(Note 6) 25 45 ps Part to Part Skew (Note 6) 250 800 ps tSKEWDC Output Duty Cycle (see Figure 3) Fin = 200 MHz 40 60 % tr/tf Output rise and fall times (Note 7) 30% to 70%, RS = 33 W, CL = 10 pF 250 500 ps 200 MHz 3.7 ns TA = −405C to +855C; VDD = 3.3 V +5%, VDDO = 2.5 V +5% FIN Input Frequency tPLH Propagation Delay (Note 5) tSKEW Fin = 200 MHz 2.2 Output to Output Skew(Note 6) 25 45 ps Part to Part Skew (Note 6) 250 500 ps tSKEWDC Output Duty Cycle (see Figure 3) Fin = 200 MHz 40 60 % tr/tf Output rise and fall times (Note 7) 30% to 70%, RS = 33 W, CL = 10 pF 200 500 ps 4. Clock input with 50% duty cycle. Outputs terminated with 50 W to VDDO/2. See Figures 3 and 4. 5. Measured from VDD/2 of the input to VDDO/2 of the output. 6. Similar input conditions and the same supply voltages. Measured at VDDO /2. See Figures 3 and 4. 7. RS is Series Resistance and CL is Load Capacitance at the clock outputs. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. www.onsemi.com 4 NB3M8304C 70% 70% 30% 30% Figure 3. AC Reference Measurement VDD VDDO ZO = 50 W NB3M8304C Qx D Receiver / Scope 50 W DUT GND Spec Condition: TEST SETUP VDD: TEST SETUP VDDO: TEST SETUP DUT GND: VDD = VDDO = 3.3 V ±5% 1.65 V ±5% 1.65 V ±5% −1.65 V ±5% VDD = 3.3 V ±5%; VDDO = 2.5 V ±5% 2.05 V ±5% 1.25 V ±5% −1.25 V ±5% Figure 4. Output Driver Typical Device Evaluation and Termination Setup ORDERING INFORMATION Package Shipping† NB3M8304CDG SOIC−8 (Pb−Free) 98 Units / Rail NB3M8304CDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 NB3M8304C PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S J SOLDERING FOOTPRINT* MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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