NCS37012 Self Test Ground Fault Circuit Interrupter (GFCI) Description The NCS37012 is a fully UL943 compliant signal processor for GFCI applications with self test. The device integrates a flexible power supply (including both shunt and LDO regulators), differential fault, and grounded-neutral detection circuits. Proprietary impedance measurement and signal processing techniques are used to minimize the number of external components and improve performance. The device also includes a specialized DSP controller that offers best in class immunity to nuisance loads without the need for external analog filters. Self test is monitored every 17 minutes through an external current path and internally generated grounded neutral fault. www.onsemi.com 20 1 QFN16 MN SUFFIX CASE 485G TSSOP−20 DA SUFFIX CASE 948E 1 MARKING DIAGRAMS Features • 6.0 V − 12 V Operation (120 − 480 V AC mains with the appropriate • • • • • XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS Supply SCRdrv • • 3701 2DBG ALYWG G 37012 MNG ALYW G 1 MLD CTresGN CTbias CTstim GND (Top View) CTresD IDF • • • • series impedance) −40 to 85°C Very Low Power Consumption: <15 mW @ 5 V 16 Pin QFN Package or 20 Pin TSSOP Package Single Current Transformer (CT) Detection of both Differential and Grounded−Neutral Faults Full Self Test and Trip Indicator Monitoring Self Syncing Internal Oscillator Adjusts to AC Mains Frequency to Guarantee Full Resolution on 50 and 60 Hz Distribution Systems Optimized Solenoid Deployment (coil is not energized near the AC mains zero crossings) Randomized Testing Sequence to Minimize Noise and Potential Interactions on the AC Mains >5 mA SCR Driver for use with High Igt SCR’s for Improved Noise Immunity Superior Immunity to Nuisance Loads/Noise (up to 10 A) without Loss of Detection Capability or CT Saturation These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Load Panel GFCI Breakers • GFCI Receptacles • In−line GFCI Circuits (power cords) ORDERING INFORMATION Device Package Shipping† NCS37012MNTWG QFN16 (Pb−Free) 3000 / Tape & Reel NCS37012DBRG TSSOP20 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 0 1 Publication Order Number: NCS37012/D Supply NCS37012 − HV Bandgap Brown Out + AVDD/ DVDD − + POR CTresGN Grounded Neutral Detection IDF Digital Filter Low Pass Filter Differential Current Detection SCRdrv Mixer Self Trimmed RC Osc Control Logic CTresD GROUND FAULT PTT GN DETECTION TE Waveform Generator Offset Correction Driver LED(0) Ground GN Randomizer GFtest SELF TEST tripEN PZ Vbias CTstim CTbias LED(1) Figure 1. Simplified Block Diagram www.onsemi.com 2 Mains Level Detector / Lockout Detector MLD TI NCS37012 Table 1. PIN FUNCTION DESCRIPTION − QFN Pin # Name Pad Description 0 Ground 1 MLD 2 CTresGN 3 CTbias Direct connection to the CT 4 CTstim Direct connection to the CT 5 CTresD Determines IV converter gain for detection threshold / matched to CT turns ratio (Differential Current) 6 IDF 7 GFtest Output to induce external differential current 8 TripEN (H) Trip / (L) No Trip on Self Test Failure QFN center slug Mains Level Detect (Zero Cross) Determines IV converter gain for detection threshold / matched to CT turns ratio (Ground-Neutral) Front end noise filter capacitor 9 PZ Piezo output driver 10 NC Tie to Ground or leave floating 11 PTT Push to test input 12 TI Tip indicator input 13 LED[0] LED[0] output driver 14 LED[1] LED[1] output driver 15 SCRdrv Used to trigger the solenoid at a fault detection 16 Supply Power supply Table 2. PIN FUNCTION DESCRIPTION − TSSOP Pin # Name Pad Description 1 CTstim Differential and ground to neutral stimulus point for the current transformer 2 Ground Ground connection for IC 3 CTresD Determines IV converter gain for detection threshold / matched to CT turns ratio (Differential Current) 4 IDF 5 GFtest Determines corner frequency of the differential current path filter Output to induce external differential current 6 TripEN (H) Trip / (L) No Trip on Self Test Failure 7 PZ Piezo output driver 8 NC Tie to Ground or leave floating 9 PTT Push to test input 10 TI Tip indicator input 11 Ground Ground connection for IC 12 LED[0] LED[0] output driver 13 LED[1] LED[1] output driver 14 SCRdrv Used to trigger the solenoid at a fault detection 15 DVDD Internal digital 5 V regulated supply 16 AVDD Internal analog 5 V regulated supply 17 Supply 12 V shunt regulated power supply 18 MLD 19 CTresGN 20 CTbias Mains Level Detect (Zero Cross) and AM slope detect (for oscillator sync/trim and AM init) Determines IV converter gain for detection threshold / matched to CT turns ratio (Ground-Neutral) External 2 V bias for the current transformer www.onsemi.com 3 NCS37012 Table 3. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage Range Vs 6.0 to 12 V V Input Voltage Range (Note 1) Vin −0.3 to 6.0 V Output Voltage Range Vout −0.3 to 6.0 V or (Vin + 0.3), whichever is lower V TJ(max) 140 °C TSTG −65 to 150 °C Maximum Junction Temperature Storage Temperature Range ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV ESD Capability, Machine Model (Note 2) ESDMM 200 V TSLD 260 °C Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D Table 4. THERMAL CHARACTERISTICS Rating Symbol Value Thermal Characteristics, QFN16, 3x3.3 mm (Note 4) Thermal Resistance, Junction−to−Air (Note 5) Thermal Reference, Junction−to−Lead2 (Note 5) RqJA RYJL TBD TBD Thermal Characteristics, TSSOP−20 (Note 4) Thermal Resistance, Junction−to−Air (Note 5) RqJA TBD Unit °C/W °C/W 4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Table 5. OPERATING RANGES (Note 6) Parameter Conditions Operating Temperature Min −40 IDD in typical power state Stimulus Generator Frequency Typ Max Units 85 C 3.4 kHz 8.0 mA 5.5 V 5.0 mA 2.0 Tri−tone 3.1 SCR Trigger Current mA SCR Trigger output voltage With 5 V supply 4.5 Fault Current Sensitivity Programmable with CTresD 4.6 Ground Fault Response Time 5 − 20 mA 150 ms Ground Fault Response Time 20 − 40 mA 75 ms Ground Fault Response Time >40 mA 25 ms Saturation Fault Response Time >300 mA 1.4 ms CT Turns Ratio Ground – Neutral Detection Threshold Total series impedance (Rn and Rg) Internal Oscillator Frequency CT Stimulus Current 4.8 200 300 3.0 6.0 2.0 Internally limited CT Driver Closed Loop BW W MHz 1.0 mA 500 kHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 4 NCS37012 LINE P HA SE NEUTRA L APPLICATIONS INFORMATION LOA D_PHAS E ResMAIN Q1 CapSUP CapSCR LED[0] Supply SCRdrv ResMLD LED[1] ResLED ResTI CapBias MLD TI CTresGN PTT CTbias TE CTstim PZ ResGN CapGN ResD Q2 LOAD Figure 2. Typical Application Schematic www.onsemi.com 5 TripEN GFtest CapIDF PHAS E NE UTRAL ResGFTST IDF CTresD CapCT NCS37012 RECOMMENDED EXTERNAL COMPONENTS: Component Type Instance Value Note SCR Q1 - ON-MCR08 Diode Dx - ON-1N4007 NPN Q2 - MMBT6517LT1G LED pins drive opposite polarities LED Lx - Capacitor CapSUP 3.3 mF Capacitor CapGN 1-10 nF Matched to current transformer Capacitor CapIDF 220 nF Sets the differential corner frequency at 1 kHz Capacitor CapBias 10 nF Filtering component for CTbias voltage Capacitor CapCT 2.2 - 10 nF Filtering and resonant capacitor for CT Capacitor CapSCR - Resistor ResD 40 - 80k Matched to current transformer Resistor ResGN 100 - 400k Matched to current transformer Resistor ResMLD 400 - 800k Limiting resistor for the Mains Level Detector (MLD) input Resistor ResTI 400 - 800k Limiting resistor for the Trip Indicator (TI) input Resistor ResMAIN 10k For a full bridge rectifier Resistor ResGFTST 15k Sets the external differential test current (8 mA) Resistor ResLED 1-5k Sets the brightness of the LEDs TVS T1 - For a full bridge rectifier Filtering component 250-400V LED AND SPEAKER FUNCTIONS Device Function Normal Abnormal Device State LED[0] LED[1] Speaker No Power / Line Load Reversed OFF LOW OFF Power Up HIGH for 500 ms LOW OFF Reset (Entered through PTT) HIGH for 500 ms then LOW HIGH Tripped LOW HIGH OFF Self-Test Fails (Tripped) (Blink) HIGH LOW OFF Self-Test Fails (Reset) (Blink) HIGH LOW ON No Trip on Fault (Blink) HIGH LOW ON Filtering ON (250 ms) levels to trip at lower differential currents. CT efficiency at 60 Hz must be considered. . CTresD= 400*#Turns – Subject to CT efficiency at 60 Hz The CTresGN resistor sets the threshold for ground to neutral fault detection. The Rt parameter is the desired ground to neutral resistance trip level. Higher CTresGN values will cause the part to trip at higher ground to neutral impedances. CtresGN = #Turns^2 x Rt/2 – Subject to CT efficiency from 3 kHz to 4 kHz The analog signal capture portion of the IC includes a single pole filter that can be set externally with Cidf. This provides an additional layer of protection against false tripping under steady state noise conditions. High frequency steady state noise is common with pumps, motors or other cyclic noise generators. Cidf = 220 nF = 1 kHz low pass. For additional filtering suggestions please contact ON Semiconductor. Setting Trip Sensitivity The CTresD resistor sets the threshold for the differential current fault levels. Increasing CTresD causes the fault www.onsemi.com 6 NCS37012 Setting Grounded − Neutral Response Time Differential ground fault test – tests the CT and the internal differential detection signal path by asserting the GFtest output high for 2 half cycles. The test will pass if a 6-8 mA differential current is enabled during these two half waves. Greater than 20 mA current during this test will cause a fault to be detected. Ground neutral fault test – tests the internal ground neutral stimulus and detection paths by enabling an internal 50k resistor between the CTstim and CTbias pins. If the resistor and capacitor on CTresGN are connected this will pass the GN self test. Cgn is used to define the response time of the grounded−neutral detection circuit. The analog portion converts the impedance into a DC voltage and a high frequency (aliased) component. The capacitor is used to remove the high frequency component leaving just the DC representation of the impedance. CTcapGN= 1.8E-4/CTresGN Self Test Automatic self test will occur every 17 minutes. If a failure is observed it will be retested every second until it passes. If it fails 8 successive tests then the GFCI will indicate that it has failed self test. See the LED and speaker functions table to see the different self test indicators. If TripEN is asserted high the GFCI unit will trip. PTT When the PTT input pin is de-asserted for greater than 80 ms a self test will be performed. If this test is successful the SCR will be fired which will trip the GFCI unit. If the test is unsuccessful the LED[0] pin will flash indicating a failure. www.onsemi.com 7 NCS37012 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B −U− L PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N DIM A B C D F G H J J1 K K1 L M F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NCS37012 PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D A B ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION L L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ 0.10 C 2X EXPOSED Cu 0.10 C 2X TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L (A3) MOLD CMPD A1 DETAIL B A 0.05 C ÉÉ ÇÇ ÇÇ A3 ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C 16X L MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 SEATING PLANE 0.10 C A B DETAIL A DIM A A1 A3 b D D2 E E2 e K L L1 RECOMMENDED SOLDERING FOOTPRINT* D2 16X 8 0.58 PACKAGE OUTLINE 4 9 E2 16X 1 K 2X 1 2X 1.84 3.30 16 e e/2 BOTTOM VIEW 16X b 16X 0.10 C A B 0.05 C 0.30 NOTE 3 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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