A8499 Datasheet

A8499
High Voltage Step-Down Regulator
Features and Benefits
Description
▪
▪
▪
▪
▪
The A8499 is a step down regulator that will handle a wide
input operating voltage range.
The A8499 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ).
Applications include:
▪ Printer power supplies
▪ Consumer equipment power supplies
8 to 50 V input range
Integrated DMOS switch
Adjustable fixed off-time
Highly efficient
Adjustable 1.2 to 24 V output
Package: 8-Lead SOIC with exposed
thermal pad (suffix LJ)
Approximate Scale 1:1
Typical Application
+42 V
Efficiency vs. Output Current
CBOOT
0.01 μF
C3
100 μF
50 V
VIN
ENB
LX
L1
47 μH
A8499
TSET
VOUT
3.3 V / 1.2 A
VBIAS
R1
17.8 kΩ
RTSET
121 kΩ
GND
ESR
FB
D1
R2
10.2 kΩ
COUT
220 μF
10 V
Efficiency %
BOOT
C3
0.22 μF
90.0
88.0
86.0
84.0
82.0
80.0
78.0
76.0
74.0
72.0
70.0
VOUT (V)
3.3
5
0
200
400
600
800
1000
1200
1400
IOUT (mA)
Circuit for 42 V step down to 3.3 V at 1.2 A. Efficiency data from circuit shown in left panel.Data is for reference only.
A8499-DS, Rev. 5
A8499
High Voltage Step-Down Regulator
Functional Block Diagram
Boot Charge
BOOT
+
VIN
VIN
VOUT
–
LX
L1
ESR
D1
COUT
µC
Switch PWM
Switch
Disable
ENB
Clamp
+
TSET
–
I_Demand
FB
–
+
I_Peak
COMP
Bias Supply
GND
VBIAS is connected to VOUT
when VOUT target is between
3.3 and 5 V
VBIAS
UVLO
Soft Start
Ramp Generation
TSD
Absolute Maximum Ratings
Supply Voltage, VIN ......................................................................... 50 V
VBIAS Input Voltage, VBIAS .................................................–0.3 to 7 V
Switch Voltage, VLX......................................................................... –1 V
ENB Input Voltage, VENB ......................................................–0.3 to 7 V
Junction Temperature, TJ(max) ....................................................... 150°C
Storage Temperature, TS ............................................... –55°C to 150°C
1.2 V
Package Thermal Characteristics*
Package
RθJA
(°C/W)
PCB
LJ
35
4-layer
* Additional information is available on the Allegro Web site
Operating Ambient Temperature, TA............................... –20°C to 85°C
Ordering Information
Use the following complete part numbers when ordering:
Part Numbera
Packingb
Description
A8499SLJTR-T
13 in. reel, 3000 pieces/reel
LJ package, SOIC surface mount with
exposed thermal pad
aLeadframe
plating 100% matte tin.
for additional packing options.
bContact Allegro
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A8499
High Voltage Step-Down Regulator
ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 50 V (unless noted otherwise)
Characteristics
VIN Quiescent Current
VBIAS Input Current
Buck Switch On Resistance
Symbol
IVIN(Q)
IBIAS
RDS(on)
Fixed Off-Time Proportion
Feedback Voltage
Test Conditions
Min.
Typ.
Max.
Units
VENB = LOW, IOUT = 0 mA, VIN = 42 V
VBIAS = VOUT (see note3)
–
0.90
1.35
mA
VENB = LOW, IOUT = 0 mA, VIN = 42 V
VBIAS < 3 V
–
4.4
6.35
mA
VENB = HIGH
–
–
100
μA
VBIAS = VOUT
–
3.5
5
mA
TA = 25°C, IOUT = 2 A
–
700
800
mΩ
TA = 125°C, IOUT = 2 A
–
–
1.6
Ω
–15
–
15
%
1.176
1.200
1.224
V
–3
–
3
%
–400
–100
100
nA
Based on calculated value
VFB
Output Voltage Regulation
IOUT = 0 mA to 2 A
Feedback Input Bias Current
IFB
Soft Start Time
tss
Buck Switch Current Limit
ICL
ENB Open Circuit Voltage
VOC
5
10
15
ms
VFB > 0.5 V
2.2
–
3
A
VFB < 0.5 V
0.5
–
1.2
A
Output disabled
2.0
–
7
V
–
–
1.0
V
–10
–
–1
μA
ENB Input Voltage Threshold
VENB(0)
LOW level input (Logic 0), output enabled
ENB Input Current
IENB(0)
VENB = 0 V
VIN Undervoltage Threshold
VUVLO
VIN rising
–
6.9
7.1
V
VIN Undervoltage Hysteresis
VUVLOHYS
VIN falling
0.7
–
1.1
V
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TJTSD
Temperature increasing
–
165
–
°C
∆TJ
Recovery = TJTSD – ∆TJ
–
15
–
°C
1. Negative current is defined as coming out of (sourcing) the specified device pin.
2. Specifications over the junction temperature range of 0ºC to 125ºC are assured by design and characterization.
3. VBIAS is connected to VOUT node when VOUT target level is between 3.3 and 5 V.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A8499
High Voltage Step-Down Regulator
Functional Description
The value of a resistor between the TSET pin and ground determines the fixed off-time (see graph in the toff section).
VOUT. The output voltage is adjustable from 1.2 to 24 V, based on
the combination of the value of the external resistor divider and
the internal 1.2 V ±3% reference. The voltage can be calculated
with the following formula:
VOUT = VFB × (1 + R1/R2)
(1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 2.2 A minimum.
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF . The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (μs)
is:
R
(2)
tOFF = TSET 10 ,
1.2 10
where RTSET (kΩ) is the value of the resistor. Results are shown
in the following graph:
Resistance vs. Off-Time
17
15
13
11
tOFF (µs)
The A8499 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continuous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
3
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
ON/OFF Control. The ENB pin is externally pulled to ground
7
5
The following conditions are required to trigger a soft start:
VBIAS. To improve overall system efficiency, the regulator output,
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During start up
the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A8499 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal opperation.
9
1
12
36
60
84
108
132
156
180
RTSET (kΩ)
tON . From the volt-second balance of the inductor, the turn-on
time, tON , can be calculated approximately by the equation:
tON =
(VOUT + Vf + IOUT RL) tOFF
VIN – IOUT RDS(on) – IOUT RL – VOUT
(3)
where
Vf is the voltage drop across the external Schottky diode,
RL is the winding resistance of the inductor, and
RDS(on) is the on-resistance of the switching MOSFET.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A8499
High Voltage Step-Down Regulator
to the minimum on-time of the switcher.
The switching frequency is calculated as follows:
1
fSW =
tON + tOFF
(4)
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
Shorted Load. If the voltage on the FB pin falls below 0.5 V, the
regulator will invoke a 0.8 A typical overcurrent limit to handle
shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due
VFB (V)
TSET Multiplier
< 0.25
8 × tOFF
< 0.50
4 × tOFF
< 0.75
2 × tOFF
> 0.75
tOFF
Component Selection
L1. The inductor must be rated to handle the total load current.
The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by:
IRIPPLE = VL(OFF) × tOFF / L
(5)
VL(OFF) = VOUT + Vf + IL(AVG) × RL
(6)
Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. The maximum total current available, ILOAD(MAX) , is:
ILOAD(MAX) = ICL(MIN) × tOFF / L
(5)
Example:
where ICL(MIN) is 2.2 A, from the Electrical Chracteristics table.
Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power
inductor with L = 180 μH and RL = 0.5 Ω Rdc at 55°C, tOFF =
7 μs, and RDS(on) = 1 Ω.
D1. The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during all operating
conditions. The duty cycle for high input voltages can be very
close to 100%.
Substituting into equation 6:
VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V
COUT. The main consideration in selecting an output capacitor
is voltage ripple on the output. For electrolytic output capacitors,
a low-ESR type is recommended.
Substituting into equation 5:
IRIPPLE = 5.8 V × 7 μs / 180 μH = 225 mA
The switching frequency, fSW, can then be estimated by:
fSW = 1 / ( tON + tOFF )
(7)
tON = IRIPPLE × L / VL(ON)
(8)
VL(ON) = VIN – IL(AVG) × RDS(on) – IL(AVG) × RL– VOUT
(9)
Substituting into equation 9:
VL(ON) = 42 V – 0.5 A × 1 Ω – 0.5 A × 0.5 Ω – 5 V = 36 V
Substituting into equation 8:
tON = 225 mA × 180 μH / 36 V = 1.12 μs
Substituting into equation 7:
fSW = 1 / (7 μs +1.12 μs) = 123 kHz
The peak-to-peak output voltage ripple is simply IRIPPLE × ESR.
Note that increasing the inductor value can decrease the ripple
current. The ESR should be in the range from 50 to 500 mΩ.
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on time of the switcher is not violated and
prevent the switcher from cycle skipping. For a given VIN to
VOUT ratio, the RTSET value must be greater than or equal to the
value defined by the curve in the chart RTSET Value versus VIN/
VOUT , on the next page.
Note. The curve represents the minimum RTSET value. When
calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8499
High Voltage Step-Down Regulator
RTSET Value versus VIN /VOUT
13.0
12.5
12.0
Violation of
Minimum On-Time
11.5
11.0
10.5
10.0
9.5
9.0
VIN / VOUT
8.5
8.0
7.5
um
im
in
M
7.0
6.5
6.0
e
lu
Va
R
of
TS
ET
Safe Operating Area
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
70.0
67.5
62.5
65.0
57.5
60.0
55.0
52.5
50.0
47.5
42.5
45.0
37.5
40.0
35.0
30.0
32.5
27.5
25.0
20.0
22.5
17.5
12.5
15.0
10.0
RTSET (k7)
Typical Application Circuit
+12 V
C2
0.1 μF
C1
22 μF/ 25 V
CBOOT
0.01 μF
BOOT
VIN
ENB
TSET
RTSET
30.1 kΩ
L1
47 μH
LX
A 8499
VBIAS
GND
FB
R1
10 kΩ
D1
B340
VOUT
5.0 V / 1.8 A
COUT
330 μF/ 6.3 V
(Aluminum)
R2
3.16 kΩ
12 V step down to 5.0 V at 1.8 A
Pin-out Diagram
BOOT
1
8
VIN
ENB
2
7
LX
TSET
3
6
VBIAS
GND
4
5
FB
Pad
Terminal List Table
Pin Name
BOOT
ENB
TSET
GND
NC
NC
FB
VBIAS
LX
VIN
Pad
Pin Description
Gate drive boost node
On/off control logic input
Off-time setting
Ground
No connect
No connect
Feedback for adjustable regulator
Bias supply input
Buck switching node
Supply input
Exposed pad for thermal dissipation
Pin Number
1
2
3
4
N/A
N/A
5
6
7
8
Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8499
High Voltage Step-Down Regulator
Package LJ 8-Pin SOIC
4.90 ±0.10
0.65
8°
0°
8
B
A
1
3.90 ±0.10
6.00 ±0.20
2
SEATING PLANE
GAUGE PLANE
Branded Face
SEATING
PLANE
0.10 C
1.27 BSC
1
1.27
0.40
0.25 BSC
0.51
0.31
2.41
1.04 REF
3.30 NOM
8X
C
5.60
2
3.30
C
PCB Layout Reference View
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.70 MAX
0.15
0.00
1.27
1.75
0.25
0.17
2.41 NOM
8
A Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
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permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
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nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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