A8587 Datasheet

A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
FEATURES AND BENEFITS
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DESCRIPTION
The A8587 is a high-frequency step-down switching regulator
with an integrated high-side power MOSFET. It provides up
to 2 A output current. The A8587 can achieve fast transient
response using current-mode control and simple external
compensation.
Automotive AEC-Q100 qualified
Supply voltage from 3.8 to 36 V
Output voltage adjustable from 0.8 to 30 V
Maximized duty cycle for low-dropout operation
Low 30 μA operational quiescent current
150 mΩ integrated MOSFET switch
Programmable switching frequency up to 4 MHz
Improved EMC with frequency dithering and controlled
switch-node rise and fall times
Active-low power-on reset signal (NPOR)
Ceramic capacitor stable
Internal soft-start
Overcurrent protection
APPLICATIONS
• High-voltage power
conversion
• Automotive systems
• Industrial power systems
The wide input range of 3.8 to 36 V makes the A8587
suitable for a wide range of step-down applications, including those
in an automotive input environment. Battery-driven applications
benefit from the low 30 μA operational quiescent current.
The A8587 maintains high efficiency across a wide load range
by the use of pulse-frequency modulation (PFM) as the load
reduces. This in turn reduces switching and gate driver losses
at light load.
Frequency foldback helps to prevent inductor current runaway
during startup and provides enhanced dropout performance.
Extensive protection features of the A8587 include pulse-bypulse current limit, hiccup-mode short-circuit protection, open/
short freewheeling diode protection, BOOT open/short voltage
protection, VIN undervoltage lockout, and thermal shutdown.
• Distributed power systems
• Battery-powered systems
The A8587 also provides an active-low power-on reset (NPOR)
signal. This signal goes high—after a short delay—when
VOUT reaches regulation, and it goes low when VOUT falls
out of regulation.
PACKAGES:
10-Pin DFN with Exposed
Thermal Pad (suffix EJ)
The A8587 is designed to aid in EMC/EMI design by including
frequency dithering, soft freewheel diode turnoff, and wellcontrolled switch-node slew rates. A 4 MHz oscillator allows
the A8587 to switch outside EMI-sensitive frequency bands
such as the AM band or ADSL bands.
The A8587 is available in an industry standard DFN10 package.
Not to scale
CBST
LO
BST
VIN
FB
VIN
NPOR
COMP
EN
CZ
RZ
CP
(optional)
GND
CIN
VOUT
SW
FREQ
VIN
RFB1
RFREQ
A8587 Simplified Schematic
A8587-DS
COUT
D
RFB2
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
SPECIFICATIONS
SELECTION GUIDE
Part Number
Package
Packing
A8587KEJTR-T
10-Pin DFN with Thermal Pad
1,500 pieces per 7-inch reel
ABSOLUTE MAXIMUM RATINGS1
Characteristic
Symbol
Input Voltage
VIN
Switch-Node Voltage
VSW
Bootstrap Pin to Switch Node
Notes
Rating
Unit
−0.3 to 40
V
−0.3 to VIN+0.3
V
t < 250 ns
−1.5
V
t < 50 ns
VIN+3
V
VBST-SW
EN, FREQ
All Other Pins
−0.3 to 6
V
−0.3 to VIN+0.3
V
−0.3 to 6
V
Junction Temperature
TJ
−40 to 150
ºC
Storage Temperature Range
Tstg
−40 to 150
ºC
1
Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Test Conditions*
Value
Unit
Input Voltage
VIN
3.8 to 36
V
Junction Temperature
TJ
−40 to 150
ºC
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Junction to Ambient Thermal
Resistance
2 Additional
Symbol
RθJA
Test Conditions2
DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard
Value
Unit
45
ºC/W
thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
VIN
9
VIN
8
EN
2
Boot
Charge
10
BST
1
SW
–
+
+
3
COMP
0.8 V
5
NPOR
VREG
LDO
BST
Dither
FREQ
7
FB
4
VREG
PWM
Generator
Osc
–
+
VREG
Soft Start
Ramp
0.88 V
–
+
–
GND
6
0.73 V
+
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
PINOUT DIAGRAM AND TERMINAL LIST TABLE
SW
1
EN
2
COMP
3
FB
NPOR
10 BST
9
VIN
8
VIN
4
7
FREQ
5
6
GND
PAD
Package EJ Pinouts
Terminal List Table
Pin
Name
Pin
Number
SW
1
The source of the internal MOSFET. The output inductor (LO) and cathode of the freewheel diode (D) should be connected to
this pin. LO and D should be placed as close as possible to this pin and connected with relatively wide traces.
EN
2
Enable input. This pin is a high-voltage input that turns the regulator on or off. Set this pin high to turn the regulator on or set
this pin low to turn the regulator off.
COMP
3
Output of the error amplifier and compensation node for the current-mode control loop. Connect a series RC network from this
pin to GND for loop compensation. See the Applications section of this datasheet for further details
FB
4
Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output node, VOUT, to this pin to
program the output voltage.
NPOR
5
Active-low power-on reset output signal. This pin is an open-drain output that transitions from low-impedance to high-impedance
when the output is within the final regulation voltage.
GND
6
Ground connection.
FREQ
7
Frequency setting pin. A resistor, RFREQ, from this pin to GND sets the PWM switching frequency. See Table 1 and Figure 2 to
determine the value of RFREQ.
VIN
8,9
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. Connect this pin to a power
supply of 3.8 to 36 V. A high-quality ceramic capacitor should be placed very close to this pin and GND.
BST
10
Bootstrap capacitor connection. Connect a capacitor from this pin to the SW pin. The voltage on this capacitor drives the
internal MOSFET via the high-side gate driver.
Description
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
ELECTRICAL CHARACTERISTICS1: Valid for VIN = 12 V, VEN = 2.5 V, VCOMP = 1.4 V, –40°C ≤ TJ ≤ 125°C, typical values at TJ = 25°C,
unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VEN ≥ 2.5 V
3.8
VIN rising
2.6
12
36
V
3
3.4
V
GENERAL SPECIFICATIONS
Operating Input Voltage
VIN UVLO Start
VIN
VIN(START)
VIN UVLO Hysteresis
Supply Quiescent Current1
VIN(HYS)
IQ
IQ(SLEEP)
–
0.4
–
V
No load, VFB = 0.9 V
–
27
36
µA
VEN = 0 V
–
11
18
µA
1.6
2.0
2.4
MHz
–
170
–
ºC
20
–
ºC
PWM SWITCHING FREQUENCY
Switching Frequency
fSW
RFSET = 45 kΩ
THERMAL PROTECTION
Thermal Shutdown Threshold2
TTSD
Hysteresis2
THYS
–
Minimum On-Time2
tON(MIN)
–
80
160
ns
Minimum Off-Time2
tOFF(MIN)
–
100
–
ns
Thermal Shutdown
TJ rising
PULSE-WIDTH MODULATION (PWM)
INTERNAL MOSFET
MOSFET On-Resistance
RDS(on)
VBOOT-SW = 5 V
–
150
–
mΩ
MOSFET Leakage
IFET(LKG)
VEN = 0 V, VIN = 12 V, VSW = 0 V, TJ = 25°C
–
0.1
1
µA
4.5 V ≤ VIN ≤ 36 V, TJ = 25°C
0.786
0.792
0.803
V
4.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 125°C
0.773
ERROR AMPLIFIER
Feedback Voltage
VFB
Error Amp Voltage Gain2
AVOL
0.812
V
–
1000
–
V/V
Error Amp Transconductance2
gm
ICOMP = ±3 µA
35
60
95
µA/V
Error Amp Min Source Current
IEA(SOURCE)
VFB = 0.7 V
–
–5
–
µA
IEA(SINK)
VFB = 0.9 V
Error Amp Min Sink Current
Low IQ Peak Current Threshold
IPEAK(LO_IQ)
–
5
–
µA
–
350
–
mA
–
1.5
–
ms
SOFT-START
Soft-Start Ramp Time2
tSS
0 V < VFB < 0.8 V
CURRENT PROTECTION
Current Limit
ILIM
2.3
2.7
–
A
COMP to Current-Sense
Transductance2
GCS
–
4.5
–
A/V
–
1.5
–
A/µs
1.5
1.85
V
Slope Compensation
SE(2MHz)
Measured at fSW = 2 MHz
LOGIC ENABLE
EN Threshold Rising
EN Threshold Falling
EN Hysteresis
1
2
VEN(H)
VEN rising
1.2
VEN(L)
VEN falling
1.0
1.2
1.4
V
–
300
–
mV
VEN(HYS)
For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin
(sinking).
Ensured by design and characterization, not production tested.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
ELECTRICAL CHARACTERISTICS1 (continued): Valid for VIN = 12 V, VEN = 2.5 V, VCOMP = 1.4 V, –40°C ≤ TJ ≤ 125°C, typical values at
TJ = 25°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
POWER-ON RESET (NPOR)
Undervoltage Threshold (Falling)
VNPOR(UV)
NPOR = low
710
730
750
mV
Undervoltage Hysteresis
VNPOR(HYS)
NPOR = low
–
15
–
mV
Overvoltage Threshold (Rising)
VNPOR(OV)
NPOR = low
840
880
920
mV
5
7.5
10
ms
NPOR Rising Delay
td(NPOR)
NPOR Output Voltage
VNPOR
INPOR = 10 mA, fault asserted
–
–
500
mV
VIN(NPOR)
NPOR pull-up of 2 kΩ to 5 V
–
3.5
–
V
VNPOR = 5.5 V, fault not asserted
–
–
1
μA
Minimum VIN for Correct Operation
of NPOR
NPOR Leakage 2
1
2
INPOR
For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
Ensured by design and characterization, not production tested.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
FUNCTIONAL DESCRIPTION
Overview
The A8587 is a PWM buck regulator that incorporates all of the
control and protection circuitry necessary to satisfy a wide range
of low-voltage applications. The A8587 employs current-mode
control to provide fast transient response, simple compensation,
and excellent stability.
The features of the A8587 include a ±3% reference, an adjustable switching frequency, a transconductance error amplifier, an
enable input, integrated power MOSFET, fixed soft-start time,
and low-current sleep mode.
The protection features of the A8587 include undervoltage
lockout (UVLO), cycle-by-cycle overcurrent protection (OCP),
hiccup-mode short-circuit protection (HIC), overvoltage protection (OVP), and thermal shutdown (TSD).
PWM Control
The A8587 includes a high-speed PWM comparator, capable of
pulse widths less than 100 ns. The inverting input of the comparator is connected to the output of the error amplifier. The noninverting input is connected to the current-sense signal.
At the beginning of each PWM cycle, the PWM_CLK signal
sets the PWM flip-flop and the high-side MOSFET is turned
on. When the current-sense signal rises above the error amplifier voltage, the comparator resets the PWM flip-flop and the
high-side MOSFET is turned off. It remains off for at least 100 ns
before the next cycle can be initiated.
Low-IQ Pulse-Frequency-Modulation (PFM)
Mode
At light loads, the PFM comparator, which is connected to the
FB pin, modulates the frequency of the SW node to regulate the
output voltage with very high efficiency.
The reference for the PFM comparator is calibrated approximately 1% above the PWM regulation point. When the voltage at
the internal FB point rises above the PFM comparator threshold
and peak inductor current falls below IPEAK(LO_IQ) (800 mA)
minus slope compensation, the device will enter PFM-coast
mode, tri-stating the SW node and drawing extremely low current from VIN. When voltage at the FB point falls below the
PFM comparator threshold, the device will fully power-up after
approximately a 2.5 μs delay, and the high-side MOSFET is
repeatedly turned on, operating at the PWM switching frequency,
until the voltage at the FB pin rises above the PFM comparator
threshold. VOUT will rise at a rate determined by—and have a
voltage ripple dependent on—the input voltage, output voltage,
inductor value, output capacitance, and load. In addition, the
transition point from PWM to PFM mode is defined by the input
voltage, output voltage, slope compensation, and inductor value.
Error Amplifier
The primary function of the transconductance error amplifier is
to regulate the A8587 output voltage. The error amplifier appears
as a device with three inputs: two positive and one negative. The
negative input is simply connected to the FB pin and is used to
sense the feedback voltage for regulation. The two positive inputs
are connected to the internal soft-start and reference voltages. The
error amplifier performs an analog OR selection between them;
it regulates to either the soft-start voltage or the A8587 internal
reference (VREF), whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZ CZ) must be connected from the error amplifier output
(COMP pin) to GND, as shown in the typical application schematic. In most applications, an additional low-value capacitor
(CP) should be connected in parallel with the RZ CZ compensation network to roll-off the loop gain at higher frequencies.
However, if the CP capacitor is too large, the phase margin of the
regulator may be reduced.
During operation, the minimum COMP voltage is clamped to
750 mV, and its maximum is clamped to 1.5 V. COMP is internally pulled down to GND during fault conditions.
Slope Compensation
The A8587 incorporates internal slope compensation (SE) to
allow PWM duty cycles above 50% for a wide range of input and
output voltages and inductor values. The slope compensation signal is added to the sum of the current-sense amplifier output and
the PWM ramp offset. The amount of slope compensation scales
with the maximum on-time (1/fSW – tOFF(MIN)), centered around
3.1 A/μs at 2 MHz. The value of the output inductor should be
chosen such that SE is between 0.5× and 1× the falling slope of
the inductor current (SF).
Internal Regulator
An internal series pass regulator (LDO) generates around 2.9 V
for most of the internal circuits of the A8587. The power for this
LDO is derived from VIN. The LDO is in full regulation once
VIN is greater than 3 V.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
Enable Control
Active-Low Power-On Reset (NPOR) Output
The Enable (EN) input provides enabling/disabling of the A8587
with system control, or enabling/disabling of the A8587 automatically. The EN pin is rated to 40 V, so this pin may be connected
directly to VIN if there is no suitable logic signal available to
wake up the regulator.
The Active-Low Power-On Reset (NPOR) output is an open-drain
output, so an external pull-up resistor must be connected to it. An
internal comparator monitors the voltage at the FB pin and controls
the internal open-drain N-MOSFET at the NPOR pin. NPOR is
high when the voltage at the FB pin is within regulation. At startup,
there is an NPOR delay (td(NPOR)) before NPOR goes high.
When EN is used as a system-controlled enabling/disabling logic
input, and EN is kept high, the A8587 turns on, and provided
there are no fault conditions, VOUT will ramp to its final voltage
in the soft-start time. When the EN is low, the A8587 will enter
shutdown mode and draw less than 20 μA from the input.
When EN transitions low, the device waits approximately 150 μs
before shutting down. This delay provides plenty of filtering
to prevent the device from prematurely entering Sleep mode
because of any small glitches that might couple onto the PCB
trace or EN pin.
The Enable input can also be used as a programmable UVLO.
Connecting a resistor from VIN to Enable and a second resistor
from Enable to ground implements this feature.
A8587
VIN
VIN(START) =
R1 + R2
× VEN(H)
R2
(1)
VIN(STOP) =
R1 + R2
× VEN(L)
R2
(2)
R1
EN
R2
While there is an internal 1 μA current source that pulls EN up if
Enable is not used, it is recommended to connect it to VIN so the
A8587 is automatically enabled once VIN exceeds VIN(START).
Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage
is below the lockout threshold (VIN(START)). The UVLO comparator incorporates enough hysteresis (VIN(HYS)) to prevent on/off
cycling of the regulator due to IR drops in the VIN path during
heavy loading or during startup.
The NPOR output is pulled low if any of the following are true:
• VFB is rising, and is < VNPOR(UV), or
• VFB is rising, and is > VNPOR(OV), or
• VIN pin UVLO occurs, or
• Thermal Shutdown (TSD) occurs.
NPOR will remain low only as long as the internal circuitry is
able to enhance the open-drain output device. When VIN fully
collapses, NPOR will return to the high-impedance state. The
NPOR comparator incorporates hysteresis to prevent chattering
due to voltage ripple at the FB pin.
Low-Dropout Operation
The A8587 is designed to operate with one quarter of the switching
frequency when an off-time of greater than tOFF(MIN) is demanded.
Internal Soft-Start
Inrush current to the regulator is controlled by the soft-start function. When the A8587 is enabled, after all faults are cleared, the
soft-start will ramp upward from 0 to 0.8 V. The error amplifier
output slews upward, and shortly thereafter, PWM switching will
begin.
After the A8587 starts switching, the error amplifier will regulate
the voltage at the FB pin to the internal soft-start voltage. After
switching starts, the regulator output voltage will rise from 0 V
to the set point determined by the feedback resistor divider (RFB1
and RFB2). When the voltage of the internal soft-start reaches
0.8 V, the error amplifier will change mode and begin regulating
to the A8587 internal reference, 792 mV.
To keep the inductor current under control, the A8587 operates
with one quarter of the switching frequency while FB remains
below 200 mV, and half of the switching frequency when FB is
between 200 and 400 mV. The A8587 operates at the full switching frequency when FB is greater than 400 mV.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
Pre-Biased Startup
Overcurrent Protection (OCP) and Hiccup
Mode
If the output of the regulator is pre-biased to some voltage, the
A8587 modifies the normal startup routine in order to prevent
discharging the output capacitors. As described previously, the
error amplifier usually becomes active when the soft-start voltage
starts to ramp. If the output is pre-biased, the internal FB voltage
is at some non-zero voltage. The COMP pin remains low and SW
is tri-stated until the soft-start voltage rises above the VFB.
An OCP counter and hiccup-mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when
the load is too high. When the soft-start ramp is active (t < tSS),
the OCP hiccup counter is disabled. Two conditions must be met
for the OCP counter to be enabled and begin counting:
Thermal Shutdown
• VCOMP clamped at its maximum voltage (OCL = 1)
MOSFET Driver and Bootstrap Capacitor
The position of the internal N-channel MOSFET requires special
consideration when driving it. The source of this MOSFET can
be either close to VIN or close to GND. For that reason, a floating gate charge driver is required. This driver requires a voltage
greater than VIN to ensure the MOSFET can be turned on.
A simple charge pump—consisting of an internal charge circuit, an external capacitor (BST capacitor), and the freewheeling diode—is required to power the high-side gate driver. The
internal charge circuit is power by VIN. When the SW node is
sufficiently below VIN, the charge circuit will charge the BST
capacitor to around 5 V with respect to the SW node. This BST
voltage is used to turn the MOSFET on. As SW node rises, the
BST capacitor will maintain the BST pin at 5 V above SW,
thereby ensuring sufficient voltage to keep the MOSFET on.
For higher performance at low VIN, an external Schottky diode
can be placed between VOUT and BOOT when VOUT is configured for <5.5 V
Also, the BST charge circuit incorporates its own UVLO of 1.8 V
rising and 0.4 V hysteresis.
Current Comparator and Current Limit
A high-bandwidth current-sense amplifier monitors the current
in the high-side MOSFET. The current signal is supplied to the
PWM comparator and the cycle-by-cycle current limiter.
The cycle-by-cycle maximum current of the internal power
MOSFET is internally limited.
As long as these two conditions are met, the OCP counter
remains enabled and counts pulses from the overcurrent comparator. If the COMP voltage decreases (OCL = 0), the OCP counter
is cleared. If the OCP counter reaches the OCPLIM counts (120),
a hiccup latch is set and the COMP pin is quickly pulled down by
a relatively low resistance (4 kΩ). Switching is halted for 6 ms to
provide time for the IC to cool down. After the hiccup off-time
expires (6 ms), the soft-start ramp starts, marking the beginning
of a new, normal soft-start cycle as described earlier. When the
soft-start voltage crosses the effective output voltage, the error
amplifier forces the voltage at the COMP pin to quickly slew
upward and PWM switching resumes. If the short-circuit at the
regulator output remains, another hiccup cycle occurs. Hiccups
repeat until the short-circuit is removed or the converter is disabled. If the short-circuit has been removed, the device soft-starts
normally and the output voltage automatically recovers to the
target level.
3.46
3.26
3.06
Current Limit (A)
The A8587 protects itself from overheating by means of an
internal thermal monitoring circuit. If the junction temperature
exceeds the thermal shutdown threshold (TTSD, 170°C typical), the voltages at the soft-start and COMP pins will be pulled
to GND and the high-side MOSFET will be turned off. The
A8587 will automatically restart when the junction temperature
decreases more than the thermal shutdown hysteresis (THYS,
20°C typical).
• t > tSS, and
2.86
2.66
2.46
2.26
2.06
1.86
1.66
1.46
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
Min. 400 kHz
Typ. 400 kHz
Max. 400 kHz
Min. 2 MHz
Typ. 2 MHz
Max. 2 MHz
Figure 1: Current Limit versus Duty Cycle
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
BOOT Capacitor Protection
The A8587 monitors the voltage across the BOOT capacitor to
detect if the capacitor is missing or short-circuited. If the BOOT
capacitor is missing, the regulator enters hiccup mode after
7 PWM cycles. If the BOOT capacitor is shorted, the regulator
enters hiccup mode after 120 PWM cycles. For a BOOT fault,
hiccup mode operates virtually the same as described previously
for an output short-circuit fault (OCP), having a hiccup off-time
of 6 ms, followed by a soft-start retry, with repeated attempts
until the fault clears. However, OCP is the only fault that is
ignored during the soft-start ramp time (tSS). BOOT faults are a
non-latched condition, so the device automatically recovers when
the fault is corrected.
Freewheeling Diode Protection
If the freewheeling diode is missing or damaged (open), the SW
pin is subject to unusually high negative voltages. This negative voltage may cause the device to malfunction and could lead
to damage. The A8587 includes protection circuitry to detect
when the freewheeling diode is missing. If the SW pin is below
−1.25 V typically, for more than 50 ns typically, the device enters
hiccup mode after detecting one missing diode fault. Also, if the
freewheeling diode is shorted, the device experiences extremely
high currents through the high-side MOSFET. If this occurs, the
device enters hiccup mode after detecting one shorted diode fault.
Overvoltage Protection (OVP)
The A8587 provides an always-on overvoltage protection that
monitors VOUT, to protect against VOUT rising up at light loads
due to high-side switch leakage. In this case, the high-side switch
is forced off, and the low-side switch continues to operate and
can correct the OVP condition, provided only a few milliamperes
of pull-down current are required. When the condition causing
the overvoltage is corrected, the regulator automatically recovers.
Pin-to-Ground and Pin-to-Pin Short Protections
The A8587 is designed to satisfy the most demanding automotive applications. For example, the device is carefully designed
fundamentally to withstand a short-circuit to ground at each
pin without suffering damage. In addition, care was taken
when defining the device pin-out to optimize protection against
adjacent pin-to-pin short-circuits. For example, logic pins and
high-voltage pins are separated as much as possible. Inevitably,
some low-voltage pins had to be located adjacent to high-voltage
pins, but in these instances, the low-voltage pins are designed to
withstand increased voltages, with clamps, series input resistance,
or both, to prevent damage to the device.
Startup and Shutdown
If both VIN and VEN are higher than their appropriate thresholds,
the chip starts. The reference block starts first, generating stable
reference voltage and currents, and then the internal regulator is
enabled. The regulator provides stable supply for the remaining
circuits.
When the internal soft-start block is enabled, it first holds its SS
output low to ensure the remaining circuits are ready and then
slowly ramps up.
Three events can shut down the chip: VEN low, VIN low, and thermal shutdown. In the shutdown procedure, the power MOSFET is
turned off first to avoid any fault triggering. The COMP voltage
and the internal supply rail are then pulled down.
Programmable Oscillator
A resistor (RFREQ) from FREQ to ground sets the operation
frequency of the A8587. The Applications Information section
details the selection of this resistor.
Frequency Dithering
The A8587 includes a dithering function, which changes the
switching frequency within a certain frequency range. By shifting the switching frequency of the regulator in a triangle fashion
around the programmed switching frequency, the overall systemnoise magnitude can be greatly reduced.
The dithering sweep is internally set at ±8%. The switching
frequency will ramp from a low of 0.92 times the programmed
frequency to a high of 1.08 times the programmed frequency. The
rate or modulation at which the frequency sweeps is governed by
an internal 12 kHz triangle pattern.
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Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
APPLICATIONS INFORMATION
Setting the Switching Frequency
30
Maximum Input Voltage (V)
The switching frequency (fSW) of a regulator using the A8587
can be set using a resistor at the FREQ pin (RFREQ). The recommended RFREQ value for various switching frequencies can be
obtained from either Table 1 or Figure 2 below:
Table 1: RFREQ versus fSW
fSW (MHz)
RFREQ (kΩ)
4
15.4
3.5
20
3
26.1
2.5
34
2
45.3
1.5
68.1
1
105
0.8
140
0.5
232
0.3
402
0.2
619
25
20
VOUT = 3.3 V
15
10
VOUT = 2.5 V
5
1.5
2
3.5
4
Figure 3: Recommended Switching Frequency vs.
Maximum Input Voltage
Setting the Output Voltage
Many output voltages can be programmed by the selection of the
right resistor pair, RFB1 and RFB2. These resistors form a voltage
divider between VOUT and GND with FB pin as the center. The
voltage divider divides the output voltage down to the feedback
voltage.
700
600
RFB1 =
500
RFREQ (kΩ)
3
2.5
Switching Frequency (MHz)
400
VOUT
– VFB
VFB
(3)
× RFB2
Table 2 below shows some typical resistor values selected from
the E48 series for popular output voltages, using RFB2 = 40.2 kΩ.
More accurate output voltage set points can be achieved by using
a parallel combination for RFB1.
300
200
Table 2: RFB1 versus VOUT, RFB2 = 40.2 kΩ
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Switching Frequency (MHz)
Figure 2: RFREQ versus fSW
While the A8587 can switch at frequencies up to 4 MHz, care
must be taken when operating above 2 MHz. The minimum
controllable on-time for the A8587 is around 80 ns. This means
at higher frequencies, pulse skipping may be seen when trying to
achieve small duty cycles.
VOUT (V)
RFB1 (kΩ)
1
10
1.2
20.5
1.5
34.8
1.8
51.1
2
59
2.5
86.6
2.7
95.3
3.3
127
5
215
12
562
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11
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
Inductor
As with any buck converter, an inductor is required to supply constant current to the output load while being driven by the switched
input voltage. Many factors determine the selection of this inductor, such as switching frequency, output/input voltage ratio,
transient response, and ripple current. A larger-value inductor will
result in less ripple current that will result in lower output ripple
voltage. However, the larger-value inductor will have a larger physical size, higher series resistance, and/or lower saturation current.
A good rule for determining the inductance to use is to allow the
peak-to-peak ripple current in the inductor to be approximately
30% of the maximum output current (IOUT(MAX)). Also, ensure
the peak inductor current during normal operation is below the
maximum switch current limit. The inductance value can be
calculated by:
LO =
(
V
VOUT
× 1 – OUT
fSW × ΔIL
VIN
)
(4)
where VOUT is the output voltage, VIN is the input voltage, fSW
is the switching frequency, and ΔIL is the peak-to-peak inductor
ripple current (0.3 × IOUT(MAX)).
A second constraint on inductor value would be loop stability
at duty cycles greater than 50%. The A8587 uses current-mode
control and includes internal slope compensation (SE). Based on
the SE value, recommended inductance for stability would be:
LO ≥
VOUT
SE
(
× 1 – 0.18 ×
)
VIN(MIN)
VOUT
(5)
Slope compensation (SE) will vary with switching frequency. SE
can be calculated using equation 6:
(
SE = SE(2MHz) ×
1
2 MHz
1
fSW
)
– 100 ns
– 100 ns
Choose an inductor that will not saturate under the maximum
inductor peak current, which is the current limit of the A8587,
over the full temperature range.
Also, ensure the peak current at IOUT(MAX) does not exceed the
current limit. The peak inductor current can be calculated by:
(6)
ILPK = IOUT(MAX)+
VOUT
2 × fSW × LO
×
( 1 – VV )
OUT
(7)
IN
Freewheeling Diode
The freewheeling diode allows the current in the inductor to flow
to the load when the high-side switch is off. To reduce losses due to
diode forward voltage and recovery times, use a Schottky diode.
Choose a diode with a maximum reverse voltage rating greater
than the maximum input voltage and a current rating greater than
the maximum load current.
Input Capacitor
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input voltage with adequate design margin. Second,
their rms current rating must be higher than the expected rms
input current to the regulator. Third, they must have enough
capacitance and a low enough ESR to limit the input voltage
dv/dt to something much less than the hysteresis of the VIN pin
UVLO circuitry (350 mV (typ)) at maximum loading and minimum input voltage.
The input capacitor or capacitors must limit the voltage deviations at the VIN pin to something significantly less than the
A8587 VIN pin UVLO hysteresis during maximum load and
minimum input voltage. The minimum input capacitance can be
calculated as follows:
CIN >
IOUT
0.85 × fSW × ΔVIN
(
VOUT
VOUT
× V × 1–
VIN
IN
)
(8)
where ΔVIN is chosen to be much less than the hysteresis of the
VIN pin, UVLO comparator (ΔVIN ≤ 100 mV is recommended),
and fSW is the nominal PWM switching frequency.
For simplification, choose the input capacitor with an RMS current rating greater than half of the maximum load current.
Output Capacitor
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and store energy to help maintain voltage regulation during a load transient. The voltage rating
of the output capacitors must support the output voltage with
sufficient design margin.
The output voltage ripple (ΔVOUT) is a function of the output
capacitor parameters: COUT, ESR, and ESL:
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Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
ΔVOUT = ΔIL × ESR +
VIN – VOUT
ΔIL
× ESL +
(9)
LO
8×fSW×COUT
where LO is the inductor value, ESR is the equivalent series
resistance of the output capacitor, and ESL is its equivalent series
inductance.
The type of output capacitors will determine which terms of
equation 9 are dominant. For ceramic output capacitors, the ESR
and ESL are virtually zero, so the output voltage ripple will be
dominated by the third term of equation 10:
ΔVOUT =
ΔIL
8 × fSW × COUT
(10)
To reduce the voltage ripple of a design using ceramic output
capacitors, simply increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors, the value of capacitance will be
relatively high, so the third term in equation 9 will be very small.
The output voltage ripple will be determined primarily by the
first two terms of equation 9:
ΔVOUT = ΔIL × ESR +
VIN – VOUT
× ESL
LO
(11)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply decrease the equivalent ESR and ESL by using
a higher-quality capacitor, add more capacitors in parallel, or
reduce the inductor current ripple (that is increase the inductor
value).
The ESR of some electrolytic capacitors can be quite high, so
Allegro recommends choosing a quality capacitor that clearly
documents the ESR, or the total impedance, in the datasheet.
Also, the ESR of electrolytic capacitors usually increases significantly at cold temperatures—by as much as 10×— which
increases the output voltage ripple and in most cases significantly
reduces the stability of the system.
The transient response of the regulator depends on the number
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher-quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
ΔVOUT = ΔIOUT × ESR +
di
× ESL
dt
(12)
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend
on the system bandwidth, the output inductor value, and output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
The speed at which the error amplifier will bring the output voltage back to its set point will depend mainly on the closed-loop
bandwidth of the system. A higher bandwidth usually results in
a shorter time to return to the nominal voltage. However, acceptable gain and phase margins may be more difficult to obtain with
a higher-bandwidth system. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the Compensation Components section of this datasheet.
Low-IQ PFM Output Voltage Ripple Calculation
After choosing an output inductor and an output capacitor or
capacitors, it is important to calculate the output voltage ripple
(ΔVOUT(PFM)) during Low-IQ PFM mode. With ceramic output
capacitors, the output voltage ripple in PWM mode is usually
negligible, but that is not the case during Low-IQ PFM mode.
The PFM-mode comparator requires about 10 mV or greater of
voltage ripple on the VOUT pin and generates groups of pulses
to meet this requirement. However, if a single pulse results in a
voltage ripple greater than 10 mV, then the voltage ripple would
be dictated by that single pulse. To calculate the voltage ripple
from that single pulse, first the peak inductor current must be
calculated with slope compensation taken into account. The
IPEAK(LO_IQ) specification does not include slope compensation;
therefore, the peak inductor current operating point is calculated
as follows:
IPEAK(LO_IQ)
IPEAK_L =
SE × LO
1+
VIN – VOUT
(13)
Then, calculate the MOSFET on-time (tON(Q)) and freewheeling
diode on-time (tON(D)) (Figure 3). The on-time is defined as the
time it takes for the inductor current to reach IPEAK_L:
tON(Q) =
IPEAK_L × LO
VIN – VOUT – IPEAK_L × (RDS(on)HS + LO(DCR) )
(14)
where RDS(on) is the on-resistance of the internal high-side MOSFET (150 mΩ typical) and LO(DCR) is the DC resistance of the
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13
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
output inductor (LO). During this rising time interval, the length
of time for the inductor current to rise from 0 A to IOUT is:
t1 =
IOUT × LO
VIN – VOUT – IPEAK_L × (RDS(on)HS + LO(DCR) )
(15)
The freewheeling diode on-time is defined as the time it takes for
the inductor current to decay from IPEAK_L to 0 A:
tON(D) =
IPEAK_L × LO
(16)
VOUT + VF
During this falling time interval, the length of time for the inductor current to fall from IOUT to 0 A is:
IOUT × LO
(17)
t2 =
VOUT + VF
VOUT
VPP(LO_IQ)
If VPP(LO_IQ) is greater than the ~10 mV ripple that the PFM
comparator requires, then the output capacitance or inductor can
be adjusted to reduce the PFM-mode voltage ripple. In PFM
mode, decreasing the inductor value reduces the PFM ripple, but
may negatively impact the PWM voltage ripple, maximum load
current in PWM mode, or change the mode of operation from
CCM to DCM.
If VPP(LO_IQ) is less than the ~10 mV requirement, the A8587
operates with multiple pulses at the PWM frequency to meet the
ripple requirement. The fixed-frequency operation may result in
DCM or CCM operation during the multiple pulses.
Compensation Components
A8587 employs current-mode control for easy compensation
and fast transient response. The system stability and transient
response are controlled through the COMP pin. COMP pin is the
output of the internal transconductance error amplifier. A series
capacitor-resistor combination sets a pole-zero pair to control the
characteristics of the control system. The DC voltage gain, AVDC,
of the feedback loop is given by:
AVDC =
The system has two noteworthy poles: one is due to the compensation capacitor (CZ) and the error amplifier output resistor; the
other is due to the output capacitor and the load resistor. These
poles are located at:
IPEAK(LO_IQ)
IOUT
t1
tON(Q)
t2
fP1 =
t
fP2 =
Figure 4: Calculating the Output Ripple Voltage in
PFM Mode
Given the peak inductor current (IPEAK_L ) and the rise and fall
times (tON(Q) and tON(D)) for the inductor current, the output voltage ripple can be calculated for a signal pulse as follows:
IPEAK_L – IOUT
× (tON(Q) + tON(D) – t1 – t2 )
2 × COUT
gm
2π × CZ × AVOL
IOUT
2π × COUT × VOUT
(20)
(21)
where gm is the error amplifier transconductance, 60 μA/V.
tON(D)
VPP(LO_IQ) =
(19)
where AVOL is the error amplifier voltage gain, 1000 V/V. GCS is
the current-sense transconductance, 9 A/V.
t
IL
VOUT
VFB
× GCS × AVOL ×
V
IOUT
OUT
(18)
The system has one noteworthy zero. This is due to the compensation capacitor (CZ) and the compensation resistor (RZ). This
zero is located at:
fZ =
1
2π × CZ × RZ
(22)
The system may have another zero, if the output capacitor has a
large capacitance, or a high ESR value, or both. The zero, due to
the ESR and capacitance of the output capacitor, is located at:
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14
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
1
2π × COUT × ESR
In this case (as shown in the simplified schematic on page 1), a
third pole set by the optional compensation capacitor (CP) and the
compensation resistor (RZ) is used to compensate the effect of the
ESR zero on the loop gain. This pole is located at:
fP3 =
1
2π × CP × RZ
(24)
The goal of compensation design is to shape the converter
transfer function to get a desired loop gain. The system crossover
frequency where the feedback loop has unity gain is important. Lower crossover frequencies result in slower line and load
transient responses, while higher crossover frequencies could
cause the system to be unstable. A good rule of thumb is to set the
crossover frequency to approximately one tenth of the switching
frequency. Table 3 lists typical values of compensation components for some standard output voltages with various output
ceramic capacitors and inductors. The values of the compensation
components have been optimized for fast transient responses and
good stability.
Table 3: Compensation Values for Typical Output Voltage/
Capacitor Combinations with fSW = 500 kHz
VOUT
(V)
LO
(µH)
COUT
(µF)
RZ
(kΩ)
CZ
(pF)
CP
1.8
4.7
47
105
100
None
2.5
4.7 to 6.8
22
54.9
220
None
3.3
6.8 to 10
22
68.1
220
None
5
15 to 22
22
100
150
None
12
22 to 33
22
147
values, setting the compensation zero (fZ1) below one fourth
of the crossover frequency provides sufficient phase margin.
Determine the CZ value by the following equation:
4
CZ >
(26)
2π × RZ × fC
(23)
150
None
To optimize the compensation components for conditions not
listed in Table 3, the following procedure can be used:
1. Choose the compensation resistor (RZ) to set the desired
crossover frequency (fC). Determine the RZ value by the following equation:
2π × COUT × fC
V
(25)
RZ =
× OUT
gm × GCS
VFB
2. Choose the compensation capacitor (CZ) to achieve the
desired phase margin. For applications with typical inductor
3. Determine if the second compensation capacitor (CP) is
required. It is required if the ESR zero of the output capacitor
is located at less than half of the switching frequency or the
following relationship is valid:
1
f
(27)
< SW
2π × COUT × ESR
2
If this is the case, then add the second compensation capacitor (CP) to set the pole fP3 at the location of the ESR zero.
Determine the CP value by the equation:
CP =
COUT × ESR
RZ
(28)
Operating at Low Input Voltages
While the A8587 can operate at input voltages down to 3.8 V,
care must be taken to ensure that the internal MOSFET has sufficient gate voltage. To achieve this, it is recommended to add an
external boot diode as shown in Figure 5. This can be a low-cost
diode such as 1N4148 or equivalent. This diode should be connected to a 5 V supply.
CBST
5V
D2
(see note)
LO
BST
VIN
CIN
VIN
FB
VIN
NPOR
COMP
EN
CZ
CP
Optional
RZ
VOUT
SW
GND
fZ =
FREQ
A8587
RFB1
COUT
D
RFREQ
RFB2
Figure 5: Simplified Schematic
Note: D2 is recommended for VIN < 5 V
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15
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference DWG 2860)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.50
0.30
3.00 ±0.15
10
10
0.85
3.00 ±0.15
1.64
3.10
A
1
2
1
11X
D
0.08
2.38
C
0.75 ±0.05
C
SEATING
PLANE
0.25
+0.05
–0.07
C
PCB Layout Reference View
0.5 REF
0.05
0.00
0.5 BSC
1
2
A
Terminal #1 mark area
0.40 ±0.10
B
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
D
Coplanarity includes exposed thermal pad and terminals
1.64 NOM
B
10
2.38 NOM
Figure 6: Package EJ, 10-Pin DFN with Exposed Thermal Pad
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A8587
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
Revision History
Revision
Revision Date
–
March 25, 2016
Description of Revision
Initial Release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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