A8582 Demo Note - 5.0 V OUT , 2.0 A, 2 MHz

Demo Note for the A8582
Evaluation Board
4.7VIN – 40VIN, 5.0VOUT, 2.0A, 2MHz
Asynchronous Buck Regulator
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May 5, 2011
GENERAL SPECIFICATIONS
Specification
Absolute Maximum Input Voltage
Operating Input Voltage Range
VIN START Threshold, VIN rising
VIN STOP Threshold, VIN falling
Output Voltage (FB: 4.75K/24.9K, ±1%)
Steady-State Output Current (12VIN)
Pulse-by-pulse Current Limit @ 30%
Enable/Synchronization Input
Min
–0.3
4.7
−
−
4.812
−
2.6
–0.3
Nom
−
12
4.2
Max
40
36
4.6
3.8
4.994
2.0
−
−
4.2
5.180
2.5
3.4
5.5
Units
Volts
Volts
Volts
Volts
Volts
A
A
Volts
OPERATING INSTRUCTIONS
Input Power Connection:
Connect a 12V power supply from Vin to GND that is capable of at least 2A. Once
operational, VIN can fall as low as 3.8VTYP (4.2VMAX) before the A8582 is reset.
Enable Input Connection:
Connect an Enable signal from EN/SYNC to GND. If the EN/SYNC input voltage is higher
than 1.8V the A8582 will be enabled. If the EN/SYNC input voltage is lower than 0.8V the
A8582 will be disabled. Also, EN/SYNC may be used to simultaneously enable the A8582 and
synchronize the PWM switching frequency by applying a square wave above 2.2MHz.
Note: Continuously applying more than 5.5V to the EN/SYNC pin may damage the A8582.
Output Load Connections:
Connect a load from VOUT to GND. The steady-state load current can be as high as 2.0A. Pulseby-pulse current limit and/or thermal shutdown will occur if the load is greater than 4.75A.
DEMO BOARD PICTURE
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May 5, 2011
DEMO BOARD SCHEMATIC
TP1
Vin
U1
A8582
C1
47uF
50V
8mm
CIN2
Empty
50V
1210
SW
SW
BOOT
FBX
TP3
EN/SYNC
7
EN/Sync
TP4
SS
TP14 GND
TP15 GND
TP16 GND
TP17 GND
CSS
22nF
0603
11.5K = 2MHz
RFSET
11.5K
4
TP5
FSET
8
TP6
COMP
11
RZ 13
CP
4.7pF 23.2K
0603
14
SW
TP8
BOOT
10
TP9
FBX
EN/SYNC
SS
Cboot
100nF
50V
0603
Rboot
Empty
FB
RFB1
24.9K
9
TP10
FB
FSET
CFBX
120pF
50V
0603
NC
POK
6
CO2
Empty
16V
1206
CO3
Empty
xxV
8mm
D1
B340A
SMA
CO1
10uF
16V
1206
TP13
GND
RS1
24.9K
SW
RS2
4.75K
Bode
Empty
Snubber on bottom of PCB
Rsnub
4.7
Csnub
470pF
0603
RPU
100K
COMP
TP11
Vout
VOUT
RFB2
4.75K
TP12
POK
RPD
Empty
0
CZ
1.2nF
0603
16
15
1
Vin
Vin
Vin
GND
GND
AC
TP2
GND
CIN1
3.3uF
50V
1210
LO
3.3uH
5.2mm x 5.5mm
IHLP2020BZER3R3M01
2
1
2
3
5
12
VIN
TP7
SW
RPD should be used if Vout > 5.5V
A8582 Evaluation PCB
Note: C1 is an optional, bulk, electrolytic capacitor for general supply filtering
DEMO BOARD BILL-OF-MATERIALS
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May 5, 2011
DEMO BOARD PERFORMANCE
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May 5, 2011
Page 5 of 10
May 5, 2011
12Vin, 2.0A Load: 0dB at 181KHz, PM=48.9deg, GM=9.7dB
Iout
(A)
A8582
(deg C)
D1
(deg C)
Lo
(deg C)
0.25
31.4
30.5
29.8
0.5
34.0
33.9
32.0
1.0
37.8
39.6
37.6
1.5
46.9
50.5
46.4
2.0
53.6
59.7
56.5
2.5
63.3
70.4
69.4
Shorted Vout
33.5
35.4
34.5
Component Temperatures vs Load Current
12Vin, 5.0Vout, 2MHz, TAMB=25deg C
No Airflow (still air)
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May 5, 2011
Startup
12Vin, 2.0A (2.5Ω) load
CH1=Vout, CH2=COMP, CH3=EN, CH4=SS
Shutdown
12Vin, 2.0A (2.5Ω) load
CH1=Vout, CH2=COMP, CH3=EN, CH4=SS
Output Voltage Ripple
12Vin, 2.0A (2.5Ω) load
CH1=Vout (20mV/DIV)
Transient Response
12Vin, 0.5A to 1.5A (1.0A step)
CH1=Vout, CH2=COMP, CH4=Iout
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May 5, 2011
SWN Voltage at 12Vin, 100mA load
CH1=SWN (5V/DIV), 200ns/DIV
SWN Voltage at 12Vin, 2.0A load
CH1=SWN (5V/DIV), 200ns/DIV
Input Voltage Ripple at 12Vin, 2.0A load
CH1=Vin across CIN1 (50mV/DIV)
Output Shorted, Hiccup Mode Operation
CH1=Vout, CH2=COMP, CH3=SS, CH4=IL
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May 5, 2011
DEMO PCB LAYOUT:
Top Layer and Top Silk
Layer 2 and Top Silk
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May 5, 2011
Layer 3 and Top Silk
Bottom Layer and Top Silk
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May 5, 2011
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