DESIGN FEATURES Versatile Power Supply Tracking by Dan Eddleman without MOSFETs Introduction Modern electronics systems often have complex power supply voltage tracking and sequencing requirements. Ignoring these requirements can result in the immediate destruction of devices, or worse yet, premature failures in the field. Voltage tracking requirements usually specify that the voltage difference between two power supplies must never exceed a certain limit. This constraint applies at all times: during power up, power down, and steady state operation. In contrast, supply sequencing requirements specify the order in which supplies power up and power down. Figure 1 shows various tracking and sequencing scenarios. The penalty for poor tracking or sequencing is often irreparable damage to devices in the system. FGPAs, PLDs, DSPs and microprocessors typically have diodes placed between the core and I/O supplies as a component of the ESD protection. If the supplies violate the tracking requirements and forward bias the protection diodes, the device may be damaged. Forward biasing internal diodes, whether protection diodes or other diodes inherent to the CMOS process, may trigger latchup destroying the device. In other cases, when the I/O supply rises before the core supply, undefined logic states in the core can cause excessive current in the I/O circuitry. Even when the individual components of a system do not require supply tracking or sequencing, the complete system may require power supply sequencing for proper operation. For example, a system clock may need to start before a block of logic is powered. A Simple and Versatile Solution a. Coincident tracking b. Offset tracking c. Ratiometric tracking d. Supply sequencing Figure 1. Types of power supply voltage tracking Linear Technology Magazine • February 2004 The LTC2923 provides a simple and versatile solution to both power supply tracking and sequencing without the drawbacks of series MOSFETs. By selecting a few resistors, the supplies are configured to ramp-up and ramp-down with a variety of voltage profiles. Tracking requirements can dictate that supply voltages are equal during ramp up and ramp down (Figure 1a), or that the supplies must ramp up and down with fixed voltage offsets between them (Figure 1b), or that they must ramp up and down ratiometrically (Figure 1c). Alternatively, supply sequencing may be required, which can also be handled by the LTC2923 (Figure 1d). Many voltage tracking solutions use series MOSFETs, which have the problems of an inherent voltage drop, additional power consumption, and extra PC board real estate. Instead, the LTC2923 controls supplies by injecting current into their feedback nodes and thus avoids the pass element losses inherent in series MOSFET solutions. Furthermore, power supply stability and transient response remain unaffected because the injected current from the LTC2923 offsets the output voltage without al13 DESIGN FEATURES tering the power supply control loop dynamics. Power supply tracking is straightforward with the LTC2923. It controls two slave supplies that track a master signal. A pair of resistors configures the behavior of each slave supply relative to the master signal. The choice of resistors can cause a slave supply to track the master signal exactly or with a different ramp rate, voltage offset, time delay, or combination of these. An optional series FET provides support for a third supply or any supply that does not allow direct access to its feedback resistors, such as module power supplies, as shown in Figure 2. When the optional series FET is used, its output serves as the master signal. If the series FET is not used, the master signal is generated by tying a capacitor from the GATE and RAMP pins to ground as shown in Figure 3. How a Simple Cell Tracks and Sequences Supplies The operation of the LTC2923 is based on the simple tracking cell shown in Figure 4. This cell servos the TRACK pin to 0.8V and mirrors the current supplied by that pin at the FB pin. Connecting a resistive divider from the master signal to the TRACK pin configures the FB pin’s current as a function of the master signal. By selecting the appropriate resistor values, R TA and R TB, it is possible to generate any of the profiles shown in Figure 1. The LTC2923’s data sheet outlines a simple 3-step procedure to choose resistor values for each of the supply behaviors shown in Figure 1. This procedure is described in the data sheet and reprinted in the sidebar here. The rest of this section covers a more in-depth analysis of the operation of the LTC2923. Examine the schematic shown in Figure 5, and assume that the DC/DC converter’s feedback voltage is 0.8V. Now, consider the case where VMASTER = 0V. Here, the current from the TRACK pin flows through RTA and R TB, which are both grounded. The tracking cell mirrors this same current at the FB pin. Because R TA = RFA and R TB = RFB, 0.8V is forced at the feedback node of the DC/DC converter. This Tracking and/or Sequencing Power Supplies is as Easy as 1, 2, 3 Any of the profiles shown in Figure 1 can be achieved by using the following simple design procedure. Figure 2 shows a basic three-supply application circuit. 1. Set the ramp rate of the master signal. Solve for the value of CGATE, the capacitor on the GATE pin, based on the desired ramp rate (V/s) of the master supply, SM. CGATE = IGATE where IGATE ≈ 10µA SM (1) If the external FET has a gate capacitance comparable to CGATE, then the external capacitor’s value should be reduced to compensate for the FET’s gate capacitance. If no external FET is used, tie the GATE and RAMP pins together. 2. Solve for the pair of resistors that provide the desired ramp rate of the slave supply, assuming no delay. Choose a ramp rate for the slave supply, SS. If the slave supply ramps up coincident with the master supply or with a fixed voltage offset, then the ramp rate equals the master supply’s ramp rate. Be sure to use a fast enough ramp rate for the slave supply so that it will finish ramping before the master supply has reached its final supply value. If not, the slave supply will be held below the intended regulation value by the master supply. Use the following formulas to determine the resistor values for the desired ramp rate, where RFB and RFA are the feedback resistors in the slave supply and VFB is the feedback reference voltage of the slave supply: 14 RTB = RFB • RTA ′ = VFB RFB SM SS (2) VTRACK V V + FB – TRACK RFA RTB (3) where VTRACK ≈ 0.8V. Note that large ratios of slave ramp rate to master ramp rate, SS/SM, may result in negative values for R TAʹ. If a sufficiently large delay is used in step 3, RTA will be positive, otherwise SS/SM must be reduced. 3. Choose R TA to obtain the desired delay. If no delay is required, such as in coincident and ratiometric tracking, then simply set R TA = R TAʹ. If a delay is desired, as in offset tracking and supply sequencing, calculate R TAʹʹ to determine the value of R TA where tD is the desired delay in seconds. RTA ′′ = VTRACK • RTB tD • SM RTA = RTA ′ || RTA ′′ (4) (5) the parallel combination of R TAʹ and R TAʹʹ As noted in step 2, small delays and large ratios of slave ramp rate to master ramp rate (usually only seen in sequencing) may result in solutions with negative values for R TA. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. Linear Technology Magazine • February 2004 DESIGN FEATURES results in an output voltage, VSLAVE, of 0V. Any voltage greater than 0V at the DC/DC converter’s output results in a feedback voltage greater than 0.8V causing the converter to drive its output towards 0V. So, with R TA = RFA and R TB = RFB, VSLAVE = 0V when VMASTER = 0V. Now, consider the case in Figure 6 where VMASTER = 2.5V, the nominal output voltage of the DC/DC converter. Without the LTC2923, the DC/DC converter’s feedback network drives 0.8V at its feedback node while generating an output voltage of 2.5V. Since R TA = RFA and R TB = RFB, the resistive divider formed by R TA and R TB forces 0.8V at the TRACK pin when VMASTER = 2.5V, without requiring any current from the tracking cell. Since the tracking cell only sources current, no current flows from the TRACK pin when VMASTER ≥ 2.5V. Therefore, when VMASTER is above 2.5V the DC/DC converter operates as if the tracking cell were not present. The relationship between VMASTER and VSLAVE is linear between 0V and 2.5V, so the fact that the DC/DC converter’s output is equal to VMASTER at 0V and at 2.5V means that VMASTER and VSLAVE are equal at all points in between. The DC/DC converter’s output tracks VMASTER exactly until VMASTER rises above 2.5V. When VMASTER is above 2.5V, no current flows from the FB pin and the tracking cell is effectively removed from the circuit. The fact that R TA = RFA and R TB = RFB in this example is not just a fortunate coincidence. For a DC/DC converter with a feedback voltage of 0.8V, setting the track resistors, R TA and R TB, equal to the feedback resistors, RFA and RFB causes the supplies to track together exactly. When the feedback voltage is not equal to 0.8V, only R TA needs to be adjusted, a result that is discussed below. RTB Configures the Ramp Rate The LTC2923 really shows flexibility when R TA ≠ RFA and/or R TB ≠ RFB. First consider the effects of R TB’s value. R TB configures the ramp rate of the slave supply. More accurately, Linear Technology Magazine • February 2004 RAMPED OUTPUT 3.3V (MASTER) Q1 BULK VIN 3.3V CGATE 3.3V RONB 154k GATE VCC ON RONA 100k FB1 LTC2923 TRACK1 RTA1 IN LTC1876 FB = 0.8V OUT RTB2 TRACK2 2.5V SLAVE1 RFA1 RFB1 8.25k 17.4k 3.3V RAMPBUF RTB1 IN LTC1876 FB = 0.8V OUT RAMP FB2 1.8V SLAVE2 GND RTA2 RFA2 8.06k RFB2 10k Figure 2. Typical coincident tracking application. The optional series FET is used to ramp the 3.3V bulk supply. MASTER 3.3V RONB 154k RONA 100k ON FB1 LTC2923 RTB2 887k RTA2 412k 3.3V IN DC/DC FB = 1.235V OUT VCC GATE RAMP 1.8V SLAVE1 RFA1 RFB1 35.7k 16.5k RAMPBUF RTB1 16.5k RTA1 13k CGATE 10nF 3.3V TRACK1 IN DC/DC FB = 0.8V OUT FB2 TRACK 2 2.5V SLAVE2 GND RFA2 412k RFB2 887k Figure 3. If the series FET is not used, the master signal is generated by tying a capacitor from the GATE and RAMP pins to ground. R TB configures the gain of the slave supply relative to the master supply and ultimately determines the ramp rate. Continuing with the example in Figure 5, as long as the track cell is regulating the TRACK pin at 0.8V (which is true for VMASTER < 2.5V), the current through R TA is fixed at 0.8/ R TA. Therefore, the current change in response to a voltage change at VMASTER is completely determined by R TB, as shown in Figure 7. Because one end VCC + MASTER RTB – TRACK + – 0.8V FB DC/DC FB OUT RTA RFA SLAVE RFB Figure 4. Simplified tracking cell 15 DESIGN FEATURES VCC + VMASTER 0V RTB 170k ITRACK RTA 80k IFB = 0.8V = R TA || R TB – + – DC/DC IFB FB TRACK 0.8V 0.8V VFB = 0.8V RTA = RFA RTB = RFB RFA 80k ITRACK = IFB VSLAVE 0V OUT FB ∆ITRACK = ∆VMASTER R TB (6) . This change in current is mirrored at the FB pin. Since the DC/DC converter regulates its feedback node to 0.8V, the voltage across RFA is fixed at 0.8V, and thus the current through RFA is also fixed. Any change in the current from the FB pin results in an equal change in the current across RFB. If R TB = RFB then any change in voltage at VMASTER results in an equal change in the voltage at the DC/DC converter’s output, VSLAVE. If RFB is increased relative to R TB the voltage change at VSLAVE is greater than the voltage change at VMASTER. The change in voltage at the DC/DC converter’s output is: ∆IFB • RFB = ∆ITRACK • R FB ∆VSLAVE RFB 170k ∆VSLAVE 10µA R FB = • . ∆t CGATE R TB Solving for R TA gives the exact value of R TA that compensates for the 1.2V feedback voltage as opposed to the 0.8V value. This value of R TA, the value that sets VSLAVE to track VMASTER with no delay, is represented by R TAʹ in the 3-step design procedure. RTA Configures an Offset As mentioned above, R TA is adjusted when a DC/DC converter’s feedback voltage is not equal to 0.8V. If, for example, the DC/DC converter’s feedback voltage is 1.2V, then the current from the FB pin, IFB, needed to hold the converter’s output at 0V is R TA not only compensates for the DC/DC converter’s feedback voltage, it serves an even broader purpose. It configures an offset voltage between VMASTER and VSLAVE. VCC + VMASTER 2.5V RTB 170k + – – ITRACK = 0 0.8V FB TRACK 0.8V RTA 80k (7) DC/DC IFB = 0 OUT FB 0.8V VFB = 0.8V RTA = RFA RTB = RFB RFA 80k VSLAVE 2.5V RFB 170k Figure 6. VSLAVE = 2.5V when VMASTER = 2.5V R FB R TB VCC This can be interpreted as a gain of RFB/R TB between the master signal and the output voltage. Because an external capacitor connected to the GATE pin programs the master supply’s ramp rate at: ∆VMASTER 10µA = , ∆t CGATE (9) RTA Corrects for Converter VREF ∆V = MASTER • R FB R TB = ∆VMASTER • (11) 0.8V 0.8V = R TA || R FB R FA || R FB Figure 5. IFB forces VSLAVE to 0V of the resistor R TB is fixed at 0.8V, the change in current from the TRACK pin is equal to (10) R TB = RFB still sets the gain between VMASTER and VTRACK to 1V/V. If VMASTER is at 0V, then ITRACK just barely holds VSLAVE at 0V when 0.8V 0.8V IFB = = R TA || R TB R FA || R FB 0.8V 1.2V R FA || R FB (8) ∆VMASTER RTB ∆VSLAVE = IFB • RFB ∆VMASTER RTB ∆IFB = ∆VMASTER ∆IRTB = RTB + – ITRACK + – = ∆VMASTER • 0.8V FB TRACK IFB = 0 0.8V RTA IRTA = 0.8V RTB ∆ITRACK = ∆VMASTER RTB IRFA = 0.8V RFA the ramp rate of the slave supply is: RFB RTB DC/DC FB OUT VSLAVE 2.5V RFB RFA Figure 7. RTB configures gain (ramp rate) 16 Linear Technology Magazine • February 2004 DESIGN FEATURES To demonstrate this, assume that R TA is reduced to 62kΩ so that R TA < RFA as shown in Figure 8. This creates the voltage profile shown in Figure 9. Compared to the previous example, more current flows from the TRACK pin when VMASTER is at ground. The output of the DC/DC converter remains at ground until VMASTER rises high enough to reduce the current from the TRACK pin to the level that just holds VSLAVE at 0V: ITRACK = IFB = 0.8V R FA || R FB ∆VMASTER 0.5V RTB 170k + 1.8µA ITRACK = 14.7µA 0.8V ∆VMASTER – 0.8V 0.8V − = 62kΩ 170kΩ 80kΩ || 170kΩ ∆VMASTER = 0.5V The gain between V SLAVE and VMASTER is still determined by RFB/R TB as VSLAVE ramps from 0V to 2.5V, and the voltage across R TA is still 0.8V, so the ramp rate does not vary with R TA. VSLAVE, however, does not rise above 0V until VMASTER reaches 0.5V in this example. In the 3-step design procedure, the slave supply is offset by R TA˝, the value of resistor that is placed in parallel with R TAʹ to produce the desired offset. RTA Configures a Delay Alternatively, the voltage offset generated by R TA may be interpreted as a time delay between the supplies. In the above example it was shown that VSLAVE remains at ground until VMASTER rises above 0.5V. Since the ramp-rate is 1000V/s and VSLAVE follows 0.5V below VMASTER, this can also be interpreted as a time delay of 0.5V = 0.5ms 1000V⁄s This representation is helpful when implementing supply sequencing. To sequence supplies, the slave supplies are ramped up at a faster rate than the master signal and each is delayed. By choosing the appropriate ramp rates and time delays, each supply is completely powered before the next supply ramps up. Multiple iterations Linear Technology Magazine • February 2004 – + – 0.8V FB TRACK RTA 62k DC/DC IFB = 14.7µA 0.8V FB OUT VFB = 0.8V VSLAVE 0V RFB, 170k 10µA 12.9µA RFA 80k 4.7µA VRFB = 0.8V Figure 8. RTA < RFA configures offset tracking (12) 0.8V ∆VMASTER – 0.8V 0.8V − = R FA || R FB R TA R TB TD = VCC may be necessary to find an acceptable solution since small delays combined with large slave ramp rate to master ramp rate ratios may result in negative values for R TA. Also, the chosen values for R TA and R TB must not require more than 1mA from the TRACK pin. In the 3-step design procedure this delay is achieved with R TA˝, the value of resistor that is placed in parallel with R TAʹ to produce the desired delay. Examples Now consider how varying R TA and R TB can produce each of the voltage tracking profiles in Figure 1. The schematic in Figure 2 uses an LTC1876 dual synchronous step-down converter to produce 2.5V and 1.8V supplies from a 3.3V input. An LTC2923 connected to the feedback nodes controls the rampup and ramp-down behavior of these supplies. In the following example, the 3-step design procedure outlined in the sidebar is followed. An external Si2306 MOSFET controls the behavior of the 3.3V supply with the ramp-rate determined by the capacitor on the GATE pin. Following Step 1 of the 3-Step design procedure, if a ramp-rate, SM, of 1000V/s is desired, equation (1) results in: Coincident Tracking Consider coincident tracking as shown in Figure 1a. We know from the above discussion that if the feedback voltage of the switching power supply is 0.8V, as it is on the LTC1876, then coincident tracking can be configured by setting the tracking resistors equal to the feedback resistors. In this case, RTA1 = RFA1 RTB1 = RFB1 RTA2 = RFA2 RTB2 = RFB2 Verify this conclusion by following Step 2 of the 3-Step Design Procedure. From equation (2): RTB1 = 17.4kΩ RTB2 = 10kΩ And from equation (3): RTA1´ = 8.25kΩ RTA2´ = 8.06kΩ As mentioned above, in the 3-step design procedure R TAʹ represents the value of R TA that produces no delay or offset. Since no delay is desired, R TA1 = R TA1ʹ and R TA2 = R TA2ʹ, and Step 3 of the Design Procedure is unnecessary. CGATE = 10nF If ramp-rate accuracy is critical then the external MOSFET’s gate capacitance should be subtracted from the CGATE capacitor’s value. If no MOSFET is used, tie the GATE and RAMP pins together and connect the CGATE capacitor between those pins and ground. 3.3V MASTER 2.5V SLAVE 1V/DIV 1ms/DIV Figure 9. Output profile of circuit in Figure 8 17 DESIGN FEATURES Ratiometric Tracking Now consider ratiometric tracking as seen in Figure 1b. Set the slave ramprates, SS1 and SS2: SS1 = 1000 V s • 2.5V 3.3V (13) = 758V/s ≈ 800V/s SS2 = 1000 V s • 1.8V 3.3V (14) = 545V/s ≈ 600V/s Round up the ramp-rates, SS1 and SS2, to 800V/s and 600V/s so that there is no chance of the 3.3V supply voltage holding the 2.5V or 1.8V supplies low after the ramp-up is complete. Solving equation (3) from Step 2 of the Design Procedure: RTB1 ≈ 21.5kΩ RTB2 ≈ 16.9kΩ This agrees with the intuitive expectation that R TB1 and R TB2 should be less than RFB1 and RFB2, because we desire gains of less than 1V/V between the master and the slave supplies. (Remember that the gain is RFB/R TB.) To complete Step 2, we must also solve for R TA1ʹ and R TA2ʹ using equation (3). RTA1´ ≈ 7.5kΩ RTA2´ ≈ 6.04kΩ Since no delay is desired, R TA1 = R TA1ʹ and R TA2 = R TA2ʹ and Step 3 is unnecessary. Offset Tracking In this example, the 2.5V supply ramps up 0.5V below the 3.3V supply, and the 1.8V supply ramps up 1V below the 3.3V supply, as shown in Figure 1c. In offset tracking, the ramp-rates are equal so the gain between the master and slave supplies is 1V/V. As in Step 1 of the coincident tracking example: RTB1 = RFB1 = 17.4kΩ RTB2 = RFB2 = 10kΩ Remember that R TA is used to configure the offsets. We know intuitively 18 that R TA1 and R TA2 should be smaller than in the coincident tracking example to generate offsets in the slave outputs. We already found that RTA1´ = RFA1 = 8.25kΩ RTA2´ = RFA2 = 8.06kΩ in the coincident tracking example above. Now we can use Step 3 of the Design Procedure to solve for R TA1 and R TA2 after converting the voltage offset to a time delay. V t D1 = OS1 SS1 = 0.5V/1000(V/s) = 0.5ms t D2 = VOS2 SS2 (15) (16) = 1V/1000(V/s) = 1ms From equation (4): RTA1˝ = 27.8kΩ RTA2˝ = 8kΩ Remember that R TA˝ is the value of resistor that is placed in parallel with R TAʹ to produce the desired offset. Therefore, R TA1 and R TA2 can be found from equation (5): RTA1 ≈ 6.34kΩ RTA2 ≈ 4.02kΩ Supply Sequencing To produce a voltage profile such as the one shown in Figure 1d, supply sequencing applications require the slaves to have fast ramp rates and time delays relative to the master. First, reducing the master signal ramp-rate to 100V/s using the equation from Step 1 of the Design Procedure results in: CGATE = 100nF Set the slave ramp rates to 500V/s in equation (2) to find RTB1 and R TB2: RTB1 = 3.48kΩ RTB2 = 2kΩ Intuitively, RFB/R TB should be 5 times greater than the previous examples since the gain from the master signal to the slave supply is now 5 times greater. Complete Step 2 by solving for R TA1ʹ and R TA2ʹ using equation (3). RTA1´ = –9.20kΩ RTA2´ = –3.62kΩ Step 3 adjusts R TA1 and R TA2 for the desired delays between the two supplies. In this case, factor in a delay of 20ms for the 2.5V supply relative to the master signal and a delay of 10ms for the 1.8V supply. RTA1˝ = 1.39kΩ RTA1 = RTA1´||RTA1˝ ≈ 1.65kΩ RTA2˝ = 1.6kΩ RTA2 = RTA2´||RTA2˝ ≈ 2.87kΩ Note that not every combination of ramp-rates and delays is possible. Small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. In such cases, either the delay must be increased or the ratio of slave ramp rate to the master ramp rate must be reduced. In addition, the chosen resistor values should not require more than 1mA to flow from the TRACK and FB pins. Therefore, confirm that less than 1mA flows from TRACK when VMASTER is at 0V. ITRACK1 = VTRACK R TA1 || R TB1 (17) = 0.718mA < 1mA ITRACK2 = VTRACK R TA 2 || R TB2 (18) = 0.679mA < 1mA Conclusion The LTC2923 simplifies power supply tracking and sequencing while offering superior performance in a smaller area than competing solutions. A few resistors can configure simple or complex supply behaviors. In most cases, series MOSFETs are eliminated along with their parasitic voltage drops and power consumption, but for those designs that require a series MOSFET, support is provided for one. The LTC2923 offers all of these features in a tiny MS10 or leadless 12-pin DFN package. Linear Technology Magazine • February 2004