FRX130D, FRX130R, FRX130H Radiation Hardened N-Channel Power MOSFETs April 1998 Features Description • 6A, 100V, rDS(ON) = 0.180Ω The Intersil has designed a series of SECOND GENERATION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from 100V to 500V, 1A to 60A, and on resistance as low as 25mΩ. Total dose hardness is offered at 100K RAD (Si) and 1000K RAD (Si) with neutron hardness ranging from 1E13n/cm2 for 500V product to 1E14n/cm2 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current limiting and 2E12 with current limiting. • Second Generation Rad Hard MOSFET Results From New Design Concepts • Gamma - Meets Pre-RAD Specifications to 100K RAD (Si) - Defined End-Point Specs at 300K RAD (Si) and 1000K RAD (Si) - Performance Permits Limited Use to 3000K RAD (Si) This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and neutron (no) exposures. Design and processing efforts are also directed to enhance survival to heavy ion (SEU) and/or dose rate (GAMMA DOT) exposure. • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 1.50nA Per-RAD (Si)/s Typically • Neutron This part may be supplied as a die or in various packages other than shown above. Reliability screening is available as either non TX (commercial), TX equivalent of MIL-S19500, TXV equivalent of MIL-S-19500, or space equivalent of MIL-S-19500. Contact the Intersil High-Reliability Marketing group for any desired deviations from the data sheet. - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Ordering Information PART NUMBER PACKAGE BRAND FRX130D1 18 Ld CLCC FRX130D1 FRX130D3 18 Ld CLCC FRX130D3 FRX130R1 18 Ld CLCC FRX130R1 FRX130R3 18 Ld CLCC FRX130R3 FRX130R4 18 Ld CLCC FRX130R4 FRX130H4 18 Ld CLCC FRX130H4 Symbol D G S Package 18 LEAD CLCC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 3144.3 FRX130D, FRX130R, FRX130H Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) FRX130D, R, H 100 100 6 4 18 ±20 11.4 4.5 0.09 18 6 18 -55 to 150 300 UNITS V V A A A V W W W/oC A A A oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - - V Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V 100 Gate Threshold Voltage VGS(TH) ID = 1mA, VDS = VGS 2.0 4.0 V Gate-Body Leakage Forward IGSSF VGS = +20V - 100 nA Gate-Body Leakage Reverse IGSSR VGS = -20V - 100 nA Zero Gate Voltage Drain Current IDSS1 IDSS2 IDSS3 VDS = 100V, VGS = 0 VDS = 80V, VGS = 0 VDS = 80V, VGS = 0, TC = 125oC - - 1 0.025 0.25 µA Time = 20µs - - 18 A Rated Avalanche Current IAR Drain to Source On-State Volts VDS(ON) VGS = 10V, ID = 6A - - 1.130 V Drain to Source On Resistance rDS(ON) VGS = 10V, ID = 4A - - 0.180 Ω td(ON) VDD = 50V, ID = 6A - - 30 Pulse Width = 3µs - - 100 Period = 300µs, Rg = 25Ω - - 200 0 ≤ VGS ≤ 10 (See Test Circuit) - - 100 Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time tr td(OFF) tf ns Gate-Charge Threshold Qg(TH) 1 - 4 Gate-Charge On State Qg(ON) 17 - 70 32 - 128 3 - 12 VDD = 50V, ID = 6A IGS1 = IGS2 0 ≤ VGS ≤ 20 nc Gate-Charge Total QgM Plateau Voltage VGP Gate-Charge Source QgS 3 - 14 Gate-Charge Drain QgD 8 - 32 Diode Forward Voltage VSD 0.6 - 1.8 V Reverse Recovery Time trr - - 400 ns - - 11 - - 250 Junction To Case RθJC Junction To Ambient RθJA V nc ID = 6A, VGD = 0 I = 6A; di/dt = 100A/µs Free Air Operation 2 oC/W FRX130D, FRX130R, FRX130H Typical Performance Curves Unless Otherwise Specified OPERATION IN THIS AREA IS LIMITED BY rDS(ON) ID, DRAIN (A) ID, DRAIN (A) 8 6 4 10 2 10ms FRX130 FRX130 0 100 50 CASE TEMPERATURE (TC) 50 VDS DRAIN-TO-SOURCE (V) FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 FIGURE 2. SAFE OPERATING AREA CURVE CASE TEMPERATURE = 25oC NORMALIZED rDS(ON) 80 ID, DRAIN (A) 50 30 20 4 500V RATED BVDSS 200V 3 100V 50V 2 FRX130 1E13 1E15 1E14 FLUENCE - NEUTRONS/cm2 100 500 TIME OF INDUCTIVE DISCHARGE (µs) FIGURE 4. NORMALIZED ON-RESISTANCE vs NEUTRON FLUENCE N-CHANNEL LIMITING INDUCTANCE (H) DRAIN CURRENT (A) FIGURE 3. TYPICAL UNCLAMPED INDUCTIVE SWITCHING FAILURE ONSET AVALANCHE MODE 100 10 1 1E-4 ILM = 10A ILM = 30A 1E-5 ILM = 100A ILM = 300A 1E-6 GAMMA DOT FRX130 1E8 1E9 30 1E10 100 300 DRAIN SUPPLY (V) GAMMA DOT - RAD (Si)/s FIGURE 5. TYPICAL PHOTO CURRENT vs GAMMA RATE FIGURE 6. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO ILM 3 FRX130D, FRX130R, FRX130H Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS 50Ω VDD 50V-150V DUT tP VDD + VGS ≤ 20V 0V VDS IAS 50Ω tAV FIGURE 7. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 8. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF tD(ON) tD(OFF) tR RL VDS tF 90% 90% VDS VGS = 12V 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 9. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 10. RESISTIVE SWITCHING WAVEFORMS 4 FRX130D, FRX130R, FRX130H 18 Pin CLCC 18 PIN CERAMIC LEADLESS CHIP CARRIER INCHES E SYMBOL R1 D R 1 2 NOTES 0.092 0.112 2.34 2.84 - b 0.020 0.030 0.51 0.76 - D 0.275 0.295 6.99 7.49 - D1 0.175 0.215 4.45 5.46 - D2 0.070 0.080 1.78 2.03 - E 0.340 0.360 8.64 9.14 - E1 0.240 0.280 6.10 7.11 - E2 0.095 0.105 2.42 2.66 - 0.050 BSC 1.27 BSC - L 0.085 0.115 2.16 2.92 - L1 0.035 0.055 0.89 1.39 - R 0.007 0.017 0.18 0.43 4 R1 0.003 0.013 0.08 0.33 4 2. All exposed metallized areas shall be plated with a minimum of 50 microinches of gold over nickel unless otherwise stated. 3. Metallized castellations shall be connected to the seating plane and extend upward toward top of package. 4. Corner shape (notch, radius, square, etc.) may vary at the manufacturer's option. 5. Unless otherwise specified, a minimum clearance of 0.010 inches (0.25mm) shall be maintained between all metallized areas. 6. Controlling dimension: Inch. 7. Revision 1 dated 6-93. e D1 MAX 1. No current JEDEC outline for this package. E2 D2 MILLIMETERS MIN NOTES: SEATING PLANE E1 MAX A e A MIN b L1 L ELEMENT PAD PINS CONNECTED GATE A 5 DRAIN B 1, 2, 3, 4, 16, 17, 18 SOURCE C 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 5