ISL98012 ® Data Sheet December 8, 2010 1.8V Input PWM Step-Up Regulator Features The ISL98012 is a high frequency, high efficiency step-up DC/DC regulator operated in fixed frequency PWM mode. With an integrated 1.4A MOSFET, it can deliver up to 600mA output current at up to 92% efficiency. The adjustable switching frequency is up to 750kHz, making it ideal for common boost applications. • Up to 92% Efficiency When shut down, it draws <1µA of current. This feature, along with the minimum starting voltage of 1.8V, makes it suitable for portable equipment powered by 1 Lithium Ion, 3 to 4 NiMH cells, or 2 cells of alkaline battery. The ISL98012 is available in a 10 Ld MSOP package, with a maximum height of 1.1mm. With proper external components, the whole converter takes less than 0.25in2 PCB space. This device is specified for operation over the full -40°C to +85°C temperature range. FN6654.1 • Up to 600mA IOUT • 4.5V < VOUT < 17V • 1.8V < VIN < 13.2V • Up to 750kHz Adjustable Frequency • <1µA Shutdown Current • Adjustable Soft-Start • Low Battery Detection • Internal Thermal Protection • 1.1mm Max Height 10 Ld MSOP Package • Pb-Free (RoHS compliant) Applications • 1.8V to 15V Converters - OLED Pinout • 5V to 12V Converters ISL98012 (10 LD MSOP) TOP VIEW • 3V to 5V and 3V to 12V Converters • TFT-LCD PGND 1 10 LX SGND 2 9 VDD RT 3 8 FB EN 4 7 SS LBI 5 6 LBO • Portable Equipment Ordering Information PART NUMBER (Note) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # ISL98012IUZ 98012 10 Ld MSOP M10.118A ISL98012IUZ-T* 98012 10 Ld MSOP M10.118A ISL98012IUZ-TK* 98012 10 Ld MSOP M10.118A *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL98012 Typical Application L1 VIN (1.8V TO 9V) D1 C1 5k 10µF 1 PGND 2 SGND 3 RT LX 10 VDD 9 FB 8 22µF C4 0.1µF R3 R2 113kΩ C3 56kΩ EN 1.8V TO 12V VOUT (15V UP TO 200mA) C5 R4 10µH 4 EN SS 7 5 LBI LBO 6 R1 C10 10kΩ 4.7nF 20nF 2 FN6654.1 December 8, 2010 ISL98012 Absolute Maximum Ratings (TA = +25°C) Thermal Information FB, SS, RT, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, 6.5V LX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +18V VDD, EN, LBI, LBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +12V Thermal Resistance (Typical, Note 1) θJA (°C/W) 10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature: . . . . . . . . . . . . . . . . . . . . . +135°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Maximum Operating Conditions Maximum Operating Frequency. . . . . . . . . . . . . . . . . . . . . . . 750kHz Minimum Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . 380kHz CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications . PARAMETER VIN = 5V, VOUT = 12V, L = 10µH, IOUT = 0mA, RT = 56kΩ, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT VIN Input Voltage Range R4 must ensure VDD ≤ 12V 1.8 13.2 V VOUT Output Voltage Range Note 2 4.5 17 V IQ1 Quiescent Current - Shut-down VEN = 0, feedback resistors disconnected 1 µA IQ2 Quiescent Current VEN = 2V, Continuous operation 1.4 2 mA VFB Feedback Voltage 1.33 1.37 V IFB Feedback Input Bias Current 0.10 µA DMAX Maximum Duty Cycle ILIM Current Limit - Max Peak Input Current IEN Enable Input Bias Current VLBI LBI Threshold Voltage VOL-LBO LBO Output Low ILEAK-LBO 1.29 0 < VFB < 1.5V 89.5 92 % 1 1.4 A 1 µA 220 250 mV ILBO = 1mA 0.1 0.2 V LBO Output Leakage Current VLBI = 250mV, VLBO = 5V 0.02 2 µA RDS(ON) Switch On Resistance At 12V output 220 ILEAK-SWITCH Switch Leakage Current LX = 18V 180 ΔVOUT/ΔVIN/VOUT Line Regulation 3V < VIN < 6V, VOUT = 12V, no load ΔVOUT/VOUT Load Regulation ISS mΩ 1 µA 0.4 %/V IOUT = 50mA to 150mA 1 % Soft Start Current 0 < VSS< 0.1V 12 µA VRT Voltage at RT for Bias Current RT = 56kΩ 1.34 V fOSC1 Switching Frequency RT = 56kΩ VHI_EN EN Input High Threshold VLO_EN EN Input Low Threshold 600 670 750 1.6 kHz V 0.5 V NOTE: 2. Minimum VOUT of 4.5V is tested with VIN = 1.8V. 3 FN6654.1 December 8, 2010 ISL98012 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1 PGND Power ground; connected to the source of internal N-Channel power MOSFET 2 SGND Signal ground; ground reference for all the control circuitry; needs to have only a single connection to PGND 3 RT Timing resistor to adjust the oscillation frequency of the converter. Resistor value on RT pin determines frequency. Range varies from RT = 49.9kΩ for 750kHz and RT = 100kΩ for 380kHz 4 EN Chip enable; connects to logic HI (>1.6V) for chip to function 5 LBI Low battery input; connects to a sensing voltage, or connect to GND if function is not used 6 LBO Low battery detection output; connected to the open drain of a MOSFET; able to sink 1mA current 7 SS Soft-start; connects to a capacitor to control the start-up of the converter. During start-up, VSS controls the current limit and hence the in-rush current. 8 FB Voltage feedback input; needs to connect to resistor divider to decide VO 9 VDD 10 LX Control circuit positive supply Inductor drive pin; connected to the drain of internal N-Channel power MOSFET Block Diagram VOUT = 15V 10µH 113k 10kΩ VIN 5kΩ 4.7nF 22µF 0.1µF FB 10µF VDD LX THERMAL SHUT-DOWN MAX_DUTY RT REFERENCE GENERATOR 56kΩ VREF VRAMP PWM LOGIC PWM COMPARATOR 0.2Ω EN LBO 12µA LBI + + START-UP OSCILLATOR ILOUT 80mΩ 7.2kΩ 220mV SGND SS PGND 20nF 4 FN6654.1 December 8, 2010 ISL98012 Typical Performance Curves 92 90 EFFICIENCY (%) EFFICIENCY (%) 90 80 VIN @ 3.3V 70 VIN @ 1.8V 88 86 84 82 60 0 50 100 150 200 IOUT (mA) 250 80 300 FIGURE 1. EFFICIENCY vs IOUT, VO = 15V 1.6 92 1.5 90 200 86 84 500 600 700 VDD = 10V, VO = 12V TO 17V CONTINUOUS MODE 1.3 1.2 1.1 82 1.0 80 0 100 200 300 400 500 0.9 300 600 400 IOUT (mA) FREQUENCY (kHz) FS (kHz) RT = 200kΩ 6 7 8 9 10 VDD (V) FIGURE 5. FS vs VDD 5 800 VDD = 10V RT = 100kΩ 5 700 80 RT = 71.5kΩ 200 600 FIGURE 4. IDD vs FS RT = 51.1kΩ 750 500 FREQUENCY (kHz) FIGURE 3. EFFICIENCY vs IOUT, VIN = 5V, VO = 12V 0 300 400 IOUT (mA) 1.4 88 IDD (mA) EFFICIENCY (%) 100 FIGURE 2. EFFICIENCY vs IOUT, VIN = 3.3V, VO = 5V 94 78 0 11 70 60 50 40 12 30 40 60 80 100 120 R (kΩ) FIGURE 6. FS vs RT FN6654.1 December 8, 2010 ISL98012 Typical Performance Curves (Continued) OUTPUT RIPPLE OUTPUT RIPPLE INPUT RIPPLE INPUT RIPPLE LX LX ILX ILX FIGURE 7. STEADY STATE OPERATION (INDUCTOR DISCONTINUOUS CONDUCTION), VIN = 3.3V, VO = 15V, IO < 1mA ΔVIN 50mV/DIV FIGURE 8. STEADY STATE OPERATION (INDUCTOR CONTINUOUS CONDUCTION), VIN = 3.3V, VO = 15V, IO = 30mA ΔVIN 50mV/DIV VLX 10V/DIV ΔVO 20mV/DIV 10V/DIV VLX 20mV/DIV ΔVO IL IL 0.5A/DIV 0.5A/DIV 1.0µs/DIV 1.0µs/DIV FIGURE 9. STEADY STATE OPERATION (INDUCTOR DISCONTINUOUS CONDUCTION), VIN = 5V, VO = 12V, IO = 30mA FIGURE 10. STEADY STATE OPERATION (INDUCTOR CONTINUOUS CONDUCTION), VIN = 5V, VO = 12V, IO = 300mA 2V/DIV 5V/DIV ΔVIN ILX VO 0.5A/DIV IL 0.5ms/DIV FIGURE 11. POWER-UP, VIN = 3.3V, VO = 15V, IO = 30mA 6 FIGURE 12. POWER-UP, VIN = 5V, VO = 12V, IO = 300mA FN6654.1 December 8, 2010 ISL98012 Typical Performance Curves (Continued) IO OUTPUT LOAD CURRENT 100mA/DIV ΔVO 0.5V/DIV 0.2ms/DIV FIGURE 13. LOAD TRANSIENT RESPONSE 10mA TO 30mA, VIN = 1.8V, FREQ = 56.2k, VO = 15V, IO = 10mA TO 30mA FIGURE 14. LOAD TRANSIENT RESPONSE, VIN = 5V, VO = 12V, IO = 50mA TO 300mA 10mV/DIV 10mV/DIV FIGURE 15. OUTPUT RIPPLE, VIN = 1.8V, VO = 15V, IO = 30mA Applications Information The ISL98012 is a fixed frequency step-up pulse-width modulation (PWM) regulator. The input voltage range is 1.8V to 13.2V and output voltage range is 4.5V to 17V. The switching frequency (up to 750kHz) is decided by the resistor connected to RT pin. Start-Up During start-up, as VDD reaches a threshold of about 1.6V, a start-up oscillator generates a fixed duty-ratio of 0.5 to 0.7 at a frequency of several hundred kHz. This will boost the output voltage. When VDD reaches about 3.7V, the PWM comparator takes over control. The duty ratio will be decided by the least of the multiple-input direct summing comparator, the Max_Duty signal (about 92% duty-ratio), or the Current Limit Comparator. 7 FIGURE 16. OUTPUT RIPPLE, VIN = 3.3V, VO = 15V, IO = 30mA Soft-start is provided by ramping up the current limit comparator. An internal 12µA current source charges the external CSS capacitor. The peak MOSFET current is limited by the voltage on this capacitor. This in turn controls the rising rate of the output voltage. The regulator goes through the same start-up sequence as well after the EN signal is pulled to HI. Steady-State Operation When the output reaches the preset voltage, the regulator operates in steady state. Depending on the input/output conditions and component values, the inductor operates in either continuous-conduction mode or discontinuous-conduction mode. In continuous-conduction mode, inductor current is a triangular waveform and LX voltage a pulse waveform. In discontinuous-conduction mode, inductor current has FN6654.1 December 8, 2010 ISL98012 completely dried out before the MOSFET is turned on again. The input voltage source, the inductor, and the MOSFET and output diode parasitic capacitors form a resonant circuit. Oscillation will occur in this period. This oscillation is normal and will not affect regulation. At very low load, the MOSFET will skip pulses sometimes; this is normal. Current Limit The MOSFET current limit is nominally 1.4A and guaranteed 1A. This restricts the maximum output current IOMAX based on Equation 1: V IN ΔI L I OMAX = ⎛ 1 – --------⎞ × --------⎝ 2 ⎠ VO (EQ. 1) where: The inductor has peak and average current decided by Equations 4 and 5: ΔI L I LPK = I LAVG + -------2 (EQ. 4) IO I LAVG = ------------1–D (EQ. 5) The inductor should be chosen to handle this current. Furthermore, due to fixed internal compensation, it is recommended that maximum inductance of 10µH and 15µH be used in the 5V and 12V or higher output voltage, respectively. The output diode has an average current of IO and peak current is the same as the inductor's peak current. A Schottky diode is recommended and it should be able to handle those currents. • ΔIL is the inductor peak-to-peak current ripple and is decided by Equation 2: The output voltage ripple can be calculated as Equation 6: V IN D ΔI L = --------- × ----L fS IO × D ΔV O = ---------------------- + I LPK × ESR FS × CO (EQ. 2) • D is the MOSFET turn-on ratio and is decided by Equation 3: V O – V IN D = -----------------------VO (EQ. 6) Where: (EQ. 3) • fS is the switching frequency Table1 gives typical values: TABLE 1. MAX CONTINUOUS OUTPUT CURRENTS • CO is the output capacitance. • The ESR is the output capacitor ESR value. Low ESR capacitors should be used to minimize output voltage ripple. Multilayer ceramic capacitors (X5R and X7R) are preferred for output capacitors since they have a low ESR and small packages. Tantalum capacitors also can be used, but they take more board space and have higher ESR. A minimum of 22µF output capacitor is sufficient for high output current application. For lower output current, the output capacitor can be smaller, like 4.7µF. The capacitor should always have enough voltage rating. In addition to the voltage rating, the output capacitor should also be able to handle the RMS current, which is given by Equation 7: VIN (V) VO (V) L (µH) fS (kHz) IOMAX (mA) 2 5 10 750 360 2 9 10 750 190 2 12 10 750 140 3.3 5 10 750 600 3.3 9 10 750 310 3.3 12 10 750 230 5 9 10 750 470 Output Voltage 5 12 10 750 340 9 12 10 750 630 12 15 10 750 670 An external resistor divider is required to divide the output voltage down to the nominal reference voltage. The current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network less than 300kΩ is recommended. Component Considerations It is recommended that CIN is larger than 10µF. Theoretically, the input capacitor has a ripple current of ΔIL. Due to high-frequency noise in the circuit, the input current ripple may exceed the theoretical value. A larger capacitor will reduce the ripple further. 8 I CORMS = 2 ⎛ ⎞ ΔI L 1 ( 1 – D ) × ⎜ D + -------------------- × ------ ⎟ × I LAVG ⎜ 2 12 ⎟ I LAVG ⎝ ⎠ (EQ. 7) FN6654.1 December 8, 2010 ISL98012 The boost converter output voltage is determined by the relationship in Equation 8: R 2⎞ ⎛ V OUT = V FB × ⎜ 1 + -------⎟ R 1⎠ ⎝ (EQ. 8) where VFB slightly changes with VDD. RC Filter The maximum voltage rating for the VDD pin is 12V. An RC filter is recommended to clean the output ripple before bootstrapping the part. For bootstrapped applications with VOUT greater than 10V, R4 can drop VOUT for coupling into the VDD pin and is given by Equation 9: V O – 10 R 4 = --------------------I DD (EQ. 9) where IDD is shown in the IDD vs fS curve. Otherwise, R4 can be 10Ω to 51Ω with C4 = 0.1µF. Thermal Performance The ISL98012 uses a fused-lead package, which has a reduced θJA of +100°C/W on a four-layer board and +115°C/W on a two-layer board. Maximizing copper around the ground pins will improve the thermal performance. Layout Considerations The layout is very important for the converter to function properly. power ground ( ) and signal ground ( ) should be separated to ensure that the high pulse current in the power ground never interferes with the sensitive signals connected to signal ground. They should only be connected at one point. The trace connected to pin 8 (FB) is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the SGND pin. Maximizing the copper area around it is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on these principles. Please refer to the ISL98012 Technical Brief for the layout. http://www.intersil.com/data/tb/tb429.pdf This chip also has internal thermal shut-down set at around +135°C to protect the component. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6654.1 December 8, 2010 ISL98012 Package Outline Drawing M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0 ± 0.1 A 0.25 10 DETAIL "X" CAB 0.18 ± 0.05 SIDE VIEW 2 4.9 ± 0.15 3.0 ± 0.1 1.10 Max B PIN# 1 ID 1 2 0.95 BSC 0.5 BSC TOP VIEW Gauge Plane 0.86 ± 0.09 H 0.25 C 3°±3° SEATING PLANE 0.10 ± 0.05 0.23 +0.07/ -0.08 0.08 C A B 0.55 ± 0.15 0.10 C DETAIL "X" SIDE VIEW 1 5.80 4.40 3.00 NOTES: 0.50 0.30 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. 4. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L. 10 FN6654.1 December 8, 2010